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Lucas Russo authored
Using VHDL dor DDR core issues an error. No idea when that happens, unless re-target my project for Verilog and regenerate the DDR core.
2d242771
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artix7 | ||
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virtex6 | ||
Manifest.py |
Using VHDL dor DDR core issues an error. No idea when that happens, unless re-target my project for Verilog and regenerate the DDR core.
Name |
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artix7 | Loading commit data... | |
kintex7 | Loading commit data... | |
virtex6 | Loading commit data... | |
Manifest.py | Loading commit data... |