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Beam Positoning Monitor - Gateware
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hdl/platform/artix7/*: add AXI4-Stream 2-to-1 muxer
· b5ae2a89
Lucas Russo
authored
Nov 04, 2014
This will be the base (for now, at least) for the multiplexed acquisition core.
b5ae2a89
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Manifest.py
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axis_interconnect_v1_1_arb_rr.v
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axis_interconnect_v1_1_axis_clock_converter.v
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axis_interconnect_v1_1_axis_data_fifo.v
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axis_interconnect_v1_1_axis_dwidth_converter.v
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axis_interconnect_v1_1_axis_infrastructure.vh
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axis_interconnect_v1_1_axis_interconnect.v
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axis_interconnect_v1_1_axis_interconnect_16x16_top.v
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axis_interconnect_v1_1_axis_register_slice.v
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axis_interconnect_v1_1_axis_subset_converter.v
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axis_interconnect_v1_1_axis_switch.v
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axis_interconnect_v1_1_axis_switch_arbiter.v
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axis_interconnect_v1_1_axisc_arb_responder.v
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axis_interconnect_v1_1_axisc_decoder.v
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axis_interconnect_v1_1_axisc_downsizer.v
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axis_interconnect_v1_1_axisc_register_slice.v
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axis_interconnect_v1_1_axisc_sample_cycle_ratio.v
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axis_interconnect_v1_1_axisc_sync_clock_converter.v
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axis_interconnect_v1_1_axisc_transfer_mux.v
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axis_interconnect_v1_1_axisc_upsizer.v
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axis_interconnect_v1_1_dynamic_datapath.v
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axis_interconnect_v1_1_dynamic_priority_encoder.v
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axis_interconnect_v1_1_mux_enc.v
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axis_interconnect_v1_1_util_aclken_converter.v
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axis_interconnect_v1_1_util_aclken_converter_wrapper.v
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axis_interconnect_v1_1_util_axis2vector.v
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axis_interconnect_v1_1_util_vector2axis.v
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