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Beam Positoning Monitor - Software
Commit 569e9e37 authored by Lucas Russo's avatar Lucas Russo
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include,boards: add afcv3_1 board target 

The only difference from AFCv3 is the
EEPROM address, which is correct (0x50 and 0x52
for the FMC1 and FMC2 slots, respectively) in this
version.
parent cfd3e8bf
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include/boards/afcv3_1/acq_chan.h 0 → 100644
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#ifndef _ACQ_CHAN_H_
#define _ACQ_CHAN_H_
#include <acq_chan_gen_defs.h>
#define NUM_ACQ_CORE_SMIOS 2
/************************ Acquistion 0 Channel Parameters **************/
/* ADC */
#define ADC0_CHAN_ID 0
#define ADC0_SAMPLE_SIZE 8 /* 8 Bytes -> ADC0 = 16-bit / ADC1 = 16-bit ... */
/* ADC SWAPPED (after the switching module) */
#define ADCSWAP0_CHAN_ID (ADC0_CHAN_ID + 1)
#define ADCSWAP0_SAMPLE_SIZE 8 /* 8 Bytes -> ADCSWAP0 = 16-bit / ADCSWAP1 = 16-bit ... */
/* MIXER I/Q 1/2 */
#define MIXIQ120_CHAN_ID (ADCSWAP0_CHAN_ID + 1)
#define MIXIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> MIXI0 = 32-bit / MIXQ0 = 32-bit ... */
/* MIXER I/Q 3/4 */
#define MIXIQ340_CHAN_ID (MIXIQ120_CHAN_ID + 1)
#define MIXIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> MIXI2 = 32-bit / MIXQ2 = 32-bit ... */
/* TBTDECIM I/Q 1/2 */
#define TBTDECIMIQ120_CHAN_ID (MIXIQ340_CHAN_ID + 1)
#define TBTDECIMIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> TBTDECIM0 = 32-bit / TBTDECIM1 = 32-bit ... */
/* TBTDECIM I/Q 3/4 */
#define TBTDECIMIQ340_CHAN_ID (TBTDECIMIQ120_CHAN_ID + 1)
#define TBTDECIMIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> TBTDECIM0 = 32-bit / TBTDECIM1 = 32-bit ... */
/* TBT AMP */
#define TBTAMP0_CHAN_ID (TBTDECIMIQ340_CHAN_ID + 1)
#define TBTAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> TBTAMP0 = 32-bit / TBTAMP1 = 32-bit ... */
/* TBT PHASE */
#define TBTPHA0_CHAN_ID (TBTAMP0_CHAN_ID + 1)
#define TBTPHA0_SAMPLE_SIZE 16 /* 16 Bytes -> TBTPHA0 = 32-bit / TBTPHA1 = 32-bit ... */
/* TBT POS */
#define TBTPOS0_CHAN_ID (TBTPHA0_CHAN_ID + 1)
#define TBTPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* FOFBDECIM I/Q 1/2 */
#define FOFBDECIMIQ120_CHAN_ID (TBTPOS0_CHAN_ID + 1)
#define FOFBDECIMIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBDECIM0 = 32-bit / FOFBDECIM1 = 32-bit ... */
/* FOFBDECIM I/Q 3/4 */
#define FOFBDECIMIQ340_CHAN_ID (FOFBDECIMIQ120_CHAN_ID + 1)
#define FOFBDECIMIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBDECIM0 = 32-bit / FOFBDECIM1 = 32-bit ... */
/* FOFB AMP */
#define FOFBAMP0_CHAN_ID (FOFBDECIMIQ340_CHAN_ID + 1)
#define FOFBAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBAMP0 = 32-bit / FOFBAMP1 = 32-bit ... */
/* FOFB PHA */
#define FOFBPHA0_CHAN_ID (FOFBAMP0_CHAN_ID + 1)
#define FOFBPHA0_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBPHA0 = 32-bit / FOFBPHA1 = 32-bit ... */
/* FOFB POS */
#define FOFBPOS0_CHAN_ID (FOFBPHA0_CHAN_ID + 1)
#define FOFBPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT AMP */
#define MONITAMP0_CHAN_ID (FOFBPOS0_CHAN_ID + 1)
#define MONITAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> MONITAMP0 = 32-bit / MONITAMP1 = 32-bit ... */
/* MONIT POS */
#define MONITPOS0_CHAN_ID (MONITAMP0_CHAN_ID + 1)
#define MONITPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT1 POS */
#define MONIT1POS0_CHAN_ID (MONITPOS0_CHAN_ID + 1)
#define MONIT1POS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* End of channels placeholder */
#define END_CHAN_ID (MONIT1POS0_CHAN_ID + 1)
#endif
include/boards/afcv3_1/board.h 0 → 100644
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#ifndef _BOARD_H_
#define _BOARD_H_
#include "defs.h"
/****************************/
/* General Definitions */
/****************************/
/* CPU Clock frequency in hertz */
#define SYS_CLOCK 100000000ULL
/* Baud rate of the builtin UART (does not apply to the VUART) */
#define UART_BAUDRATE 115200ULL
int board_init();
int board_update();
#endif
include/boards/afcv3_1/chips_addr.h 0 → 100644
View file @ 569e9e37
/*
* Copyright (C) 2015 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _CHIPS_ADDR_H_
#define _CHIPS_ADDR_H_
extern const uint32_t fmc130m_4ch_si571_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_ad9510_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_24aa64_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM75A];
extern const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS];
#endif
include/boards/afcv3_1/ddr3_defs.h 0 → 100644
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#ifndef _DDR3_DEFS_H_
#define _DDR3_DEFS_H_
#ifdef __SHRINK_AFCV3_DDR_SIZE__
#define MEM_TOTAL_SIZE (1ULL << 28) /* 256 MB reserved for position storage */
#else
#define MEM_TOTAL_SIZE (1ULL << 31) /* 2 GB reserved for position storage */
#endif
#define MEM_REGION_SIZE (MEM_TOTAL_SIZE / 16)
/* FPGA Specific */
#define DDR3_PAYLOAD_SIZE 32 /* In Bytes: Artix7 (AFCv3) */
/* DDR3 Specific */
/* DDR3 for AFCv3 has a 32-bit interface */
#define DDR3_DATA_WIDTH 32 /* In Bits */
#define DDR3_BYTE_2_BIT 8
#define DDR3_ADDR_WORD_2_BYTE (DDR3_DATA_WIDTH/DDR3_BYTE_2_BIT)
#endif
include/boards/afcv3_1/ddr3_map.h 0 → 100644
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include/boards/afcv3_1/defs.h 0 → 100644
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#ifndef _DEFS_H_
#define _DEFS_H_
#include "ddr3_defs.h"
#include "ddr3_map.h"
#include "mem_layout.h"
#endif
include/boards/afcv3_1/mem_layout.h 0 → 100644
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#ifndef _MEM_LAYOUT_H_
#define _MEM_LAYOUT_H_
#include "pcie_regs.h"
#include "acq_chan.h"
#define NUM_MAX_SLOTS 12
#define NUM_MAX_BPM_PER_SLOT 2
#define NUM_MAX_BPMS (NUM_MAX_SLOTS * NUM_MAX_BPM_PER_SLOT)
#define NUM_FMC130M_4CH_SMIOS 2
/*********************** Static AFCv3 FPGA layout ***********************/
/* FMC_130M Components */
#define FMC_130M_CTRL_RAW_REGS_OFFS 0x0000
#define FMC_130M_SI571_RAW_I2C_OFFS 0x0100
#define FMC_130M_AD9510_RAW_SPI_OFFS 0x0200
#define FMC_130M_EEPROM_RAW_I2C_OFFS 0x0300
#define FMC_130M_LM75A_RAW_I2C_OFFS 0x0400
/* DSP Components */
#define DSP_CTRL_RAW_REGS_OFFS 0x0000
#define DSP_BPM_RAW_SWAP_OFFS 0x0100
/* AFC DIAG Components */
#define WB_AFC_DIAG_CTRL_RAW_REGS_OFFS 0x0000
/* ACQ Components */
#define WB_ACQ_CORE_CTRL_RAW_REGS_OFFS 0x0000
/* Should be autodiscovered by SDB */
/* Wishbone RAW Addresses */
#define FMC1_130M_BASE_RAW_ADDR 0x00310000
#define FMC1_130M_CTRL_RAW_REGS (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC1_130M_SI571_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_SI571_RAW_I2C_OFFS)
#define FMC1_130M_AD9510_RAW_SPI (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC1_130M_EEPROM_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC1_130M_LM75A_RAW_I2C (FMC1_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ1_BASE_RAW_ADDR 0x00330000
#define FMC2_130M_BASE_RAW_ADDR 0x00350000
#define FMC2_130M_CTRL_RAW_REGS (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC2_130M_SI571_RAW_I2C (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_SI571_RAW_I2C_OFFS)
#define FMC2_130M_AD9510_RAW_SPI (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC2_130M_EEPROM_RAW_I2C (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC2_130M_LM75A_RAW_I2C (FMC2_130M_BASE_RAW_ADDR + \
FMC_130M_LM75A_RAW_I2C_OFFS)
#define DSP2_BASE_RAW_ADDR 0x00340000
#define DSP2_CTRL_RAW_REGS (DSP2_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP2_BPM_RAW_SWAP (DSP2_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ2_BASE_RAW_ADDR 0x00360000
#define WB_PERIPH_RAW_ADDR 0x00370000
#define WB_AFC_DIAG_RAW_ADDR 0x00380000
#define WB_AFC_DIAG_CTRL_RAW_REGS (WB_AFC_DIAG_RAW_ADDR + \
WB_AFC_DIAG_CTRL_RAW_REGS_OFFS)
/* Large Memory RAW Addresses. It lives at address 0 */
#define LARGE_MEM_RAW_ADDR 0x00000000
/* The following is a bit of a hack.
* We employ a generic API for talking to the hardware.
* So, our transport layer (PCIe or Ethernet, for now)
* should be invisible to the SMIO instances.
*
* However, PCI devices generally employ multiple BAR
* registers mapped to different parts of the device.
* For instance, in the bpm-gw FPGA firmware, the PCIe
* core has 3 BARs (BAR0, BAR2 and BAR4) mapped to the
* following:
*
* BAR0 -> PCIe control registers
* BAR2 -> DDR3 SDRAM
* BAR4 -> Wishbone (necessary to use pages mechanism)
*
* So, we define our addresses as the logic address plus
* the BAR number. With this, the PCIe transport layer
* can differentiate between multiple bars and select
* the correct one to read or write
*/
/* FMC_130M Components */
#define FMC_130M_CTRL_REGS_OFFS (BAR4_ADDR | FMC_130M_CTRL_RAW_REGS_OFFS)
#define FMC_130M_SI571_I2C_OFFS (BAR4_ADDR | FMC_130M_SI571_RAW_I2C_OFFS)
#define FMC_130M_AD9510_SPI_OFFS (BAR4_ADDR | FMC_130M_AD9510_RAW_SPI_OFFS)
#define FMC_130M_EEPROM_I2C_OFFS (BAR4_ADDR | FMC_130M_EEPROM_RAW_I2C_OFFS)
#define FMC_130M_LM75A_I2C_OFFS (BAR4_ADDR | FMC_130M_LM75A_RAW_I2C_OFFS)
/* DSP Components */
#define DSP_CTRL_REGS_OFFS (BAR4_ADDR | DSP_CTRL_RAW_REGS_OFFS)
#define DSP_BPM_SWAP_OFFS (BAR4_ADDR | DSP_BPM_RAW_SWAP_OFFS)
/* ACQ Components */
#define WB_ACQ_CORE_CTRL_REGS_OFFS (BAR4_ADDR | WB_ACQ_CORE_CTRL_RAW_REGS_OFFS)
/* Wishbone Addresses */
#define FMC1_130M_BASE_ADDR (BAR4_ADDR | FMC1_130M_BASE_RAW_ADDR)
#define FMC1_130M_CTRL_REGS (BAR4_ADDR | FMC1_130M_CTRL_RAW_REGS)
#define FMC1_130M_SI571_I2C (BAR4_ADDR | FMC1_130M_SI571_RAW_I2C)
#define FMC1_130M_AD9510_SPI (BAR4_ADDR | FMC1_130M_AD9510_RAW_SPI)
#define FMC1_130M_EEPROM_I2C (BAR4_ADDR | FMC1_130M_EEPROM_RAW_I2C)
#define FMC1_130M_LM75A_I2C (BAR4_ADDR | FMC1_130M_LM75A_RAW_I2C)
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define WB_ACQ1_BASE_ADDR (BAR4_ADDR | WB_ACQ1_BASE_RAW_ADDR)
#define FMC2_130M_BASE_ADDR (BAR4_ADDR | FMC2_130M_BASE_RAW_ADDR)
#define FMC2_130M_CTRL_REGS (BAR4_ADDR | FMC2_130M_CTRL_RAW_REGS)
#define FMC2_130M_SI571_I2C (BAR4_ADDR | FMC2_130M_SI571_RAW_I2C)
#define FMC2_130M_AD9510_SPI (BAR4_ADDR | FMC2_130M_AD9510_RAW_SPI)
#define FMC2_130M_EEPROM_I2C (BAR4_ADDR | FMC2_130M_EEPROM_RAW_I2C)
#define FMC2_130M_LM75A_I2C (BAR4_ADDR | FMC2_130M_LM75A_RAW_I2C)
#define DSP2_BASE_ADDR (BAR4_ADDR | DSP2_BASE_RAW_ADDR)
#define DSP2_CTRL_REGS (BAR4_ADDR | DSP2_CTRL_RAW_REGS)
#define DSP2_BPM_SWAP (BAR4_ADDR | DSP2_BPM_RAW_SWAP)
#define WB_ACQ2_BASE_ADDR (BAR4_ADDR | WB_ACQ2_BASE_RAW_ADDR)
#define WB_PERIPH_BASE_ADDR (BAR4_ADDR | WB_PERIPH_RAW_ADDR)
#define WB_AFC_DIAG_BASE_ADDR (BAR4_ADDR | WB_AFC_DIAG_RAW_ADDR)
#define WB_AFC_DIAG_CTRL_REGS (BAR4_ADDR | WB_AFC_DIAG_CTRL_RAW_REGS)
/* Large Memory Addresses */
#define LARGE_MEM_ADDR (BAR2_ADDR | LARGE_MEM_RAW_ADDR)
/************************* AFCv3 Gateware Options *************************/
/********************* FMC130M_4CH SMIO Gateware Options ******************/
/* Chip SPI slave select lines and I2C address */
#define NUM_FMC130M_4CH_LM75A 2
extern const uint32_t fmc130m_4ch_si571_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_ad9510_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_24aa64_addr[NUM_FMC130M_4CH_SMIOS];
extern const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM75A];
extern const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS];
/*********************** SMIO ACQ Gateware Options ***********************/
/* FIXME: The Gateware does not support yet a way of reading which
* ACQ channels are valid. So, we hardcoded it here for now. This issue
* should be addressed soon */
/* We define 10 Channels: ADC 1, TBT AMP 1, TBT POS 1, FOFB AMP 1, FOFB POS 1,
* ADC 2, TBT AMP 2, TBT POS 2, FOFB AMP 2, FOFB POS 2 */
#define SMIO_ACQ_NUM_CHANNELS END_CHAN_ID
#endif
src/boards/afcv3_1/board.mk 0 → 100644
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board_DIR = $(SRC_DIR)/boards/afcv3_1
board_OBJS = $(board_DIR)/epics_mapping.o \
$(board_DIR)/ddr3_map.o \
$(board_DIR)/chips_addr.o
src/boards/afcv3_1/chips_addr.c 0 → 100644
View file @ 569e9e37
/*
* Copyright (C) 2015 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
const uint32_t fmc130m_4ch_si571_addr[NUM_FMC130M_4CH_SMIOS] = {0x49, 0x49};
const uint32_t fmc130m_4ch_ad9510_addr[NUM_FMC130M_4CH_SMIOS] = {0x01, 0x01};
const uint32_t fmc130m_4ch_24aa64_addr[NUM_FMC130M_4CH_SMIOS] = {0x50, 0x52};
const uint32_t fmc130m_4ch_lm75a_addr[NUM_FMC130M_4CH_SMIOS][NUM_FMC130M_4CH_LM75A] = {
{0x48, 0x49},
{0x48, 0x49},
};
/* This CI PCA9547 is located on the carrier, but it's controlled by the FMC130M_4CH */
const uint32_t fmc130m_4ch_pca9547_addr[NUM_FMC130M_4CH_SMIOS] = {0x70, 0x70};
src/boards/afcv3_1/ddr3_map.c 0 → 100644
View file @ 569e9e37
/*
* Copyright (C) 2014 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include <czmq.h>
#include "acq_chan_gen_defs.h"
#include "board.h"
#include "ddr3_map.h"
#include "ddr3_map_structs.h"
const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
/*** Acquisition Core 0 Channel Parameters ***/
{
{
.id = ADC0_CHAN_ID,
.start_addr = DDR3_ADC0_START_ADDR,
.end_addr = DDR3_ADC0_END_ADDR,
.max_samples = DDR3_ADC0_MAX_SAMPLES,
.sample_size = DDR3_ADC0_SAMPLE_SIZE
},
{
.id = ADCSWAP0_CHAN_ID,
.start_addr = DDR3_ADCSWAP0_START_ADDR,
.end_addr = DDR3_ADCSWAP0_END_ADDR,
.max_samples = DDR3_ADCSWAP0_MAX_SAMPLES,
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
},
{
.id = MIXIQ120_CHAN_ID,
.start_addr = DDR3_MIXIQ120_START_ADDR,
.end_addr = DDR3_MIXIQ120_END_ADDR,
.max_samples = DDR3_MIXIQ120_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ120_SAMPLE_SIZE
},
{
.id = MIXIQ340_CHAN_ID,
.start_addr = DDR3_MIXIQ340_START_ADDR,
.end_addr = DDR3_MIXIQ340_END_ADDR,
.max_samples = DDR3_MIXIQ340_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ340_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ120_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ120_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ120_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ120_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ120_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ340_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ340_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ340_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ340_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ340_SAMPLE_SIZE
},
{
.id = TBTAMP0_CHAN_ID,
.start_addr = DDR3_TBTAMP0_START_ADDR,
.end_addr = DDR3_TBTAMP0_END_ADDR,
.max_samples = DDR3_TBTAMP0_MAX_SAMPLES,
.sample_size = DDR3_TBTAMP0_SAMPLE_SIZE
},
{
.id = TBTPHA0_CHAN_ID,
.start_addr = DDR3_TBTPHA0_START_ADDR,
.end_addr = DDR3_TBTPHA0_END_ADDR,
.max_samples = DDR3_TBTPHA0_MAX_SAMPLES,
.sample_size = DDR3_TBTPHA0_SAMPLE_SIZE
},
{
.id = TBTPOS0_CHAN_ID,
.start_addr = DDR3_TBTPOS0_START_ADDR,
.end_addr = DDR3_TBTPOS0_END_ADDR,
.max_samples = DDR3_TBTPOS0_MAX_SAMPLES,
.sample_size = DDR3_TBTPOS0_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ120_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ120_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ120_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ120_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ120_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ340_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ340_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ340_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ340_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ340_SAMPLE_SIZE
},
{
.id = FOFBAMP0_CHAN_ID,
.start_addr = DDR3_FOFBAMP0_START_ADDR,
.end_addr = DDR3_FOFBAMP0_END_ADDR,
.max_samples = DDR3_FOFBAMP0_MAX_SAMPLES,
.sample_size = DDR3_FOFBAMP0_SAMPLE_SIZE
},
{
.id = FOFBPHA0_CHAN_ID,
.start_addr = DDR3_FOFBPHA0_START_ADDR,
.end_addr = DDR3_FOFBPHA0_END_ADDR,
.max_samples = DDR3_FOFBPHA0_MAX_SAMPLES,
.sample_size = DDR3_FOFBPHA0_SAMPLE_SIZE
},
{
.id = FOFBPOS0_CHAN_ID,
.start_addr = DDR3_FOFBPOS0_START_ADDR,
.end_addr = DDR3_FOFBPOS0_END_ADDR,
.max_samples = DDR3_FOFBPOS0_MAX_SAMPLES,
.sample_size = DDR3_FOFBPOS0_SAMPLE_SIZE
},
{
.id = MONITAMP0_CHAN_ID,
.start_addr = DDR3_MONITAMP0_START_ADDR,
.end_addr = DDR3_MONITAMP0_END_ADDR,
.max_samples = DDR3_MONITAMP0_MAX_SAMPLES,
.sample_size = DDR3_MONITAMP0_SAMPLE_SIZE
},
{
.id = MONITPOS0_CHAN_ID,
.start_addr = DDR3_MONITPOS0_START_ADDR,
.end_addr = DDR3_MONITPOS0_END_ADDR,
.max_samples = DDR3_MONITPOS0_MAX_SAMPLES,
.sample_size = DDR3_MONITPOS0_SAMPLE_SIZE
},
{
.id = MONIT1POS0_CHAN_ID,
.start_addr = DDR3_MONIT1POS0_START_ADDR,
.end_addr = DDR3_MONIT1POS0_END_ADDR,
.max_samples = DDR3_MONIT1POS0_MAX_SAMPLES,
.sample_size = DDR3_MONIT1POS0_SAMPLE_SIZE
}
},
/*** Acquisition Core 1 Channel Parameters ***/
{
{
.id = ADC0_CHAN_ID,
.start_addr = DDR3_ADC1_START_ADDR,
.end_addr = DDR3_ADC1_END_ADDR,
.max_samples = DDR3_ADC1_MAX_SAMPLES,
.sample_size = DDR3_ADC0_SAMPLE_SIZE
},
{
.id = ADCSWAP0_CHAN_ID,
.start_addr = DDR3_ADCSWAP1_START_ADDR,
.end_addr = DDR3_ADCSWAP1_END_ADDR,
.max_samples = DDR3_ADCSWAP1_MAX_SAMPLES,
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
},
{
.id = MIXIQ120_CHAN_ID,
.start_addr = DDR3_MIXIQ121_START_ADDR,
.end_addr = DDR3_MIXIQ121_END_ADDR,
.max_samples = DDR3_MIXIQ121_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ120_SAMPLE_SIZE
},
{
.id = MIXIQ340_CHAN_ID,
.start_addr = DDR3_MIXIQ341_START_ADDR,
.end_addr = DDR3_MIXIQ341_END_ADDR,
.max_samples = DDR3_MIXIQ341_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ340_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ120_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ121_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ121_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ121_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ120_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ340_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ341_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ341_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ341_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ340_SAMPLE_SIZE
},
{
.id = TBTAMP0_CHAN_ID,
.start_addr = DDR3_TBTAMP1_START_ADDR,
.end_addr = DDR3_TBTAMP1_END_ADDR,
.max_samples = DDR3_TBTAMP1_MAX_SAMPLES,
.sample_size = DDR3_TBTAMP0_SAMPLE_SIZE
},
{
.id = TBTPHA0_CHAN_ID,
.start_addr = DDR3_TBTPHA1_START_ADDR,
.end_addr = DDR3_TBTPHA1_END_ADDR,
.max_samples = DDR3_TBTPHA1_MAX_SAMPLES,
.sample_size = DDR3_TBTPHA0_SAMPLE_SIZE
},
{
.id = TBTPOS0_CHAN_ID,
.start_addr = DDR3_TBTPOS1_START_ADDR,
.end_addr = DDR3_TBTPOS1_END_ADDR,
.max_samples = DDR3_TBTPOS1_MAX_SAMPLES,
.sample_size = DDR3_TBTPOS0_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ120_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ121_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ121_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ121_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ120_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ340_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ341_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ341_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ341_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ340_SAMPLE_SIZE
},
{
.id = FOFBAMP0_CHAN_ID,
.start_addr = DDR3_FOFBAMP1_START_ADDR,
.end_addr = DDR3_FOFBAMP1_END_ADDR,
.max_samples = DDR3_FOFBAMP1_MAX_SAMPLES,
.sample_size = DDR3_FOFBAMP0_SAMPLE_SIZE
},
{
.id = FOFBPHA0_CHAN_ID,
.start_addr = DDR3_FOFBPHA1_START_ADDR,
.end_addr = DDR3_FOFBPHA1_END_ADDR,
.max_samples = DDR3_FOFBPHA1_MAX_SAMPLES,
.sample_size = DDR3_FOFBPHA0_SAMPLE_SIZE
},
{
.id = FOFBPOS0_CHAN_ID,
.start_addr = DDR3_FOFBPOS1_START_ADDR,
.end_addr = DDR3_FOFBPOS1_END_ADDR,
.max_samples = DDR3_FOFBPOS1_MAX_SAMPLES,
.sample_size = DDR3_FOFBPOS0_SAMPLE_SIZE
},
{
.id = MONITAMP0_CHAN_ID,
.start_addr = DDR3_MONITAMP1_START_ADDR,
.end_addr = DDR3_MONITAMP1_END_ADDR,
.max_samples = DDR3_MONITAMP1_MAX_SAMPLES,
.sample_size = DDR3_MONITAMP0_SAMPLE_SIZE
},
{
.id = MONITPOS0_CHAN_ID,
.start_addr = DDR3_MONITPOS1_START_ADDR,
.end_addr = DDR3_MONITPOS1_END_ADDR,
.max_samples = DDR3_MONITPOS1_MAX_SAMPLES,
.sample_size = DDR3_MONITPOS0_SAMPLE_SIZE
},
{
.id = MONIT1POS0_CHAN_ID,
.start_addr = DDR3_MONIT1POS1_START_ADDR,
.end_addr = DDR3_MONIT1POS1_END_ADDR,
.max_samples = DDR3_MONIT1POS1_MAX_SAMPLES,
.sample_size = DDR3_MONIT1POS0_SAMPLE_SIZE
},
}
};
src/boards/afcv3_1/epics_mapping.c 0 → 100644
View file @ 569e9e37
/*
* Copyright (C) 2015 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, DEV_IO, "[dev_io:epics]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, DEV_IO, "[dev_io:epics]", \
devio_err_str(DEVIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, DEV_IO, "[dev_io:epics]", \
devio_err_str (err_type))
/* Reverse bpm-sw <-> EPICS board mapping */
const board_epics_rev_map_t board_epics_rev_map[NUM_MAX_SLOTS+1][NUM_MAX_BPM_PER_SLOT] = {
/* board, bpm */ /* bpm_id */
/* 0, 0 (INVALID) */ {{-1},
/* 0, 1 (INVALID) */ {-1}},
/* 1, 0 */ {{0},
/* 1, 1 */ {1}},
/* 2, 0 */ {{2},
/* 2, 1 */ {3}},
/* 3, 0 */ {{4},
/* 3, 1 */ {5}},
/* 4, 0 */ {{6},
/* 4, 1 */ {7}},
/* 5, 0 */ {{8},
/* 5, 1 */ {9}},
/* 6, 0 */ {{10},
/* 6, 1 */ {11}},
/* 7, 0 */ {{12},
/* 7, 1 */ {13}},
/* 8, 0 */ {{14},
/* 8, 1 */ {15}},
/* 9, 0 */ {{16},
/* 9, 1 */ {17}},
/* 10, 0 */ {{18},
/* 10, 1 */ {19}},
/* 11, 0 */ {{20},
/* 11, 1 */ {21}},
/* 12, 0 */ {{22},
/* 12, 1 */ {23}}
};
const board_epics_opts_t board_epics_opts[NUM_MAX_SLOTS+1][NUM_MAX_BPM_PER_SLOT] = {
/* board, bpm */ /* bpm_id */
/* 0, 0 (INVALID) */ {{-1},
/* 0, 1 (INVALID) */ {-1}},
/* 1, 0 */ {{20000 + 0},
/* 1, 1 */ {20000 + 1}},
/* 2, 0 */ {{20000 + 2},
/* 2, 1 */ {20000 + 3}},
/* 3, 0 */ {{20000 + 4},
/* 3, 1 */ {20000 + 5}},
/* 4, 0 */ {{20000 + 6},
/* 4, 1 */ {20000 + 7}},
/* 5, 0 */ {{20000 + 8},
/* 5, 1 */ {20000 + 9}},
/* 6, 0 */ {{20000 + 10},
/* 6, 1 */ {20000 + 11}},
/* 7, 0 */ {{20000 + 12},
/* 7, 1 */ {20000 + 13}},
/* 8, 0 */ {{20000 + 14},
/* 8, 1 */ {20000 + 15}},
/* 9, 0 */ {{20000 + 16},
/* 9, 1 */ {20000 + 17}},
/* 10, 0 */ {{20000 + 18},
/* 10, 1 */ {20000 + 19}},
/* 11, 0 */ {{20000 + 20},
/* 11, 1 */ {20000 + 21}},
/* 12, 0 */ {{20000 + 22},
/* 12, 1 */ {20000 + 23}}
};
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