Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
B
Beam Positoning Monitor - Software
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Beam Positoning Monitor - Software
Commits
9bdaa06f
Commit
9bdaa06f
authored
Apr 24, 2016
by
Lucas Russo
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
include/boards/*: declare components in ascending order of addresses
parent
30323471
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
54 additions
and
54 deletions
+54
-54
mem_layout.h
include/boards/afcv3/mem_layout.h
+21
-21
mem_layout.h
include/boards/afcv3_1/mem_layout.h
+21
-21
mem_layout.h
include/boards/ml605/mem_layout.h
+12
-12
No files found.
include/boards/afcv3/mem_layout.h
View file @
9bdaa06f
...
...
@@ -16,6 +16,13 @@
/* Should be autodiscovered by SDB */
/* Wishbone RAW Addresses */
#define DSP1_BASE_RAW_ADDR 0x00310000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define FMC1_130M_BASE_RAW_ADDR 0x00320000
#define FMC1_130M_CTRL_RAW_REGS (FMC1_130M_BASE_RAW_ADDR + \
...
...
@@ -44,15 +51,15 @@
#define FMC1_250M_ISLA216P_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define
DSP1_BASE_RAW_ADDR 0x0031
0000
#define
WB_ACQ1_BASE_RAW_ADDR 0x0033
0000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
#define DSP2_BASE_RAW_ADDR 0x00340000
#define DSP2_CTRL_RAW_REGS (DSP2_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP
1_BPM_RAW_SWAP (DSP1
_BASE_RAW_ADDR + \
#define DSP
2_BPM_RAW_SWAP (DSP2
_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ1_BASE_RAW_ADDR 0x00330000
#define FMC2_130M_BASE_RAW_ADDR 0x00350000
#define FMC2_130M_CTRL_RAW_REGS (FMC2_130M_BASE_RAW_ADDR + \
...
...
@@ -81,13 +88,6 @@
#define FMC2_250M_ISLA216P_RAW_SPI (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define DSP2_BASE_RAW_ADDR 0x00340000
#define DSP2_CTRL_RAW_REGS (DSP2_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP2_BPM_RAW_SWAP (DSP2_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ2_BASE_RAW_ADDR 0x00360000
#define WB_PERIPH_RAW_ADDR 0x00370000
...
...
@@ -122,6 +122,11 @@
*/
/* Wishbone Addresses */
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define FMC1_130M_BASE_ADDR (BAR4_ADDR | FMC1_130M_BASE_RAW_ADDR)
#define FMC1_130M_CTRL_REGS (BAR4_ADDR | FMC1_130M_CTRL_RAW_REGS)
...
...
@@ -139,12 +144,12 @@
#define FMC1_250M_AMC7823_SPI (BAR4_ADDR | FMC1_250M_AMC7823_RAW_SPI)
#define FMC1_250M_ISLA216P_SPI (BAR4_ADDR | FMC1_250M_ISLA216P_RAW_SPI)
#define
DSP1_BASE_ADDR (BAR4_ADDR | DSP
1_BASE_RAW_ADDR)
#define
WB_ACQ1_BASE_ADDR (BAR4_ADDR | WB_ACQ
1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define DSP2_BASE_ADDR (BAR4_ADDR | DSP2_BASE_RAW_ADDR)
#define WB_ACQ1_BASE_ADDR (BAR4_ADDR | WB_ACQ1_BASE_RAW_ADDR)
#define DSP2_CTRL_REGS (BAR4_ADDR | DSP2_CTRL_RAW_REGS)
#define DSP2_BPM_SWAP (BAR4_ADDR | DSP2_BPM_RAW_SWAP)
#define FMC2_130M_BASE_ADDR (BAR4_ADDR | FMC2_130M_BASE_RAW_ADDR)
...
...
@@ -163,11 +168,6 @@
#define FMC2_250M_AMC7823_SPI (BAR4_ADDR | FMC2_250M_AMC7823_RAW_SPI)
#define FMC2_250M_ISLA216P_SPI (BAR4_ADDR | FMC2_250M_ISLA216P_RAW_SPI)
#define DSP2_BASE_ADDR (BAR4_ADDR | DSP2_BASE_RAW_ADDR)
#define DSP2_CTRL_REGS (BAR4_ADDR | DSP2_CTRL_RAW_REGS)
#define DSP2_BPM_SWAP (BAR4_ADDR | DSP2_BPM_RAW_SWAP)
#define WB_ACQ2_BASE_ADDR (BAR4_ADDR | WB_ACQ2_BASE_RAW_ADDR)
#define WB_PERIPH_BASE_ADDR (BAR4_ADDR | WB_PERIPH_RAW_ADDR)
...
...
include/boards/afcv3_1/mem_layout.h
View file @
9bdaa06f
...
...
@@ -16,6 +16,13 @@
/* Should be autodiscovered by SDB */
/* Wishbone RAW Addresses */
#define DSP1_BASE_RAW_ADDR 0x00310000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define FMC1_130M_BASE_RAW_ADDR 0x00320000
#define FMC1_130M_CTRL_RAW_REGS (FMC1_130M_BASE_RAW_ADDR + \
...
...
@@ -44,15 +51,15 @@
#define FMC1_250M_ISLA216P_RAW_SPI (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define
DSP1_BASE_RAW_ADDR 0x0031
0000
#define
WB_ACQ1_BASE_RAW_ADDR 0x0033
0000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
#define DSP2_BASE_RAW_ADDR 0x00340000
#define DSP2_CTRL_RAW_REGS (DSP2_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP
1_BPM_RAW_SWAP (DSP1
_BASE_RAW_ADDR + \
#define DSP
2_BPM_RAW_SWAP (DSP2
_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ1_BASE_RAW_ADDR 0x00330000
#define FMC2_130M_BASE_RAW_ADDR 0x00350000
#define FMC2_130M_CTRL_RAW_REGS (FMC2_130M_BASE_RAW_ADDR + \
...
...
@@ -81,13 +88,6 @@
#define FMC2_250M_ISLA216P_RAW_SPI (FMC2_250M_BASE_RAW_ADDR + \
FMC_250M_ISLA216P_RAW_SPI_OFFS)
#define DSP2_BASE_RAW_ADDR 0x00340000
#define DSP2_CTRL_RAW_REGS (DSP2_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP2_BPM_RAW_SWAP (DSP2_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ2_BASE_RAW_ADDR 0x00360000
#define WB_PERIPH_RAW_ADDR 0x00370000
...
...
@@ -122,6 +122,11 @@
*/
/* Wishbone Addresses */
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define FMC1_130M_BASE_ADDR (BAR4_ADDR | FMC1_130M_BASE_RAW_ADDR)
#define FMC1_130M_CTRL_REGS (BAR4_ADDR | FMC1_130M_CTRL_RAW_REGS)
...
...
@@ -139,12 +144,12 @@
#define FMC1_250M_AMC7823_SPI (BAR4_ADDR | FMC1_250M_AMC7823_RAW_SPI)
#define FMC1_250M_ISLA216P_SPI (BAR4_ADDR | FMC1_250M_ISLA216P_RAW_SPI)
#define
DSP1_BASE_ADDR (BAR4_ADDR | DSP
1_BASE_RAW_ADDR)
#define
WB_ACQ1_BASE_ADDR (BAR4_ADDR | WB_ACQ
1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define DSP2_BASE_ADDR (BAR4_ADDR | DSP2_BASE_RAW_ADDR)
#define WB_ACQ1_BASE_ADDR (BAR4_ADDR | WB_ACQ1_BASE_RAW_ADDR)
#define DSP2_CTRL_REGS (BAR4_ADDR | DSP2_CTRL_RAW_REGS)
#define DSP2_BPM_SWAP (BAR4_ADDR | DSP2_BPM_RAW_SWAP)
#define FMC2_130M_BASE_ADDR (BAR4_ADDR | FMC2_130M_BASE_RAW_ADDR)
...
...
@@ -163,11 +168,6 @@
#define FMC2_250M_AMC7823_SPI (BAR4_ADDR | FMC2_250M_AMC7823_RAW_SPI)
#define FMC2_250M_ISLA216P_SPI (BAR4_ADDR | FMC2_250M_ISLA216P_RAW_SPI)
#define DSP2_BASE_ADDR (BAR4_ADDR | DSP2_BASE_RAW_ADDR)
#define DSP2_CTRL_REGS (BAR4_ADDR | DSP2_CTRL_RAW_REGS)
#define DSP2_BPM_SWAP (BAR4_ADDR | DSP2_BPM_RAW_SWAP)
#define WB_ACQ2_BASE_ADDR (BAR4_ADDR | WB_ACQ2_BASE_RAW_ADDR)
#define WB_PERIPH_BASE_ADDR (BAR4_ADDR | WB_PERIPH_RAW_ADDR)
...
...
include/boards/ml605/mem_layout.h
View file @
9bdaa06f
...
...
@@ -16,6 +16,13 @@
/* Should be autodiscovered by SDB */
/* Wishbone RAW Addresses */
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define FMC1_130M_BASE_RAW_ADDR 0x00310000
#define FMC1_130M_CTRL_RAW_REGS (FMC1_130M_BASE_RAW_ADDR + \
...
...
@@ -44,13 +51,6 @@
#define FMC1_250M_EEPROM_RAW_I2C (FMC1_250M_BASE_RAW_ADDR + \
FMC_250M_EEPROM_RAW_I2C_OFFS)
#define DSP1_BASE_RAW_ADDR 0x00308000
#define DSP1_CTRL_RAW_REGS (DSP1_BASE_RAW_ADDR + \
DSP_CTRL_RAW_REGS_OFFS)
#define DSP1_BPM_RAW_SWAP (DSP1_BASE_RAW_ADDR + \
DSP_BPM_RAW_SWAP_OFFS)
#define WB_ACQ1_BASE_RAW_ADDR 0x00330000
/* Large Memory RAW Addresses. It lives at address 0 */
...
...
@@ -78,6 +78,11 @@
*/
/* Wishbone Addresses */
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define FMC1_130M_BASE_ADDR (BAR4_ADDR | FMC1_130M_BASE_RAW_ADDR)
#define FMC1_130M_CTRL_REGS (BAR4_ADDR | FMC1_130M_CTRL_RAW_REGS)
...
...
@@ -95,11 +100,6 @@
#define FMC1_250M_AMC7823_SPI (BAR4_ADDR | FMC1_250M_AMC7823_RAW_SPI)
#define FMC1_250M_ISLA216P_SPI (BAR4_ADDR | FMC1_250M_ISLA216P_RAW_SPI)
#define DSP1_BASE_ADDR (BAR4_ADDR | DSP1_BASE_RAW_ADDR)
#define DSP1_CTRL_REGS (BAR4_ADDR | DSP1_CTRL_RAW_REGS)
#define DSP1_BPM_SWAP (BAR4_ADDR | DSP1_BPM_RAW_SWAP)
#define WB_ACQ1_BASE_ADDR (BAR4_ADDR | WB_ACQ1_BASE_RAW_ADDR)
/************************* ML605 Gateware Options *************************/
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment