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Beam Positoning Monitor - Software
Commit c3748c21 authored by Lucas Russo's avatar Lucas Russo
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include/hw: add new/update register files for FMCs

parent c171576c
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include/hw/wb_fmc130m_4ch_regs.h
View file @ c3748c21
/*
Register definitions for slave core: Control and status registers for FMC 130M 4CH
* File : fmc130m_4ch_regs.h
* File : wb_fmc130m_4ch_regs.h
* Author : auto-generated by wbgen2 from fmc_130m_4ch_regs.wb
* Created : Fri Apr 15 17:13:52 2016
* Created : Mon Apr 18 15:10:45 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_130m_4ch_regs.wb
......@@ -31,80 +31,6 @@
#endif
/* definitions for register: FMC Status */
/* definitions for field: FMC Present in reg: FMC Status */
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_PRSNT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Power Good from mezzanine in reg: FMC Status */
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_PG_M2C WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Clock Direction in reg: FMC Status */
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_CLK_DIR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Firware ID in reg: FMC Status */
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_FIRMWARE_ID_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_FIRMWARE_ID_SHIFT 3
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_FIRMWARE_ID_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_130M_4CH_CSR_FMC_STATUS_FIRMWARE_ID_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Trigger control */
/* definitions for field: DIR in reg: Trigger control */
#define WB_FMC_130M_4CH_CSR_TRIGGER_DIR WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Termination Control in reg: Trigger control */
#define WB_FMC_130M_4CH_CSR_TRIGGER_TERM WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Trigger Value in reg: Trigger control */
#define WB_FMC_130M_4CH_CSR_TRIGGER_TRIG_VAL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Trigger control */
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_SHIFT 3
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Monitor and FMC status control register */
/* definitions for field: Temperate Alarm in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_TEMP_ALARM WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Led 2 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_SHIFT 4
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Clock distribution control register */
/* definitions for field: SI571_OE in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PLL_FUNCTION in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)
/* definitions for field: PLL_STATUS in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: CLK_SEL in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: ADC LTC2208 control register (4 chips) */
/* definitions for field: RAND in reg: ADC LTC2208 control register (4 chips) */
......@@ -151,8 +77,8 @@
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 6, 2)
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 6, 2)
/* definitions for field: Enable test data in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEST_DATA_EN WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Temperature Alarm in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEMP_ALARM WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Reserved in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED2_MASK WBGEN2_GEN_MASK(9, 23)
......@@ -306,34 +232,26 @@
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_SHIFT 5
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* [0x0]: REG FMC Status */
#define WB_FMC_130M_4CH_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */
#define WB_FMC_130M_4CH_CSR_REG_TRIGGER 0x00000004
/* [0x8]: REG Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_REG_MONITOR 0x00000008
/* [0xc]: REG Clock distribution control register */
#define WB_FMC_130M_4CH_CSR_REG_CLK_DISTRIB 0x0000000c
/* [0x10]: REG ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_REG_ADC 0x00000010
/* [0x14]: REG FPGA control */
#define WB_FMC_130M_4CH_CSR_REG_FPGA_CTRL 0x00000014
/* [0x18]: REG IDELAY ADC0 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY0_CAL 0x00000018
/* [0x1c]: REG IDELAY ADC1 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY1_CAL 0x0000001c
/* [0x20]: REG IDELAY ADC2 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY2_CAL 0x00000020
/* [0x24]: REG IDELAY ADC3 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY3_CAL 0x00000024
/* [0x28]: REG ADC Data Channel 0 */
#define WB_FMC_130M_4CH_CSR_REG_DATA0 0x00000028
/* [0x2c]: REG ADC Data Channel 1 */
#define WB_FMC_130M_4CH_CSR_REG_DATA1 0x0000002c
/* [0x30]: REG ADC Data Channel 2 */
#define WB_FMC_130M_4CH_CSR_REG_DATA2 0x00000030
/* [0x34]: REG ADC Data Channel 3 */
#define WB_FMC_130M_4CH_CSR_REG_DATA3 0x00000034
/* [0x38]: REG ADC DCM control */
#define WB_FMC_130M_4CH_CSR_REG_DCM 0x00000038
/* [0x0]: REG ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_REG_ADC 0x00000000
/* [0x4]: REG FPGA control */
#define WB_FMC_130M_4CH_CSR_REG_FPGA_CTRL 0x00000004
/* [0x8]: REG IDELAY ADC0 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY0_CAL 0x00000008
/* [0xc]: REG IDELAY ADC1 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY1_CAL 0x0000000c
/* [0x10]: REG IDELAY ADC2 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY2_CAL 0x00000010
/* [0x14]: REG IDELAY ADC3 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY3_CAL 0x00000014
/* [0x18]: REG ADC Data Channel 0 */
#define WB_FMC_130M_4CH_CSR_REG_DATA0 0x00000018
/* [0x1c]: REG ADC Data Channel 1 */
#define WB_FMC_130M_4CH_CSR_REG_DATA1 0x0000001c
/* [0x20]: REG ADC Data Channel 2 */
#define WB_FMC_130M_4CH_CSR_REG_DATA2 0x00000020
/* [0x24]: REG ADC Data Channel 3 */
#define WB_FMC_130M_4CH_CSR_REG_DATA3 0x00000024
/* [0x28]: REG ADC DCM control */
#define WB_FMC_130M_4CH_CSR_REG_DCM 0x00000028
#endif
include/hw/wb_fmc250m_4ch_regs.h
View file @ c3748c21
/*
Register definitions for slave core: FMC ADC 250MS/s core registers
* File : fmc250m_4ch_regs.h
* File : wb_fmc250m_4ch_regs.h
* Author : auto-generated by wbgen2 from wb_fmc250m_4ch_regs.wb
* Created : Fri Apr 15 16:48:45 2016
* Created : Mon Apr 18 15:12:15 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc250m_4ch_regs.wb
......@@ -31,86 +31,6 @@
#endif
/* definitions for register: Status register */
/* definitions for field: MMCM locked status in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_MMCM_LOCKED WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC power good status in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_PWR_GOOD WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC board present status in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_PRST WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Status register */
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_RESERVED_MASK WBGEN2_GEN_MASK(3, 28)
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_RESERVED_SHIFT 3
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 28)
#define WB_FMC_250M_4CH_CSR_FMC_STATUS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 28)
/* definitions for register: Trigger control */
/* definitions for field: Direction in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_DIR WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Termination Control in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_TERM WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Trigger Value in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_TRIG_VAL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Trigger control */
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_SHIFT 3
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_250M_4CH_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Monitor and FMC status control register */
/* definitions for field: Enable test data in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_TEST_DATA_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_LED1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Led 2 in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_LED2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Monitor device in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_MON_DEV_MASK WBGEN2_GEN_MASK(4, 1)
#define WB_FMC_250M_4CH_CSR_MONITOR_MON_DEV_SHIFT 4
#define WB_FMC_250M_4CH_CSR_MONITOR_MON_DEV_W(value) WBGEN2_GEN_WRITE(value, 4, 1)
#define WB_FMC_250M_4CH_CSR_MONITOR_MON_DEV_R(reg) WBGEN2_GEN_READ(reg, 4, 1)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(5, 27)
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_SHIFT 5
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define WB_FMC_250M_4CH_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* definitions for register: Clock distribution control register */
/* definitions for field: Si 571 Output Enable in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: AD9510 PLL function in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)
/* definitions for field: AD9510 PLL Status in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reference Clock Selection in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_250M_4CH_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Global ADC Status register */
/* definitions for field: FMC ADC clock chains in reg: Global ADC Status register */
......@@ -525,40 +445,42 @@
#define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY_SHIFT 10
#define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
/* [0x0]: REG Status register */
#define WB_FMC_250M_4CH_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */
#define WB_FMC_250M_4CH_CSR_REG_TRIGGER 0x00000004
/* [0x8]: REG Monitor and FMC status control register */
#define WB_FMC_250M_4CH_CSR_REG_MONITOR 0x00000008
/* [0xc]: REG Clock distribution control register */
#define WB_FMC_250M_4CH_CSR_REG_CLK_DISTRIB 0x0000000c
/* [0x10]: REG Global ADC Status register */
#define WB_FMC_250M_4CH_CSR_REG_ADC_STA 0x00000010
/* [0x14]: REG Global ADC Control register */
#define WB_FMC_250M_4CH_CSR_REG_ADC_CTL 0x00000014
/* [0x18]: REG Channel 0 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_STA 0x00000018
/* [0x1c]: REG Channel 0 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_FN_DLY 0x0000001c
/* [0x20]: REG Channel 0 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_CS_DLY 0x00000020
/* [0x24]: REG Channel 1 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_STA 0x00000024
/* [0x28]: REG Channel 1 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_FN_DLY 0x00000028
/* [0x2c]: REG Channel 1 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_CS_DLY 0x0000002c
/* [0x30]: REG Channel 2 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_STA 0x00000030
/* [0x34]: REG Channel 2 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_FN_DLY 0x00000034
/* [0x38]: REG Channel 2 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_CS_DLY 0x00000038
/* [0x3c]: REG Channel 3 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_STA 0x0000003c
/* [0x40]: REG Channel 3 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_FN_DLY 0x00000040
/* [0x44]: REG Channel 3 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_CS_DLY 0x00000044
/* definitions for register: FMC temperature monitor register */
/* definitions for field: Monitor device in reg: FMC temperature monitor register */
#define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV_MASK WBGEN2_GEN_MASK(0, 1)
#define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV_SHIFT 0
#define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV_W(value) WBGEN2_GEN_WRITE(value, 0, 1)
#define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV_R(reg) WBGEN2_GEN_READ(reg, 0, 1)
/* [0x0]: REG Global ADC Status register */
#define WB_FMC_250M_4CH_CSR_REG_ADC_STA 0x00000000
/* [0x4]: REG Global ADC Control register */
#define WB_FMC_250M_4CH_CSR_REG_ADC_CTL 0x00000004
/* [0x8]: REG Channel 0 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_STA 0x00000008
/* [0xc]: REG Channel 0 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_FN_DLY 0x0000000c
/* [0x10]: REG Channel 0 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_CS_DLY 0x00000010
/* [0x14]: REG Channel 1 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_STA 0x00000014
/* [0x18]: REG Channel 1 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_FN_DLY 0x00000018
/* [0x1c]: REG Channel 1 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_CS_DLY 0x0000001c
/* [0x20]: REG Channel 2 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_STA 0x00000020
/* [0x24]: REG Channel 2 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_FN_DLY 0x00000024
/* [0x28]: REG Channel 2 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_CS_DLY 0x00000028
/* [0x2c]: REG Channel 3 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_STA 0x0000002c
/* [0x30]: REG Channel 3 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_FN_DLY 0x00000030
/* [0x34]: REG Channel 3 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_CS_DLY 0x00000034
/* [0x38]: REG FMC temperature monitor register */
#define WB_FMC_250M_4CH_CSR_REG_TEMP 0x00000038
#endif
include/hw/wb_fmc_active_clk_regs.h 0 → 100644
View file @ c3748c21
/*
Register definitions for slave core: FMC Active Clock registers
* File : wb_fmc_active_clk_regs.h
* Author : auto-generated by wbgen2 from wb_fmc_active_clk_regs.wb
* Created : Mon Apr 18 10:20:28 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_active_clk_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WB_FMC_ACTIVE_CLK_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMC_ACTIVE_CLK_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Clock distribution control register */
/* definitions for field: Si 571 Output Enable in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: AD9510 PLL function in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)
/* definitions for field: AD9510 PLL Status in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reference Clock Selection in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Dummy */
/* definitions for field: Reserved in reg: Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_SHIFT 0
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* [0x0]: REG Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_REG_CLK_DISTRIB 0x00000000
/* [0x4]: REG Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_REG_DUMMY 0x00000004
#endif
include/hw/wb_fmc_adc_common_regs.h 0 → 100644
View file @ c3748c21
/*
Register definitions for slave core: FMC ADC Common registers
* File : wb_fmc_adc_common_regs.h
* Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
* Created : Mon Apr 18 09:02:33 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WB_FMC_ADC_COMMON_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMC_ADC_COMMON_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status register */
/* definitions for field: MMCM locked status in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_MMCM_LOCKED WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC power good status in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_PWR_GOOD WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FMC board present status in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_PRST WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_MASK WBGEN2_GEN_MASK(3, 28)
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_SHIFT 3
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 28)
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 28)
/* definitions for register: Trigger control */
/* definitions for field: Direction in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_DIR WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Termination Control in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_TERM WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Trigger Value in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_TRIG_VAL WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_SHIFT 3
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
/* definitions for register: Monitor and FMC status control register */
/* definitions for field: Enable test data in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_TEST_DATA_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED1 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Led 2 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED2 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_SHIFT 4
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* [0x0]: REG Status register */
#define WB_FMC_ADC_COMMON_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */
#define WB_FMC_ADC_COMMON_CSR_REG_TRIGGER 0x00000004
/* [0x8]: REG Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_REG_MONITOR 0x00000008
#endif
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