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Converter Common Gateware
Commit f3f788a6 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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WRPC instantiation uses wrc.ram and no-WRPC logic connects MGT pins

parent 105019a2
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Showing with 74 additions and 9 deletions
top/conv_common_gw.vhd
View file @ f3f788a6
......@@ -450,9 +450,9 @@ begin
-- for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125,
I => clk_125_p_i,
IB => clk_125_n_i
IB => clk_125_n_i,
O => clk_125
);
--============================================================================
......@@ -1332,8 +1332,8 @@ gen_with_wr : if (g_with_wr = true) generate
cmp_clk_20_buf : BUFG
port map
(
O => clk_20_buf,
I => clk_20_i
I => clk_20_i,
O => clk_20_buf
);
cmp_dmtd_clk_pll : PLL_BASE
......@@ -1360,8 +1360,8 @@ gen_with_wr : if (g_with_wr = true) generate
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd,
I => clk_dmtd_fr_pll
I => clk_dmtd_fr_pll,
O => clk_dmtd
);
-- Instantiate the White Rabbit PTP Core (WRPC)
......@@ -1374,7 +1374,7 @@ gen_with_wr : if (g_with_wr = true) generate
g_virtual_uart => false,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "", --"wrc.ram",
g_dpram_initf => "wrc.ram",
g_dpram_size => 90112/4, --16384,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
......@@ -1470,11 +1470,12 @@ gen_with_wr : if (g_with_wr = true) generate
)
port map
(
O => clk_gtp,
I => mgt_refclk0_p_i,
IB => mgt_refclk0_n_i
IB => mgt_refclk0_n_i,
O => clk_gtp
);
cmp_gtp : wr_gtp_phy_spartan6
generic map
(
......@@ -1485,6 +1486,7 @@ gen_with_wr : if (g_with_wr = true) generate
port map
(
gtp_clk_i => clk_gtp,
ch0_ref_clk_i => clk_125,
ch0_tx_data_i => phy_tx_data(7 downto 0),
ch0_tx_k_i => phy_tx_k,
......@@ -1589,6 +1591,69 @@ gen_no_wr : if (g_with_wr = false) generate
sfp_sda_b <= 'Z';
sfp_tx_disable_o <= 'Z';
-- MGT signals
cmp_clk_gtp : IBUFGDS
generic map
(
DIFF_TERM => true,
IBUF_LOW_PWR => true,
IOSTANDARD => "DEFAULT"
)
port map
(
I => mgt_refclk0_p_i,
IB => mgt_refclk0_n_i,
O => clk_gtp
);
cmp_gtp : wr_gtp_phy_spartan6
generic map
(
g_simulation => 0,
g_enable_ch0 => 0,
g_enable_ch1 => 0
)
port map
(
gtp_clk_i => clk_gtp,
ch0_ref_clk_i => clk_125,
ch0_tx_data_i => x"00",
ch0_tx_k_i => '0',
ch0_tx_disparity_o => open,
ch0_tx_enc_err_o => open,
ch0_rx_rbclk_o => open,
ch0_rx_data_o => open,
ch0_rx_k_o => open,
ch0_rx_enc_err_o => open,
ch0_rx_bitslide_o => open,
ch0_rst_i => '1',
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125,
ch1_tx_data_i => x"00",
ch1_tx_k_i => '0',
ch1_tx_disparity_o => open,
ch1_tx_enc_err_o => open,
ch1_rx_rbclk_o => open,
ch1_rx_data_o => open,
ch1_rx_k_o => open,
ch1_rx_enc_err_o => open,
ch1_rx_bitslide_o => open,
ch1_rst_i => '1',
ch1_loopen_i => '0',
pad_txn0_o => mgt_tx0_n_o,
pad_txp0_o => mgt_tx0_p_o,
pad_rxn0_i => mgt_rx0_n_i,
pad_rxp0_i => mgt_rx0_p_i,
pad_txn1_o => open,
pad_txp1_o => open,
pad_rxn1_i => '0',
pad_rxp1_i => '0'
);
-- Implement PPS counter for the thermometer module (normally from WR)
gen_therm_pps_no_wr : if (g_with_thermometer = true) generate
p_therm_pps : process (clk_20_i)
......
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