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Conv TTL Blocking - Gateware
Commit 0dd7106c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Work on release v2.1 

hdl:
- substitute FIFO for ring buffer
- change pulse repetition duty cycle to 1/500
- renamed some files to make "generic" naming

sim:
- release: add I2C simulation capabilities
- conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle

syn:
- update project file with new files
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent b7a79518
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modules/Release/Manifest.py
View file @ 0dd7106c
......@@ -2,5 +2,6 @@ files = [
"conv_regs.vhd",
"conv_pulse_gen.vhd",
"conv_man_trig.vhd",
"pulse_timetag.vhd"
"conv_ring_buf.vhd",
"conv_pulse_timetag.vhd"
];
modules/Release/README.txt 0 → 100644
View file @ 0dd7106c
conv_regs.wb
============
If you change the FIFO width in the top-level conv_ttl_blo.vhd, you need to
also change the width of the USEDW field.
conv_regs.vhd
=============
You need to make some changes to this file after EVERY RUN of wbgen2:
1. Add the following output port declaration after the reg_tbmr_wrtag_i port:
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
2. Assign the port FOUR TIMES in the register bank process:
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
-- [...]
reg_tb_rd_req_p_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
-- [...]
reg_tb_rd_req_p_o <= '0';
ack_in_progress <= '0';
else
-- [...]
reg_tb_rd_req_p_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
[...]
when "1011" =>
if (wb_we_i = '1') then
end if;
reg_tb_rd_req_p_o <= '1';
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
rddata_reg(31) <= reg_tbmr_wrtag_i;
[...]
modules/Release/conv_pulse_gen.vhd
View file @ 0dd7106c
......@@ -23,8 +23,8 @@
-- is extended or cut to g_pwidth, if it is shorter or respectively longer than
-- g_pwidth. At the end of the pulse, a rejection phase is implemented in order
-- to avoid too many pulses arriving on the input. This is to safeguard the
-- isolation transformers on the CONV-TTL-BLO boards. The isolation phase
-- limits the input pulse to 1/5 duty cycle.
-- blocking output stage of the CONV-TTL-BLO boards. The isolation phase limits
-- the input pulse to 1/500 duty cycle.
--
-- dependencies:
-- none
......@@ -64,7 +64,10 @@ entity conv_pulse_gen is
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
......@@ -116,19 +119,20 @@ architecture behav of conv_pulse_gen is
-- * g_pwidth-4: three-cycle delay through synchronizer
-- * g_pwidth-5: reset signal applied in REJ_GF_OFF state
-- reject:
-- * 5*g_pwidth: 1/5 duty cycle
-- * 5*g_pwidth-5: 5-cycle delay added from the generate phase
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-5: 5-cycle delay added from the generate phase
-- glitch filter ON:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- reject:
-- * 5*g_pwidth: 1/5 duty cycle
-- * 5*g_pwidth-2: need one cycle less to allow for true 1/5 duty cycle,
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-2: need one cycle less to allow for true 1/D
-- duty cycle,
-- since the FSM needs to go through IDLE to accept a pulse
constant c_max_gen_gf_off : natural := g_pwidth-5;
constant c_max_rej_gf_off : natural := 5*g_pwidth-5;
constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 5;
constant c_max_gen_gf_on : natural := g_pwidth-1;
constant c_max_rej_gf_on : natural := 5*g_pwidth-2;
constant c_max_rej_gf_on : natural := g_duty_cycle_div*g_pwidth - 2;
--============================================================================
-- Function and procedure declarations
......@@ -163,7 +167,7 @@ architecture behav of conv_pulse_gen is
signal inh_fp_gf_on : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(6*g_pwidth)-1 downto 0);
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
-- FSM signal
signal state : t_state;
......
modules/Release/pulse_timetag.vhd → modules/Release/conv_pulse_timetag.vhd
View file @ 0dd7106c
......@@ -40,7 +40,7 @@ use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity pulse_timetag is
entity conv_pulse_timetag is
generic
(
-- Frequency in Hz of the clk_i signal
......@@ -75,14 +75,13 @@ entity pulse_timetag is
tm_wrpres_o : out std_logic;
chan_o : out std_logic_vector(g_nr_chan downto 1);
-- FIFO I/O
fifo_full_i : in std_logic;
fifo_wr_req_p_o : out std_logic
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
);
end entity pulse_timetag;
end entity conv_pulse_timetag;
architecture behav of pulse_timetag is
architecture behav of conv_pulse_timetag is
--============================================================================
-- Signal declarations
......@@ -183,21 +182,21 @@ begin
);
end generate gen_sync_chains;
-- Set the control signals to the FIFO on the rising edge of any pulse channel
p_fifo_ctrl : process (clk_i)
-- Set the control signals to the ring buffer on the rising edge of any
-- pulse channel
p_buf_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fifo_wr_req_p_o <= '0';
buf_wr_req_p_o <= '0';
else
fifo_wr_req_p_o <= '0';
if not (pulse_redge_p = (pulse_redge_p'range => '0'))
and (fifo_full_i = '0') then
fifo_wr_req_p_o <= '1';
buf_wr_req_p_o <= '0';
if not (pulse_redge_p = (pulse_redge_p'range => '0')) then
buf_wr_req_p_o <= '1';
end if;
end if;
end if;
end process p_fifo_ctrl;
end process p_buf_ctrl;
-- And delay the pulse rising edge for sampling (this is due to the delayed
-- setting of the write signal to the FIFO)
......
modules/Release/conv_regs.vhd
View file @ 0dd7106c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Thu Feb 13 17:08:07 2014
-- Created : Mon Mar 24 09:06:14 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
......@@ -13,7 +13,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity conv_regs is
port (
......@@ -28,9 +27,8 @@ entity conv_regs is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_wr_i : in std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_id_bits_i : in std_logic_vector(31 downto 0);
reg_bidr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board switches' in reg: 'SR'
......@@ -86,31 +84,33 @@ entity conv_regs is
reg_tvhr_o : out std_logic_vector(7 downto 0);
reg_tvhr_i : in std_logic_vector(7 downto 0);
reg_tvhr_load_o : out std_logic;
-- FIFO write request
reg_tf_wr_req_i : in std_logic;
-- FIFO full flag
reg_tf_wr_full_o : out std_logic;
-- FIFO empty flag
reg_tf_wr_empty_o : out std_logic;
reg_tf_chan_i : in std_logic_vector(5 downto 0);
reg_tf_wrtag_i : in std_logic;
reg_tf_cyc_i : in std_logic_vector(27 downto 0);
reg_tf_tai_l_i : in std_logic_vector(31 downto 0);
reg_tf_tai_h_i : in std_logic_vector(7 downto 0)
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i : in std_logic_vector(6 downto 0);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i : in std_logic;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i : in std_logic;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal reg_tf_rst_n : std_logic ;
signal reg_tf_in_int : std_logic_vector(74 downto 0);
signal reg_tf_out_int : std_logic_vector(74 downto 0);
signal reg_tf_rdreq_int : std_logic ;
signal reg_tf_rdreq_int_d0 : std_logic ;
signal reg_tf_full_int : std_logic ;
signal reg_tf_empty_int : std_logic ;
signal reg_tf_clear_bus_int : std_logic ;
signal reg_tf_usedw_int : std_logic_vector(6 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -150,8 +150,8 @@ begin
reg_ch6pcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tf_clear_bus_int <= '0';
reg_tf_rdreq_int <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -170,7 +170,8 @@ begin
reg_ch6pcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tf_clear_bus_int <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
ack_in_progress <= '0';
else
reg_sr_i2c_wdto_load_o <= '0';
......@@ -185,6 +186,8 @@ begin
reg_ch6pcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -192,7 +195,7 @@ begin
when "0000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_id_bits_i;
rddata_reg(31 downto 0) <= reg_bidr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
......@@ -337,14 +340,9 @@ begin
when "1011" =>
if (wb_we_i = '1') then
end if;
if (reg_tf_rdreq_int_d0 = '0') then
reg_tf_rdreq_int <= not reg_tf_rdreq_int;
else
rddata_reg(5 downto 0) <= reg_tf_out_int(5 downto 0);
rddata_reg(31) <= reg_tf_out_int(6);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
reg_tb_rd_req_p_o <= '1';
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
rddata_reg(31) <= reg_tbmr_wrtag_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
......@@ -370,10 +368,12 @@ begin
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_tf_out_int(34 downto 7);
rddata_reg(27 downto 0) <= reg_tbcyr_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
......@@ -383,13 +383,13 @@ begin
when "1101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_tf_out_int(66 downto 35);
rddata_reg(31 downto 0) <= reg_tbtlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_tf_out_int(74 downto 67);
rddata_reg(7 downto 0) <= reg_tbthr_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......@@ -418,14 +418,12 @@ begin
ack_in_progress <= '1';
when "1111" =>
if (wb_we_i = '1') then
if (wrdata_reg(18) = '1') then
reg_tf_clear_bus_int <= '1';
end if;
reg_tbcsr_clr_load_o <= '1';
end if;
rddata_reg(16) <= reg_tf_full_int;
rddata_reg(17) <= reg_tf_empty_int;
rddata_reg(18) <= '0';
rddata_reg(6 downto 0) <= reg_tf_usedw_int;
rddata_reg(6 downto 0) <= reg_tbcsr_usedw_i;
rddata_reg(16) <= reg_tbcsr_full_i;
rddata_reg(17) <= reg_tbcsr_empty_i;
rddata_reg(18) <= reg_tbcsr_clr_i;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
......@@ -493,48 +491,16 @@ begin
reg_tvlr_o <= wrdata_reg(31 downto 0);
-- TAI seconds counter bits 39..32
reg_tvhr_o <= wrdata_reg(7 downto 0);
-- extra code for reg/fifo/mem: Tag FIFO
reg_tf_in_int(5 downto 0) <= reg_tf_chan_i;
reg_tf_in_int(6) <= reg_tf_wrtag_i;
reg_tf_in_int(34 downto 7) <= reg_tf_cyc_i;
reg_tf_in_int(66 downto 35) <= reg_tf_tai_l_i;
reg_tf_in_int(74 downto 67) <= reg_tf_tai_h_i;
reg_tf_rst_n <= rst_n_i and (not reg_tf_clear_bus_int);
reg_tf_INST : wbgen2_fifo_async
generic map (
g_size => 128,
g_width => 75,
g_usedw_size => 7
)
port map (
wr_req_i => reg_tf_wr_req_i,
wr_full_o => reg_tf_wr_full_o,
wr_empty_o => reg_tf_wr_empty_o,
rd_full_o => reg_tf_full_int,
rd_empty_o => reg_tf_empty_int,
rd_usedw_o => reg_tf_usedw_int,
rd_req_i => reg_tf_rdreq_int,
rst_n_i => reg_tf_rst_n,
wr_clk_i => clk_wr_i,
rd_clk_i => clk_sys_i,
wr_data_i => reg_tf_in_int,
rd_data_o => reg_tf_out_int
);
-- extra code for reg/fifo/mem: FIFO 'Tag FIFO' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
reg_tf_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
reg_tf_rdreq_int_d0 <= reg_tf_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'Tag FIFO' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Tag FIFO' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Tag FIFO' data output register 3
-- Channel mask
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- Buffer counter
-- Buffer full
-- Buffer empty
-- Clear tag buffer
reg_tbcsr_clr_o <= wrdata_reg(18);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/Release/conv_regs.wb
View file @ 0dd7106c
......@@ -8,11 +8,10 @@ peripheral {
reg {
name = "BIDR";
description = "Board ID Register";
prefix = "id";
prefix = "bidr";
reset_value = "0x54424c4f";
field {
name = "ID register bits";
prefix = "bits";
reset_value = "0x54424c4f";
type = SLV;
size = 32;
......@@ -100,8 +99,8 @@ peripheral {
-- Logic reset bits
field {
name = "Reset unlock bit";
description = "1 - Reset bit unlocked \
0 - Reset bit locked";
description = "1 -- Reset bit unlocked \
0 -- Reset bit locked";
prefix = "rst_unlock";
type = BIT;
access_dev = READ_WRITE;
......@@ -110,8 +109,8 @@ peripheral {
};
field {
name = "Reset bit";
description = "1 - initiate logic reset \
0 - no reset";
description = "1 -- initiate logic reset \
0 -- no reset";
prefix = "rst";
type = BIT;
access_bus = READ_WRITE;
......@@ -247,16 +246,10 @@ peripheral {
};
};
fifo_reg {
size = 128;
name = "Tag FIFO";
prefix = "tf";
direction = CORE_TO_BUS;
flags_bus = {FIFO_COUNT, FIFO_FULL, FIFO_EMPTY, FIFO_CLEAR};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
clock="clk_wr_i";
reg {
name = "TBMR";
description = "Tag Buffer Meta Register";
prefix = "tbmr";
field {
name = "Channel mask";
description = "Mask for the channel(s) that triggered time-tag storage: \
......@@ -267,8 +260,9 @@ peripheral {
prefix = "chan";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
......@@ -276,32 +270,95 @@ peripheral {
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBCYR";
description = "Tag Buffer Cycles Register";
prefix = "tbcyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
prefix = "cyc";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBTLR";
description = "Tag Buffer TAI Low Register";
prefix = "tbtlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
prefix = "tai_l";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBTHR";
description = "Tag Buffer TAI High Register";
prefix = "tbthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai_h";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBCSR";
description = "Tag Buffer Control and Status Register";
prefix = "tbcsr";
field {
name = "Buffer counter";
prefix = "usedw";
description = "Number of samples in the ring buffer";
type = SLV;
size = 7;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Buffer full";
description = "1 -- buffer full \
0 -- buffer is not full";
prefix = "full";
type = BIT;
align = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Buffer empty";
description = "1 -- buffer empty\
0 -- buffer is not empty";
prefix = "empty";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Clear tag buffer";
description = "1 -- clear\
0 -- no effect";
prefix = "clr";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
};
modules/Release/conv_ring_buf.vhd 0 → 100644
View file @ 0dd7106c
--==============================================================================
-- CERN (BE-CO-HT)
-- Ring buffer for converter board designs
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-03-19
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-03-19 Theodor Stana Created file and copied content from
-- fd_ring_buffer.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity conv_ring_buf is
generic
(
-- Buffer data input and output width
g_data_width : positive;
-- Buffer size in number of samples
g_size : positive
);
port
(
-- Clocks and reset
clk_rd_i : in std_logic;
clk_wr_i : in std_logic;
rst_n_a_i : in std_logic;
-- Buffer inputs
buf_dat_i : in std_logic_vector(g_data_width-1 downto 0);
buf_rd_req_i : in std_logic;
buf_wr_req_i : in std_logic;
buf_clr_i : in std_logic;
-- Buffer outputs
buf_dat_o : out std_logic_vector(g_data_width-1 downto 0);
buf_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
buf_full_o : out std_logic;
buf_empty_o : out std_logic
);
end entity conv_ring_buf;
architecture behav of conv_ring_buf is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_fifo_size : positive := 8;
--============================================================================
-- Signal declarations
--============================================================================
-- FIFO signals
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_read : std_logic;
signal fifo_read_d0 : std_logic;
signal fifo_write : std_logic;
signal fifo_in : std_logic_vector(g_data_width-1 downto 0);
signal fifo_out : std_logic_vector(g_data_width-1 downto 0);
-- Buffer signals
signal buf_write : std_logic;
signal buf_read : std_logic;
signal buf_wr_ptr : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_rd_ptr : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_wr_data : std_logic_vector(g_data_width-1 downto 0);
signal buf_rd_data : std_logic_vector(g_data_width-1 downto 0);
signal buf_count : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_empty : std_logic;
signal buf_full : std_logic;
signal buf_overflow : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Buffer FIFO and RAM
--============================================================================
-- Assign FIFO input and control
fifo_in <= buf_dat_i;
fifo_write <= not fifo_full and buf_wr_req_i;
fifo_read <= not fifo_empty;
-- Instantiate FIFO to synchronize data inputs from read clock to write clock
cmp_clk_adjust_fifo : generic_async_fifo
generic map
(
g_data_width => fifo_in'length,
g_size => c_fifo_size
)
port map (
rst_n_i => rst_n_a_i,
clk_wr_i => clk_wr_i,
d_i => fifo_in,
we_i => fifo_write,
wr_full_o => fifo_full,
clk_rd_i => clk_rd_i,
q_o => fifo_out,
rd_i => fifo_read,
rd_empty_o => fifo_empty);
-- Instantiate the actual buffer RAM
-- The buffer gets fed with data from the FIFO
buf_wr_data <= fifo_out;
cmp_buf_ram : generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_dual_clock => false)
port map (
rst_n_i => rst_n_a_i,
clka_i => clk_rd_i,
bwea_i => (others => '1'),
wea_i => buf_write,
aa_i => std_logic_vector(buf_wr_ptr),
da_i => buf_wr_data,
qa_o => open,
clkb_i => clk_rd_i,
bweb_i => (others => '0'),
web_i => '0',
ab_i => std_logic_vector(buf_rd_ptr),
db_i => (others => '0'),
qb_o => buf_rd_data);
--============================================================================
-- Buffer control
--============================================================================
-- Assign buffer control signals
buf_write <= fifo_read_d0;
buf_read <= '1' when ((buf_rd_req_i = '1') and (buf_empty = '0')) or
(buf_overflow = '1')
else '0';
buf_overflow <= '1' when (buf_write = '1') and (buf_full = '1') else '0';
-- Buffer control process
p_buffer_control : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
if (rst_n_a_i = '0') or (buf_clr_i = '1') then
buf_rd_ptr <= (others => '0');
buf_wr_ptr <= (others => '0');
buf_count <= (others => '0');
buf_full <= '0';
buf_empty <= '1';
fifo_read_d0 <= '0';
else
fifo_read_d0 <= fifo_read;
-- Read and write signals
if(buf_write = '1') then
buf_wr_ptr <= buf_wr_ptr + 1;
end if;
if(buf_read = '1') then
buf_rd_ptr <= buf_rd_ptr + 1;
end if;
-- Buffer count and full/empty control
if (buf_write = '1') and (buf_read = '0') and (buf_full = '0') then
buf_count <= buf_count + 1;
buf_empty <= '0';
if (buf_count = (buf_count'range => '1')) then
buf_full <= '1';
end if;
end if;
if (buf_write = '0') and (buf_read = '1') and (buf_empty = '0') then
buf_count <= buf_count - 1;
buf_full <= '0';
if (buf_count = 1) then
buf_empty <= '1';
end if;
end if;
end if;
end if;
end process;
--============================================================================
-- Output signals
--============================================================================
buf_full_o <= buf_full;
buf_empty_o <= buf_empty;
buf_count_o <= std_logic_vector(buf_count);
buf_dat_o <= buf_rd_data;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
sim/Release/Makefile
View file @ 0dd7106c
......@@ -39,12 +39,14 @@ work/lm32_shifter/.lm32_shifter_v \
work/lm32_multiplier/.lm32_multiplier_v \
work/jtag_tap/.jtag_tap_v \
VHDL_SRC := testbench.vhd \
VHDL_SRC := i2c_bus_model.vhd \
testbench.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../modules/Release/conv_regs.vhd \
../../modules/Release/conv_pulse_gen.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../modules/Release/pulse_timetag.vhd \
../../modules/Release/conv_ring_buf.vhd \
../../modules/Release/conv_pulse_timetag.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
......@@ -104,7 +106,7 @@ VHDL_SRC := testbench.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
......@@ -136,7 +138,7 @@ VHDL_SRC := testbench.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../modules/Release/conv_regs.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
......@@ -148,12 +150,14 @@ VHDL_SRC := testbench.vhd \
../../top/Release/conv_ttl_blo.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
VHDL_OBJ := work/testbench/.testbench_vhd \
VHDL_OBJ := work/i2c_bus_model/.i2c_bus_model_vhd \
work/testbench/.testbench_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/conv_regs/.conv_regs_vhd \
work/conv_pulse_gen/.conv_pulse_gen_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/pulse_timetag/.pulse_timetag_vhd \
work/conv_ring_buf/.conv_ring_buf_vhd \
work/conv_pulse_timetag/.conv_pulse_timetag_vhd \
work/reset_gen/.reset_gen_vhd \
work/rtm_detector/.rtm_detector_vhd \
work/wishbone_pkg/.wishbone_pkg_vhd \
......@@ -213,7 +217,7 @@ work/simple_uart_wb/.simple_uart_wb_vhd \
work/wb_simple_uart/.wb_simple_uart_vhd \
work/xwb_simple_uart/.xwb_simple_uart_vhd \
work/vic_prio_enc/.vic_prio_enc_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
work/wb_vic/.wb_vic_vhd \
work/xwb_vic/.xwb_vic_vhd \
work/wb_spi/.wb_spi_vhd \
......@@ -245,7 +249,7 @@ work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
work/wbgen2_eic/.wbgen2_eic_vhd \
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
work/conv_regs/.conv_regs_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
......@@ -339,6 +343,11 @@ work/jtag_tap/.jtag_tap_v: ../../ip_cores/general-cores/modules/wishbone/wb_lm32
work/i2c_bus_model/.i2c_bus_model_vhd: i2c_bus_model.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/testbench/.testbench_vhd: testbench.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -349,7 +358,7 @@ work/genram_pkg/.genram_pkg_vhd: ../../ip_cores/general-cores/modules/genrams/ge
@mkdir -p $(dir $@) && touch $@
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
work/conv_regs/.conv_regs_vhd: ../../modules/Release/conv_regs.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -367,12 +376,20 @@ work/gencores_pkg/.gencores_pkg_vhd: ../../ip_cores/general-cores/modules/common
work/gencores_pkg/.gencores_pkg: \
work/genram_pkg/.genram_pkg
work/pulse_timetag/.pulse_timetag_vhd: ../../modules/Release/pulse_timetag.vhd
work/conv_ring_buf/.conv_ring_buf_vhd: ../../modules/Release/conv_ring_buf.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/pulse_timetag/.pulse_timetag: \
work/conv_ring_buf/.conv_ring_buf: \
work/genram_pkg/.genram_pkg
work/conv_pulse_timetag/.conv_pulse_timetag_vhd: ../../modules/Release/conv_pulse_timetag.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_pulse_timetag/.conv_pulse_timetag: \
work/gencores_pkg/.gencores_pkg
work/reset_gen/.reset_gen_vhd: ../../modules/reset_gen.vhd
......@@ -812,14 +829,11 @@ work/vic_prio_enc/.vic_prio_enc_vhd: ../../ip_cores/general-cores/modules/wishbo
@mkdir -p $(dir $@) && touch $@
work/wb_slave_vic/.wb_slave_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_slave_vic/.wb_slave_vic: \
work/wbgen2_pkg/.wbgen2_pkg
work/wb_vic/.wb_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -1083,12 +1097,12 @@ work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../ip_cores/general-cores/module
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
work/wbgen2_pkg/.wbgen2_pkg
work/conv_regs/.conv_regs_vhd: ../../modules/Release/conv_regs.vhd
work/wb_slave_vic/.wb_slave_vic_vhd: ../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/conv_regs/.conv_regs: \
work/wb_slave_vic/.wb_slave_vic: \
work/wbgen2_pkg/.wbgen2_pkg
work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
......@@ -1160,7 +1174,8 @@ work/conv_ttl_blo/.conv_ttl_blo_vhd: ../../top/Release/conv_ttl_blo.vhd
work/conv_ttl_blo/.conv_ttl_blo: \
work/wishbone_pkg/.wishbone_pkg \
work/bicolor_led_ctrl_pkg/.bicolor_led_ctrl_pkg \
work/gencores_pkg/.gencores_pkg
work/gencores_pkg/.gencores_pkg \
work/genram_pkg/.genram_pkg
work/bicolor_led_ctrl/.bicolor_led_ctrl_vhd: ../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd
vcom $(VCOM_FLAGS) -work work $<
......
sim/Release/Manifest.py
View file @ 0dd7106c
target = "xilinx"
action = "simulation"
files = "testbench.vhd"
files = [
"i2c_bus_model.vhd",
"testbench.vhd"
]
modules = { "local" : "../../top/Release" }
sim/Release/i2c_bus_model.vhd 0 → 100644
View file @ 0dd7106c
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C bus model
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-11-27
--
-- version: 1.0
--
-- description:
-- A very simple I2C bus model for use in simulation, implementing the
-- wired-AND on the I2C protocol.
--
-- Masters and slaves should implement the buffers internally and connect the
-- SCL and SDA lines to the input ports of this model, as below:
-- - masters should connect to mscl_i and msda_i
-- - slaves should connect to sscl_i and ssda_i
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-11-27 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end entity i2c_bus_model;
architecture behav of i2c_bus_model is
--==============================================================================
-- architecture begin
--==============================================================================
begin
scl_o <= '1' when (mscl_i = (mscl_i'range => '1')) and
(sscl_i = (sscl_i'range => '1')) else
'0';
sda_o <= '1' when (msda_i = (msda_i'range => '1')) and
(ssda_i = (ssda_i'range => '1')) else
'0';
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
sim/Release/testbench.vhd
View file @ 0dd7106c
......@@ -13,6 +13,7 @@
-- Design-wide simulation testbench for the CONV-TTL-BLO gateware. Currently
-- simulated features include:
-- - pulse triggering
-- - I2C master for reading register contents
--
-- dependencies:
-- None.
......@@ -50,13 +51,39 @@ architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
type t_state_i2c_mst is
(
IDLE,
I2C_ADDR, I2C_ADDR_ACK,
WB_ADDR_B0, WB_ADDR_B0_ACK,
WB_ADDR_B1, WB_ADDR_B1_ACK,
ST_OP,
RD_RESTART, RD_RESTART_ACK,
RD, RD_ACK,
WR, WR_ACK,
STO,
SUCCESS,
ERR
);
--============================================================================
-- Constant declarations
--============================================================================
-- Clock periods
constant c_clk_20_per : time := 50 ns;
constant c_clk_125_per : time := 8 ns;
-- Number of I2C masters and slaves for the I2C bus model
constant c_nr_masters : positive := 1;
constant c_nr_slaves : positive := 1;
--============================================================================
-- Component declarations
--============================================================================
......@@ -156,12 +183,71 @@ architecture behav of testbench is
);
end component conv_ttl_blo;
-- I2C bus model
component i2c_bus_model is
generic
(
g_nr_masters : positive := 1;
g_nr_slaves : positive := 1
);
port
(
-- Input ports from master lines
mscl_i : in std_logic_vector(g_nr_masters-1 downto 0);
msda_i : in std_logic_vector(g_nr_masters-1 downto 0);
-- Input ports from slave lines
sscl_i : in std_logic_vector(g_nr_slaves-1 downto 0);
ssda_i : in std_logic_vector(g_nr_slaves-1 downto 0);
-- SCL and SDA line outputs
scl_o : out std_logic;
sda_o : out std_logic
);
end component i2c_bus_model;
-- I2C master
component i2c_master_byte_ctrl is
port
(
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
--============================================================================
-- Signal declarations
--============================================================================
signal clk_20, clk_125 : std_logic;
signal clk_125_p, clk_125_n : std_logic;
signal rst_n : std_logic;
signal rst_n, rst : std_logic;
signal pulse_led_front_n : std_logic_vector(6 downto 1);
signal pulse_led_front : std_logic_vector(6 downto 1);
......@@ -176,6 +262,51 @@ architecture behav of testbench is
signal ttl_switch_n : std_logic;
signal switches_n : std_logic_vector(7 downto 1);
-- I2C signals
signal state_i2c_mst : t_state_i2c_mst;
signal mst_fsm_op : std_logic;
signal mst_fsm_start : std_logic;
signal stim_cnt : unsigned(31 downto 0);
signal cnt : unsigned(2 downto 0);
signal buf_byte_cnt : integer;
signal once : boolean;
signal byte_cnt : unsigned(1 downto 0);
signal rcvd : std_logic_vector(31 downto 0);
signal send : std_logic_vector(31 downto 0);
signal send_val : std_logic_vector(31 downto 0);
signal wrote : std_logic;
signal slv_addr : std_logic_vector(6 downto 0);
signal adr : std_logic_vector(31 downto 0);
signal mst_sta : std_logic;
signal mst_sto : std_logic;
signal mst_rd : std_logic;
signal mst_wr : std_logic;
signal mst_ack : std_logic;
signal mst_dat_in : std_logic_vector(7 downto 0);
signal mst_dat_out : std_logic_vector(7 downto 0);
signal mst_cmd_ack : std_logic;
signal ack_fr_slv : std_logic;
signal mscl, msda : std_logic_vector(c_nr_masters-1 downto 0);
signal sscl, ssda : std_logic_vector(c_nr_slaves-1 downto 0);
signal scl, sda : std_logic;
signal scl_fr_mst : std_logic;
signal scl_en_mst : std_logic;
signal sda_fr_mst : std_logic;
signal sda_en_mst : std_logic;
signal scl_fr_slv : std_logic;
signal scl_en_slv : std_logic;
signal sda_fr_slv : std_logic;
signal sda_en_slv : std_logic;
signal t : boolean;
--==============================================================================
-- architecture begin
--==============================================================================
......@@ -256,13 +387,13 @@ begin
extra_switch_n_i => switches_n,
-- Lines for the i2c_slave
scl_i => '1',
scl_o => open,
scl_oe_o => open,
sda_i => '1',
sda_o => open,
sda_oe_o => open,
fpga_ga_i => (others => '1'),
scl_i => scl,
scl_o => scl_fr_slv,
scl_oe_o => scl_en_slv,
sda_i => sda,
sda_o => sda_fr_slv,
sda_oe_o => sda_en_slv,
fpga_ga_i => "11110",
fpga_gap_i => '0',
-- Flash memory lines
......@@ -301,6 +432,15 @@ begin
fpga_rtmp_n_i => (others => '0')
);
-- Tri-state buffers on the I2C lines
sscl(0) <= scl_fr_slv when (scl_en_slv = '1') else
'1';
ssda(0) <= sda_fr_slv when (sda_en_slv = '1') else
'1';
-- Active-high reset
rst <= not rst_n;
--============================================================================
-- Pulse outputs assignment based on OE signals
--============================================================================
......@@ -333,14 +473,11 @@ begin
blo_inp(i-1) <= blo_outp(i);
end generate gen_pulse_chain;
p_ttl_stim : process
p_stim_pulse : process
begin
ttl_inp_n(6) <= '1';
wait for 2.5 us;
ttl_inp_n(6) <= '0';
wait for 1.2 us;
ttl_inp_n(6) <= '1';
while true loop
wait until t = true;
while (t = true) loop
wait for 5.561 us;
ttl_inp_n(6) <= '0';
wait for 500 ns;
......@@ -352,8 +489,303 @@ begin
assert false report "blo_outp not '1'" severity warning;
end if;
end loop;
end process p_stim_pulse;
process
begin
t <= true;
wait for 2 ms;
t <= false;
wait for 500 ms;
t <= true;
wait for 10 ms;
t <= false;
wait;
end process p_ttl_stim;
end process;
--============================================================================
-- I2C master
--============================================================================
------------------------------------------------------------------------------
-- First, the component instantiation
------------------------------------------------------------------------------
cmp_master : i2c_master_byte_ctrl
port map
(
clk => clk_20,
rst => rst,
nReset => rst_n,
ena => '1',
clk_cnt => x"0027",
-- input signals
start => mst_sta,
stop => mst_sto,
read => mst_rd,
write => mst_wr,
ack_in => mst_ack,
din => mst_dat_in,
-- output signals
cmd_ack => mst_cmd_ack,
ack_out => ack_fr_slv,
i2c_busy => open,
i2c_al => open,
dout => mst_dat_out,
-- i2c lines
scl_i => scl,
scl_o => scl_fr_mst,
scl_oen => scl_en_mst,
sda_i => sda,
sda_o => sda_fr_mst,
sda_oen => sda_en_mst
);
-- Then, the tri-state_i2c_mst buffers on the line
mscl(0) <= scl_fr_mst when (scl_en_mst = '0') else
'1';
msda(0) <= sda_fr_mst when (sda_en_mst = '0') else
'1';
------------------------------------------------------------------------------
-- Bus model instantiation and connection to master and slaves
------------------------------------------------------------------------------
cmp_i2c_bus : i2c_bus_model
generic map
(
g_nr_masters => c_nr_masters,
g_nr_slaves => c_nr_slaves
)
port map
(
mscl_i => mscl,
msda_i => msda,
sscl_i => sscl,
ssda_i => ssda,
scl_o => scl,
sda_o => sda
);
------------------------------------------------------------------------------
-- This FSM controls the signals to the master component to implement the I2C
-- protocol defined together with ELMA. The FSM is controlled by the
-- stimuli process below
------------------------------------------------------------------------------
p_mst_fsm : process (clk_20) is
begin
if rising_edge(clk_20) then
if (rst_n = '0') then
state_i2c_mst <= IDLE;
mst_sta <= '0';
mst_wr <= '0';
mst_sto <= '0';
mst_rd <= '0';
mst_dat_in <= (others => '0');
mst_ack <= '0';
cnt <= (others => '0');
once <= true;
byte_cnt <= (others => '0');
rcvd <= (others => '0');
send <= (others => '0');
else
case state_i2c_mst is
when IDLE =>
if (mst_fsm_start = '1') then
state_i2c_mst <= I2C_ADDR;
send <= std_logic_vector(send_val);
end if;
when I2C_ADDR =>
mst_sta <= '1';
mst_wr <= '1';
mst_dat_in <= slv_addr & '0';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= I2C_ADDR_ACK;
end if;
when I2C_ADDR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B0;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B0 =>
mst_wr <= '1';
mst_dat_in <= adr(15 downto 8);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B0_ACK;
end if;
when WB_ADDR_B0_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= WB_ADDR_B1;
else
state_i2c_mst <= ERR;
end if;
end if;
when WB_ADDR_B1 =>
mst_wr <= '1';
mst_dat_in <= adr(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WB_ADDR_B1_ACK;
end if;
when WB_ADDR_B1_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= ST_OP;
else
state_i2c_mst <= ERR;
end if;
end if;
when ST_OP =>
if (mst_fsm_op = '1') then
state_i2c_mst <= RD_RESTART;
else
state_i2c_mst <= WR;
end if;
when RD_RESTART =>
mst_wr <= '1';
mst_dat_in <= slv_addr & '1';
mst_sta <= '1';
if (mst_cmd_ack = '1') then
mst_sta <= '0';
mst_wr <= '0';
state_i2c_mst <= RD_RESTART_ACK;
end if;
when RD_RESTART_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
state_i2c_mst <= RD;
else
state_i2c_mst <= ERR;
end if;
end if;
when RD =>
mst_rd <= '1';
mst_ack <= '0';
if (byte_cnt = 3) then
mst_ack <= '1';
end if;
if (mst_cmd_ack = '1') then
mst_rd <= '0';
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when RD_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
byte_cnt <= byte_cnt + 1;
rcvd <= mst_dat_out & rcvd(31 downto 8);
mst_ack <= '0';
state_i2c_mst <= RD;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
end if;
when WR =>
mst_wr <= '1';
mst_dat_in <= send(7 downto 0);
if (mst_cmd_ack = '1') then
mst_wr <= '0';
state_i2c_mst <= WR_ACK;
end if;
when WR_ACK =>
cnt <= cnt + 1;
if (cnt = 7) then
if (ack_fr_slv = '0') then
byte_cnt <= byte_cnt + 1;
send <= x"00" & send(31 downto 8);
state_i2c_mst <= WR;
if (byte_cnt = 3) then
state_i2c_mst <= STO;
end if;
else
state_i2c_mst <= ERR;
end if;
end if;
when STO =>
mst_sto <= '1';
if (mst_cmd_ack = '1') then
mst_sto <= '0';
state_i2c_mst <= IDLE;
end if;
when ERR =>
if (once) then
report("Error!");
once <= false;
end if;
when others =>
state_i2c_mst <= ERR;
end case;
end if;
end if;
end process p_mst_fsm;
------------------------------------------------------------------------------
-- Process to "stimulate" the master FSM above
------------------------------------------------------------------------------
p_stim_mst_fsm : process (rst_n, t, state_i2c_mst)
begin
if (rst_n = '0') then
mst_fsm_start <= '0';
mst_fsm_op <= '0';
slv_addr <= "1011110";
adr <= (others => '0');
buf_byte_cnt <= 0;
elsif (not t) and (state_i2c_mst = IDLE) then
mst_fsm_start <= '1';
mst_fsm_op <= '1';
buf_byte_cnt <= buf_byte_cnt + 1;
case buf_byte_cnt is
when 0 =>
adr(11 downto 0) <= x"030";
when 1 =>
adr(11 downto 0) <= x"034";
when 2 =>
adr(11 downto 0) <= x"038";
when 3 =>
adr(11 downto 0) <= x"02c";
buf_byte_cnt <= 0;
when others =>
buf_byte_cnt <= 0;
end case;
else
mst_fsm_start <= '0';
end if;
end process p_stim_mst_fsm;
end architecture behav;
--==============================================================================
......
sim/Release/wave.do
View file @ 0dd7106c
......@@ -19,15 +19,35 @@ add wave -noupdate /testbench/cmp_dut/fpga_blo_in_i
add wave -noupdate /testbench/cmp_dut/trig_a
add wave -noupdate /testbench/cmp_dut/trig_ttl_a
add wave -noupdate -expand /testbench/cmp_dut/trig_blo_a
add wave -noupdate /testbench/cmp_dut/trig
add wave -noupdate /testbench/cmp_dut/trig_chan
add wave -noupdate /testbench/cmp_dut/trig_man
add wave -noupdate -divider counters
add wave -noupdate -expand /testbench/cmp_dut/pulse_cnt
add wave -noupdate -divider i2c
add wave -noupdate /testbench/scl
add wave -noupdate /testbench/sda
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_cyc_i
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_stb_i
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_we_i
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/reg_tb_rd_req_p_o
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_adr_i
add wave -noupdate /testbench/cmp_dut/cmp_conv_regs/wb_dat_o
add wave -noupdate -divider fifo
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_count
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_wr_req_i
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_empty
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_full
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_overflow
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_read
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_write
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_rd_ptr
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_wr_ptr
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_rd_data
add wave -noupdate /testbench/cmp_dut/cmp_ring_buf/buf_wr_data
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {640454438 ps} 0}
configure wave -namecolwidth 266
configure wave -valuecolwidth 100
WaveRestoreCursors {{Cursor 1} {1225000 ps} 0}
configure wave -namecolwidth 397
configure wave -valuecolwidth 164
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
......@@ -40,4 +60,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {582143750 ps} {746206250 ps}
WaveRestoreZoom {0 ps} {10253908 ps}
sim/conv_pulse_gen/run.do
View file @ 0dd7106c
......@@ -18,5 +18,5 @@ radix -hexadecimal
# add wave *
do wave.do
run 100 us
run 10 ms
wave zoomfull
sim/conv_pulse_gen/testbench.vhd
View file @ 0dd7106c
......@@ -62,7 +62,10 @@ architecture behav of testbench is
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
......@@ -133,7 +136,8 @@ begin
DUT: conv_pulse_gen
generic map
(
g_pwidth => 24
g_pwidth => 24,
g_duty_cycle_div => 500
)
port map
(
......@@ -176,8 +180,8 @@ begin
rst_n_i => rst_n,
en_i => pgen_en,
delay_i => (others => '0'),
pwidth_i => x"00000018",
freq_i => x"000000dc",
pwidth_i => x"0000012c",
freq_i => x"000249f0",
pulse_o => trig
);
......@@ -200,19 +204,7 @@ begin
trig_degl;
actual_trig <= trig_chan or trig_man;
-- PULSE GENERATOR FOR GF_EN
cmp_pulse_gen_gp: pulse_gen_gp
port map
(
clk_i => clk,
rst_n_i => rst_n,
en_i => '1',
delay_i => (others => '0'),
pwidth_i => x"00000409",
freq_i => x"00000812",
pulse_o => gf_en
);
-- Glitch filter enable
gf_en_n <= '0';
-- manual trigger stimuli
......@@ -230,14 +222,14 @@ begin
trig_man <= '0';
wait for 10 us;
pgen_en <= '1';
wait for 30 us;
pgen_en <= '0';
wait for 10 us;
trig_man <= '1';
wait for c_clk_per;
trig_man <= '0';
wait for 10 us;
pgen_en <= '1';
-- wait for 30 us;
-- pgen_en <= '0';
-- wait for 10 us;
-- trig_man <= '1';
-- wait for c_clk_per;
-- trig_man <= '0';
-- wait for 10 us;
-- pgen_en <= '1';
wait;
end process;
......
syn/Release/conv_ttl_blo.xise
View file @ 0dd7106c
......@@ -344,7 +344,7 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/Release/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../modules/Release/conv_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
......@@ -353,354 +353,357 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../modules/Release/pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/Release/conv_ring_buf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../modules/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/Release/conv_pulse_timetag.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../modules/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../modules/Release/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/Release/conv_man_trig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../modules/Release/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../top/Release/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../top/Release/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
</files>
<bindings/>
......
top/Release/conv_ttl_blo.vhd
View file @ 0dd7106c
......@@ -54,6 +54,7 @@ use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity conv_ttl_blo is
generic
......@@ -191,7 +192,7 @@ architecture behav of conv_ttl_blo is
-- next minor release v1.1 c_gwvers = x"11";
-- 13 minor releases later v1.14 c_gwvers = x"1e";
-- next major release v2.0 c_gwvers = x"20";
constant c_gwvers : std_logic_vector(7 downto 0) := x"20";
constant c_gwvers : std_logic_vector(7 downto 0) := x"21";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
......@@ -240,7 +241,23 @@ architecture behav of conv_ttl_blo is
------------------------------------------------------------------------------
-- Pulse generator glitch filter length
------------------------------------------------------------------------------
constant c_pulse_gen_gf_len : positive := 1;
constant c_pulse_gen_pwidth : positive := 24;
constant c_pulse_gen_duty_cycle_div : positive := 500;
constant c_pulse_gen_gf_len : positive := 1;
------------------------------------------------------------------------------
-- Pulse time-tag ring buffer constants
------------------------------------------------------------------------------
-- data width: 40 -- TAI
-- 28 -- cycles
-- 1 -- WRPRES bit
-- xx -- channel mask
constant c_tb_data_width : positive := 40 + 28 + 1 + g_nr_ttl_chan;
-- size in number of (data width)-sized samples
constant c_tb_size : positive := 128;
-- <<<< NOTE >>>> Also change USEDW size in conv_regs.vhd <<<< NOTE >>>>
-- <<<< NOTE >>>> See README.txt in modules/Release/ <<<< NOTE >>>>
--============================================================================
-- Component declarations
......@@ -274,7 +291,10 @@ architecture behav of conv_ttl_blo is
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
......@@ -332,9 +352,8 @@ architecture behav of conv_ttl_blo is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_wr_i : in std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_id_bits_i : in std_logic_vector(31 downto 0);
reg_bidr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board switches' in reg: 'SR'
......@@ -390,17 +409,28 @@ architecture behav of conv_ttl_blo is
reg_tvhr_o : out std_logic_vector(7 downto 0);
reg_tvhr_i : in std_logic_vector(7 downto 0);
reg_tvhr_load_o : out std_logic;
-- FIFO write request
reg_tf_wr_req_i : in std_logic;
-- FIFO full flag
reg_tf_wr_full_o : out std_logic;
-- FIFO empty flag
reg_tf_wr_empty_o : out std_logic;
reg_tf_chan_i : in std_logic_vector(5 downto 0);
reg_tf_wrtag_i : in std_logic;
reg_tf_cyc_i : in std_logic_vector(27 downto 0);
reg_tf_tai_l_i : in std_logic_vector(31 downto 0);
reg_tf_tai_h_i : in std_logic_vector(7 downto 0)
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i : in std_logic_vector(6 downto 0);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i : in std_logic;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i : in std_logic;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic
);
end component conv_regs;
......@@ -458,11 +488,12 @@ architecture behav of conv_ttl_blo is
------------------------------------------------------------------------------
-- Pulse time-tagging component
------------------------------------------------------------------------------
component pulse_timetag is
component conv_pulse_timetag is
generic
(
-- Frequency in Hz of the clk_i signal
g_clk_rate : positive := 125000000;
-- Number of repetition channels
g_nr_chan : positive := 6
);
......@@ -492,11 +523,41 @@ architecture behav of conv_ttl_blo is
tm_wrpres_o : out std_logic;
chan_o : out std_logic_vector(g_nr_chan downto 1);
-- FIFO I/O
fifo_full_i : in std_logic;
fifo_wr_req_p_o : out std_logic
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
);
end component conv_pulse_timetag;
------------------------------------------------------------------------------
-- Ring buffer component
-- use: buffer time stamps generated by the conv_pulse_timetag component
------------------------------------------------------------------------------
component conv_ring_buf is
generic
(
g_data_width : positive;
g_size : positive
);
end component pulse_timetag;
port
(
-- Clocks and reset
clk_rd_i : in std_logic;
clk_wr_i : in std_logic;
rst_n_a_i : in std_logic;
-- Buffer inputs
buf_dat_i : in std_logic_vector(g_data_width-1 downto 0);
buf_rd_req_i : in std_logic;
buf_wr_req_i : in std_logic;
buf_clr_i : in std_logic;
-- Buffer outputs
buf_dat_o : out std_logic_vector(g_data_width-1 downto 0);
buf_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
buf_full_o : out std_logic;
buf_empty_o : out std_logic
);
end component conv_ring_buf;
--============================================================================
-- Signal declarations
......@@ -593,14 +654,18 @@ architecture behav of conv_ttl_blo is
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_tai : std_logic_vector(39 downto 0);
signal fifo_wr_req_p : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_chan : std_logic_vector(g_nr_ttl_chan downto 1);
signal fifo_wrtag : std_logic;
signal fifo_cyc : std_logic_vector(27 downto 0);
signal fifo_tai_l : std_logic_vector(31 downto 0);
signal fifo_tai_h : std_logic_vector( 7 downto 0);
signal buf_wr_req_p : std_logic;
signal buf_rd_req_p : std_logic;
signal buf_count : std_logic_vector(f_log2_size(c_tb_size)-1 downto 0);
signal buf_full : std_logic;
signal buf_empty : std_logic;
signal buf_chan : std_logic_vector(g_nr_ttl_chan downto 1);
signal buf_wrtag : std_logic;
signal buf_clr_bit : std_logic;
signal buf_clr_bit_ld : std_logic;
signal buf_clr_p : std_logic;
signal buf_dat_in : std_logic_vector(c_tb_data_width-1 downto 0);
signal buf_dat_out : std_logic_vector(c_tb_data_width-1 downto 0);
--==============================================================================
-- architecture begin
......@@ -803,7 +868,6 @@ begin
port map (
rst_n_i => rst_20_n,
clk_sys_i => clk_20_vcxo_i,
clk_wr_i => clk_125,
wb_adr_i => xbar_master_out(c_slv_conv_regs).adr(5 downto 2),
wb_dat_i => xbar_master_out(c_slv_conv_regs).dat,
......@@ -815,7 +879,7 @@ begin
wb_ack_o => xbar_master_in (c_slv_conv_regs).ack,
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
reg_id_bits_i => c_board_id,
reg_bidr_i => c_board_id,
reg_sr_gwvers_i => c_gwvers,
reg_sr_switches_i => switches_n,
reg_sr_rtm_i => rtm_lines,
......@@ -858,14 +922,18 @@ begin
reg_tvhr_i => tm_tai(39 downto 32),
reg_tvhr_load_o => tvhr_ld,
reg_tf_wr_req_i => fifo_wr_req_p,
reg_tf_wr_full_o => fifo_full,
reg_tf_wr_empty_o => fifo_empty,
reg_tf_chan_i => fifo_chan,
reg_tf_wrtag_i => fifo_wrtag,
reg_tf_cyc_i => tm_cycles,
reg_tf_tai_l_i => tm_tai(31 downto 0),
reg_tf_tai_h_i => tm_tai(39 downto 32)
reg_tbmr_chan_i => buf_dat_out( 5 downto 0),
reg_tbmr_wrtag_i => buf_dat_out( 6),
reg_tb_rd_req_p_o => buf_rd_req_p,
reg_tbcyr_i => buf_dat_out(34 downto 7),
reg_tbtlr_i => buf_dat_out(66 downto 35),
reg_tbthr_i => buf_dat_out(74 downto 67),
reg_tbcsr_clr_o => buf_clr_bit,
reg_tbcsr_clr_i => '0',
reg_tbcsr_clr_load_o => buf_clr_bit_ld,
reg_tbcsr_usedw_i => buf_count,
reg_tbcsr_full_i => buf_full,
reg_tbcsr_empty_i => buf_empty
);
-- Implement the RST_UNLOCK bit
......@@ -909,10 +977,25 @@ begin
(
clk_i => clk_20_vcxo_i,
rst_n_i => rst_20_n,
data_i => fifo_wrtag,
data_i => buf_wrtag,
synced_o => wrpres
);
-- Implement the TBCSR.CLR bit
p_tbcsr_clr : process (clk_20_vcxo_i)
begin
if rising_edge(clk_20_vcxo_i) then
if (rst_20_n = '0') then
buf_clr_p <= '0';
else
buf_clr_p <= '0';
if (buf_clr_bit_ld = '1') and (buf_clr_bit = '1') then
buf_clr_p <= '1';
end if;
end if;
end if;
end process p_tbcsr_clr;
--============================================================================
-- Output enable logic
--============================================================================
......@@ -927,7 +1010,7 @@ begin
------------------------------------------------------------------------------
-- Pulse time-tagging logic after input channel MUX
------------------------------------------------------------------------------
cmp_pulse_timetag : pulse_timetag
cmp_pulse_timetag : conv_pulse_timetag
generic map
(
-- Frequency in Hz of the clk_i signal
......@@ -958,12 +1041,44 @@ begin
-- Timing outputs
tm_cycles_o => tm_cycles,
tm_tai_o => tm_tai,
tm_wrpres_o => fifo_wrtag,
chan_o => fifo_chan,
tm_wrpres_o => buf_wrtag,
chan_o => buf_chan,
-- FIFO I/O
fifo_full_i => fifo_full,
fifo_wr_req_p_o => fifo_wr_req_p
-- Ring buffer I/O
buf_wr_req_p_o => buf_wr_req_p
);
-- Assign ring buffer component inputs
buf_dat_in( 5 downto 0) <= buf_chan;
buf_dat_in( 6) <= buf_wrtag;
buf_dat_in(34 downto 7) <= tm_cycles;
buf_dat_in(74 downto 35) <= tm_tai;
-- Instantiate the ring buffer
cmp_ring_buf : conv_ring_buf
generic map
(
g_data_width => c_tb_data_width,
g_size => c_tb_size
)
port map
(
-- Clocks and reset
clk_rd_i => clk_20_vcxo_i,
clk_wr_i => clk_125,
rst_n_a_i => rst_20_n,
-- Buffer inputs
buf_dat_i => buf_dat_in,
buf_rd_req_i => buf_rd_req_p,
buf_wr_req_i => buf_wr_req_p,
buf_clr_i => buf_clr_p,
-- Buffer outputs
buf_dat_o => buf_dat_out,
buf_full_o => buf_full,
buf_empty_o => buf_empty,
buf_count_o => buf_count
);
------------------------------------------------------------------------------
......@@ -1102,7 +1217,8 @@ begin
cmp_pulse_gen : conv_pulse_gen
generic map
(
g_pwidth => 24
g_pwidth => c_pulse_gen_pwidth,
g_duty_cycle_div => c_pulse_gen_duty_cycle_div
)
port map
(
......
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