Changing gateware version to v4.0

This commit contains the addition of a dedicated hardware module to interface to the DS18B20 thermometer chip instead of the Wishbone one-wire master that was previously implemented.

Changing gateware version to v4.0
This commit contains the addition of a dedicated hardware module to interface to the DS18B20 thermometer chip instead of the Wishbone one-wire master that was previously implemented.
93240baa · Theodor-Adrian Stana · 10351064 · 6da4b6e4 · 93240baa · 93240baa
Commit 93240baa authored Feb 15, 2015 by Theodor-Adrian Stana
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Showing with 120 additions and 117 deletions

conv-common-gw ip_cores/conv-common-gw +1 -1

conv_ttl_blo.xise syn/Release/conv_ttl_blo.xise +118 -115

conv_ttl_blo.vhd top/Release/conv_ttl_blo.vhd +1 -1

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--- a/conv-common-gw @ 6da4b6e4
+++ b/conv-common-gw @ 6da4b6e4
-Subproject commit 3ae0cfc27599e426d1eeb47bb4312a88a4aff160
+Subproject commit 6da4b6e4ec50b6a429d6ab42b07ffb7853a6e0aa
--- a/syn/Release/conv_ttl_blo.xise
+++ b/syn/Release/conv_ttl_blo.xise
--- a/top/Release/conv_ttl_blo.vhd
+++ b/top/Release/conv_ttl_blo.vhd
@@ -164,7 +164,7 @@ architecture arch of conv_ttl_blo is
  constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";

  -- Gateware version
-  constant c_gwvers   : std_logic_vector(7 downto 0) := x"30";
+  constant c_gwvers   : std_logic_vector(7 downto 0) := x"40";

  --============================================================================
  -- Type declarations