Basic pulse repetition operational. Folder structure pretty much the same as…

Basic pulse repetition operational. Folder structure pretty much the same as before, but pulse repetition files exist in <pulse_generator> folder. <release> folder holds release version for the firmware.

Basic pulse repetition operational. Folder structure pretty much the same as…
Basic pulse repetition operational. Folder structure pretty much the same as before, but pulse repetition files exist in <pulse_generator> folder. <release> folder holds release version for the firmware.
93fd7399 · Theodor-Adrian Stana · d428cec8 · 93fd7399 · 93fd7399 · 93fd7399
Commit 93fd7399 authored Mar 06, 2013 by Theodor-Adrian Stana
49 changed files
--- a/hdl/IMAGES/image1/project/image1.xise
+++ b/hdl/IMAGES/image1/project/image1.xise
@@ -143,10 +143,6 @@
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
    </file>
-    <file xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
-    </file>
    <file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>

--- a/hdl/bicolor_led_ctrl/Manifest.py
+++ b/hdl/bicolor_led_ctrl/Manifest.py
+files = [
+      "bicolor_led_ctrl_pkg.vhd",
+      "bicolor_led_ctrl.vhd"
+    ]
--- a/hdl/old_rep_test/rtl/pulse_gen.vhd
+++ b/hdl/old_rep_test/rtl/pulse_gen.vhd
@@ -48,7 +48,7 @@ entity pulse_gen is
  port
  (
    clk_i   : in  std_logic;
-    rst_i   : in  std_logic;
+    rst_n_i : in  std_logic;
    pulse_o : out std_logic
  );
 end entity pulse_gen;
@@ -100,7 +100,7 @@ begin
  p_gen_pulse: process(clk_i)
  begin
    if rising_edge(clk_i) then
-      if (rst_i = '1') then
+      if (rst_n_i = '0') then
        freq_cnt  <= (others => '0');
        pulse     <= '0';
      else

--- a/hdl/pulse_generator/Manifest.py
+++ b/hdl/pulse_generator/Manifest.py
+modules = {
+      "local" : "rtl"
+    }
--- a/hdl/pulse_generator/rtl/Manifest.py
+++ b/hdl/pulse_generator/rtl/Manifest.py
+files = [
+    "pulse_generator.vhd"
+    ]
--- a/hdl/pulse_generator/rtl/pulse_generator.vhd
+++ b/hdl/pulse_generator/rtl/pulse_generator.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Pulse generator with trigger
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-03-01
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-03-01   Theodor Stana     t.stana@cern.ch     File created
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pulse_generator is
+  generic 
+  (
+    g_pulse_len_nr_bits : natural := 9;
+    g_glitch_filt_len   : natural := 6
+  );
+  port
+  (
+    clk_i       : in  std_logic;
+    rst_n_i     : in  std_logic;
+    pulse_len_i : in  std_logic_vector(g_pulse_len_nr_bits-1 downto 0);
+    level_i     : in  std_logic;
+    trig_i      : in  std_logic;
+    pulse_o     : out std_logic
+  );
+end entity pulse_generator;
+
+
+architecture behav of pulse_generator is
+
+  --============================================================================
+  -- Type declarations
+  --============================================================================
+
+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+
+  --============================================================================
+  -- Component declarations
+  --============================================================================
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal len_cnt       : unsigned(g_pulse_len_nr_bits-1 downto 0);
+  signal reject_cnt    : unsigned(g_pulse_len_nr_bits-1 downto 0);
+  signal pulse_len     : unsigned(g_pulse_len_nr_bits-1 downto 0);
+  signal pulse         : std_logic;
+  signal pulse_reject  : std_logic;
+  signal trig          : std_logic;
+  signal level, level_n : std_logic;
+  signal level_arr     : std_logic_vector(g_glitch_filt_len downto 0);
+  signal glitch_filt   : std_logic_vector(g_glitch_filt_len downto 0);
+  signal glitch_filt_d0 : std_logic;
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  --============================================================================
+  -- I/O logic
+  --============================================================================
+  -- Inputs
+  trig      <= trig_i;
+  level     <= level_i;
+  level_n   <= not level;
+  level_arr <= (others => level);
+  pulse_len <= unsigned(pulse_len_i);
+
+  -- Output
+  pulse_o <= pulse or trig when (level = '1') else
+             pulse or (not trig);
+
+  --============================================================================
+  -- Glitch filtration logic
+  --============================================================================
+  glitch_filt(0) <= trig;
+  gen_glitch_filt: if (g_glitch_filt_len > 0) generate
+    p_glitch_filt: process (clk_i)
+    begin
+      if rising_edge(clk_i) then
+        if (rst_n_i = '0') then
+          glitch_filt(g_glitch_filt_len downto 1) <= (others => '0');
+        else
+          glitch_filt(g_glitch_filt_len downto 1) <= glitch_filt(g_glitch_filt_len-1 downto 0);
+        end if;
+      end if;
+    end process p_glitch_filt;
+  end generate gen_glitch_filt;
+
+  --============================================================================
+  -- Pulse generation logic
+  --============================================================================
+  p_gen_pulse: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (rst_n_i = '0') then
+        len_cnt      <= (others => '0');
+        reject_cnt   <= (others => '0');
+        pulse        <= '0';
+        pulse_reject <= '0';
+        glitch_filt_d0 <= '0';
+      else
+        glitch_filt_d0 <= glitch_filt(g_glitch_filt_len);
+        if (glitch_filt = level_arr) and (glitch_filt_d0 = level_n) then -- (pulse_reject = '0') then
+          pulse <= '1';
+        end if;
+
+        if (pulse = '1') then
+          len_cnt <= len_cnt + 1;
+
+          -- Reset pulse length counter when reached max length. The max length 
+          -- is given by the module input, minus the glitch filter length (due
+          -- to the flip-flops the pulse goes through). 
+          --
+          -- The "-2" is first because the counter starts from zero, thus the max 
+          -- length should be pulse_len-1, and second because the pulse is set 
+          -- on the clock edge following the glitch filter output settling to all
+          -- ones.
+          if (len_cnt = pulse_len-g_glitch_filt_len-2) then
+            len_cnt      <= (others => '0');
+            pulse        <= '0';
+            pulse_reject <= '1';
+          end if;
+        end if;
+
+        if (pulse_reject = '1') then
+          reject_cnt <= reject_cnt + 1;
+          if (reject_cnt = pulse_len-1) then
+            reject_cnt <= (others => '0');
+            pulse_reject <= '0';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process p_gen_pulse;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/hdl/pulse_generator/sim/run.do
+++ b/hdl/pulse_generator/sim/run.do
+vlib work
+
+vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
+vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
+vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
+
+vcom -explicit -93 "../../old_rep_test/rtl/pulse_gen.vhd"
+vcom -explicit -93 "../rtl/pulse_generator.vhd"
+vcom -explicit -93 "testbench.vhd"
+
+vsim -t 1ps -voptargs="+acc" -lib work work.testbench
+
+radix -hexadecimal
+# add wave *
+do wave.do
+
+run 100 us
+wave zoomfull
--- a/hdl/pulse_generator/sim/testbench.vhd
+++ b/hdl/pulse_generator/sim/testbench.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Testbench for old repeater design
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-02-28
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-02-28   Theodor Stana     t.stana@cern.ch     File created
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity testbench is
+end entity testbench;
+
+
+architecture behav of testbench is
+
+  --============================================================================
+  -- Type declarations
+  --============================================================================
+
+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+  constant c_clk_per : time := 5 ns;
+  constant c_reset_width : time := 31 ns;
+
+  --============================================================================
+  -- Component declarations
+  --============================================================================
+
+  component pulse_generator is
+    generic 
+    (
+      g_pulse_len_nr_bits : natural := 9;
+      g_glitch_filt_len   : natural := 6
+    );
+    port
+    (
+      clk_i       : in  std_logic;
+      rst_n_i       : in  std_logic;
+      pulse_len_i : in  std_logic_vector(g_pulse_len_nr_bits-1 downto 0);
+      level_i     : in  std_logic;
+      trig_i      : in  std_logic;
+      pulse_o     : out std_logic
+    );
+  end component pulse_generator;
+
+  component pulse_gen is
+    generic
+    (
+      g_pwidth : natural := 200;
+      g_freq   : natural := 400
+    );
+    port
+    (
+      clk_i   : in  std_logic;
+      rst_n_i   : in  std_logic;
+      pulse_o : out std_logic
+    );
+  end component pulse_gen;
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal clk, clk2, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
+  signal actual_trig : std_logic := '0';
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  -- DUT INSTANTIATION
+  DUT: pulse_generator
+  generic map
+  (
+    g_pulse_len_nr_bits => 9,
+    g_glitch_filt_len   => 6
+  )
+  port map
+  (
+    clk_i       => clk,
+    rst_n_i     => rst_n,
+    pulse_len_i => std_logic_vector(to_unsigned(200,9)),
+    level_i     => lvl_n,
+    trig_i      => actual_trig,
+    pulse_o     => pulse
+  );
+
+  -- CLOCK GENERATION
+  p_clk: process
+  begin
+    clk <= not clk;
+    wait for c_clk_per/2;
+  end process p_clk;
+
+  -- SECOND CLOCK GENERATION
+  p_clk2: process
+  begin
+    clk2 <= not clk2;
+    wait for 2 ns;
+  end process p_clk2;
+
+  -- RESET GENERATION
+  p_rst_n: process
+  begin
+    rst_n <= '0';
+    wait for c_reset_width;
+    rst_n <= '1';
+    wait;
+  end process p_rst_n;
+
+  -- PULSE GENERATOR FOR TRIGGER
+  cmp_pulse_gen: pulse_gen
+  generic map
+  (
+    g_pwidth => 100,
+    g_freq   => 2000
+  )
+  port map
+  (
+    clk_i   => clk,
+    rst_n_i => rst_n,
+    pulse_o => trig
+  );
+  actual_trig <= not trig; --trig when lvl = '0' else not trig;
+  
+  lvl_n <= not lvl;
+  
+  
+  
+  lvl <= '0';
+
+  --trig <= '1';
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/hdl/pulse_generator/sim/transcript
+++ b/hdl/pulse_generator/sim/transcript
--- a/hdl/pulse_generator/sim/wave.do
+++ b/hdl/pulse_generator/sim/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/rst_n
+add wave -noupdate /testbench/pulse
+add wave -noupdate /testbench/trig
+add wave -noupdate -divider internal
+add wave -noupdate /testbench/DUT/pulse_len_i
+add wave -noupdate /testbench/DUT/len_cnt
+add wave -noupdate /testbench/DUT/pulse_len
+add wave -noupdate /testbench/DUT/pulse
+add wave -noupdate /testbench/DUT/glitch_filt
+add wave -noupdate /testbench/DUT/trig
+add wave -noupdate /testbench/DUT/level_i
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 2} {12112676 ps} 0}
+configure wave -namecolwidth 233
+configure wave -valuecolwidth 91
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {105 us}
--- a/hdl/pulse_generator/syn/Makefile
+++ b/hdl/pulse_generator/syn/Makefile
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := conv_ttl_blo_v2.xise
+ISE_CRAP := *.b conv_ttl_blo_v2_summary.html *.tcl conv_ttl_blo_v2.bld conv_ttl_blo_v2.cmd_log *.drc conv_ttl_blo_v2.lso *.ncd conv_ttl_blo_v2.ngc conv_ttl_blo_v2.ngd conv_ttl_blo_v2.ngr conv_ttl_blo_v2.pad conv_ttl_blo_v2.par conv_ttl_blo_v2.pcf conv_ttl_blo_v2.prj conv_ttl_blo_v2.ptwx conv_ttl_blo_v2.stx conv_ttl_blo_v2.syr conv_ttl_blo_v2.twr conv_ttl_blo_v2.twx conv_ttl_blo_v2.gise conv_ttl_blo_v2.unroutes conv_ttl_blo_v2.ut conv_ttl_blo_v2.xpi conv_ttl_blo_v2.xst conv_ttl_blo_v2_bitgen.xwbt conv_ttl_blo_v2_envsettings.html conv_ttl_blo_v2_guide.ncd conv_ttl_blo_v2_map.map conv_ttl_blo_v2_map.mrp conv_ttl_blo_v2_map.ncd conv_ttl_blo_v2_map.ngm conv_ttl_blo_v2_map.xrpt conv_ttl_blo_v2_ngdbuild.xrpt conv_ttl_blo_v2_pad.csv conv_ttl_blo_v2_pad.txt conv_ttl_blo_v2_par.xrpt conv_ttl_blo_v2_summary.xml conv_ttl_blo_v2_usage.xml conv_ttl_blo_v2_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
+		xtclsh run.tcl
+
+
+#target for cleaing all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+    
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
+USER:=$(HDLMAKE_USER)#take the value from the environment
+SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
+R_NAME:=conv_ttl_blo_v2
+
+__test_for_remote_synthesis_variables:
+ifeq (x$(USER),x)
+	@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
+endif
+ifeq (x$(SERVER),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
+endif
+
+CWD := $(shell pwd)
+
+FILES := ../rtl/pulse_generator.vhd \
+../top/conv_ttl_blo_v2.ucf \
+../top/conv_ttl_blo_v2.vhd \
+run.tcl \
+conv_ttl_blo_v2.xise
+
+#target for running simulation in the remote location
+remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
+__send_back: __do_synthesis
+__do_synthesis: __send
+__send: __test_for_remote_synthesis_variables
+
+__send:
+		ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
+		rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
+
+__do_synthesis:
+		ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
+
+__send_back: 
+		cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
+
+#target for removing stuff from the remote location
+cleanremote:
+		ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
+
--- a/hdl/pulse_generator/syn/Manifest.py
+++ b/hdl/pulse_generator/syn/Manifest.py
+target = "xilinx"
+action = "synthesis"
+syn_device  = "xc6slx45t"
+syn_grade   = "-3"
+syn_package = "fgg484"
+syn_top     = "conv_ttl_blo_v2"
+syn_project = "conv_ttl_blo_v2.xise"
+
+modules = {
+    "local" : [
+      "../rtl",
+      "../top"
+      ]
+    }
--- a/hdl/pulse_generator/syn/conv_ttl_blo_v2.bit
+++ b/hdl/pulse_generator/syn/conv_ttl_blo_v2.bit
--- a/hdl/pulse_generator/syn/conv_ttl_blo_v2.gise
+++ b/hdl/pulse_generator/syn/conv_ttl_blo_v2.gise
--- a/hdl/pulse_generator/syn/conv_ttl_blo_v2.ppr
+++ b/hdl/pulse_generator/syn/conv_ttl_blo_v2.ppr
+<?xml version="1.0"?>
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="c08f74f5ee304d6b8a6ee13247e8885d"/>
+		<Option Name="Part" Val="xc6slx45tfgg484-3"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compxlib"/>
+		<Option Name="TargetLanguage" Val="VHDL"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
+		<Option Name="ActiveSimSet" Val=""/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
--- a/hdl/pulse_generator/syn/conv_ttl_blo_v2.xise
+++ b/hdl/pulse_generator/syn/conv_ttl_blo_v2.xise
--- a/hdl/pulse_generator/syn/run.tcl
+++ b/hdl/pulse_generator/syn/run.tcl
+project open conv_ttl_blo_v2.xise
+process run {Generate Programming File} -force rerun_all
--- a/hdl/pulse_generator/top/Manifest.py
+++ b/hdl/pulse_generator/top/Manifest.py
+files = [
+      "conv_ttl_blo_v2.ucf",
+      "conv_ttl_blo_v2.vhd"
+    ]
--- a/hdl/pulse_generator/top/conv_ttl_blo_v2.ucf
+++ b/hdl/pulse_generator/top/conv_ttl_blo_v2.ucf
--- a/hdl/pulse_generator/top/conv_ttl_blo_v2.vhd
+++ b/hdl/pulse_generator/top/conv_ttl_blo_v2.vhd
--- a/hdl/release/syn/Makefile
+++ b/hdl/release/syn/Makefile
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := conv_ttl_blo_v2.xise
+ISE_CRAP := *.b conv_ttl_blo_v2_summary.html *.tcl conv_ttl_blo_v2.bld conv_ttl_blo_v2.cmd_log *.drc conv_ttl_blo_v2.lso *.ncd conv_ttl_blo_v2.ngc conv_ttl_blo_v2.ngd conv_ttl_blo_v2.ngr conv_ttl_blo_v2.pad conv_ttl_blo_v2.par conv_ttl_blo_v2.pcf conv_ttl_blo_v2.prj conv_ttl_blo_v2.ptwx conv_ttl_blo_v2.stx conv_ttl_blo_v2.syr conv_ttl_blo_v2.twr conv_ttl_blo_v2.twx conv_ttl_blo_v2.gise conv_ttl_blo_v2.unroutes conv_ttl_blo_v2.ut conv_ttl_blo_v2.xpi conv_ttl_blo_v2.xst conv_ttl_blo_v2_bitgen.xwbt conv_ttl_blo_v2_envsettings.html conv_ttl_blo_v2_guide.ncd conv_ttl_blo_v2_map.map conv_ttl_blo_v2_map.mrp conv_ttl_blo_v2_map.ncd conv_ttl_blo_v2_map.ngm conv_ttl_blo_v2_map.xrpt conv_ttl_blo_v2_ngdbuild.xrpt conv_ttl_blo_v2_pad.csv conv_ttl_blo_v2_pad.txt conv_ttl_blo_v2_par.xrpt conv_ttl_blo_v2_summary.xml conv_ttl_blo_v2_usage.xml conv_ttl_blo_v2_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
+		xtclsh run.tcl
+
+
+#target for cleaing all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+    
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
+USER:=$(HDLMAKE_USER)#take the value from the environment
+SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
+R_NAME:=conv_ttl_blo_v2
+
+__test_for_remote_synthesis_variables:
+ifeq (x$(USER),x)
+	@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
+endif
+ifeq (x$(SERVER),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
+endif
+
+CWD := $(shell pwd)
+
+FILES := ../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
+../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
+../top/conv_ttl_blo_v2.ucf \
+../top/conv_ttl_blo_v2.vhd \
+../../reset_gen/rtl/reset_gen.vhd \
+../../pulse_generator/rtl/pulse_generator.vhd \
+../../rtm_detector/rtl/rtm_detector.vhd \
+run.tcl \
+conv_ttl_blo_v2.xise
+
+#target for running simulation in the remote location
+remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
+__send_back: __do_synthesis
+__do_synthesis: __send
+__send: __test_for_remote_synthesis_variables
+
+__send:
+		ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
+		rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
+
+__do_synthesis:
+		ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
+
+__send_back: 
+		cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
+
+#target for removing stuff from the remote location
+cleanremote:
+		ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
+
--- a/hdl/release/syn/Manifest.py
+++ b/hdl/release/syn/Manifest.py
+target = "xilinx"
+action = "synthesis"
+syn_device  = "xc6slx45t"
+syn_grade   = "-3"
+syn_package = "fgg484"
+syn_top     = "conv_ttl_blo_v2"
+syn_project = "conv_ttl_blo_v2.xise"
+
+modules = {
+    "local" : [
+      "../../reset_gen",
+      "../../pulse_generator",
+      "../../rtm_detector",
+      "../../bicolor_led_ctrl",
+      "../top"
+      ]
+    }
--- a/hdl/release/syn/conv_ttl_blo_v2.bit
+++ b/hdl/release/syn/conv_ttl_blo_v2.bit
--- a/hdl/release/syn/conv_ttl_blo_v2.gise
+++ b/hdl/release/syn/conv_ttl_blo_v2.gise
--- a/hdl/release/syn/conv_ttl_blo_v2.xise
+++ b/hdl/release/syn/conv_ttl_blo_v2.xise
--- a/hdl/release/syn/run.tcl
+++ b/hdl/release/syn/run.tcl
+project open conv_ttl_blo_v2.xise
+process run {Generate Programming File} -force rerun_all
--- a/hdl/release/top/Manifest.py
+++ b/hdl/release/top/Manifest.py
+files = [
+      "conv_ttl_blo_v2.ucf",
+      "conv_ttl_blo_v2.vhd"
+    ]
--- a/hdl/release/top/conv_ttl_blo_v2.ucf
+++ b/hdl/release/top/conv_ttl_blo_v2.ucf
--- a/hdl/release/top/conv_ttl_blo_v2.vhd
+++ b/hdl/release/top/conv_ttl_blo_v2.vhd
--- a/hdl/reset_gen/Manifest.py
+++ b/hdl/reset_gen/Manifest.py
+modules = {"local" : "rtl"}
--- a/hdl/reset_gen/rtl/Manifest.py
+++ b/hdl/reset_gen/rtl/Manifest.py
+files = ["reset_gen.vhd"]
--- a/hdl/reset_gen/rtl/reset_gen.vhd
+++ b/hdl/reset_gen/rtl/reset_gen.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Reset generator for CONV-TTL-* boards
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-03-05
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-03-05   Theodor Stana     t.stana@cern.ch     File created
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity reset_gen is
+  generic
+  (
+    -- Reset time in number of clk_i cycles
+    g_reset_time : positive := 5_000_000
+  );
+  port
+  (
+    clk_i   : in  std_logic;
+    rst_n_o : out std_logic
+  );
+end entity reset_gen;
+
+
+architecture behav of reset_gen is
+
+  --============================================================================
+  -- Function and procedure declarations
+  --============================================================================
+  function f_log2_size (A : natural) return natural is
+  begin
+    for I in 1 to 64 loop               -- Works for up to 64 bits
+      if (2**I >= A) then
+        return(I);
+      end if;
+    end loop;
+    return(63);
+  end function f_log2_size;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal cnt    : unsigned(f_log2_size(g_reset_time)-1 downto 0) := (others => '0');
+  signal cnt_en : std_logic := '1';
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  --============================================================================
+  -- Reset generation logic
+  --============================================================================
+  p_rst_gen: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if (cnt_en = '1') then
+        rst_n_o <= '0';
+        cnt     <= cnt + 1;
+        if (cnt = g_reset_time) then
+          rst_n_o <= '1';
+          cnt_en  <= '0';
+        end if;
+      end if;
+    end if;
+  end process p_rst_gen;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/hdl/reset_gen/sim/run.do
+++ b/hdl/reset_gen/sim/run.do
+vlib work
+
+vcom -explicit -93 "../rtl/reset_gen.vhd"
+vcom -explicit -93 "testbench.vhd"
+
+vsim -t 1ps -voptargs="+acc" -lib work work.testbench
+
+radix -hexadecimal
+add wave *
+# do wave.do
+
+run 250 ms
+wave zoomfull
--- a/hdl/reset_gen/sim/testbench.vhd
+++ b/hdl/reset_gen/sim/testbench.vhd
+--==============================================================================
+-- CERN (BE-CO-HT)
+-- Testbench for old repeater design
+--==============================================================================
+--
+-- author: Theodor Stana (t.stana@cern.ch)
+--
+-- date of creation: 2013-02-28
+--
+-- version: 1.0
+--
+-- description: 
+--
+-- dependencies:
+--
+-- references:
+-- 
+--==============================================================================
+-- GNU LESSER GENERAL PUBLIC LICENSE
+--==============================================================================
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version. This source is distributed in the hope that it
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+-- See the GNU Lesser General Public License for more details. You should have
+-- received a copy of the GNU Lesser General Public License along with this
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
+--==============================================================================
+-- last changes:
+--    2013-02-28   Theodor Stana     t.stana@cern.ch     File created
+--==============================================================================
+-- TODO: - 
+--==============================================================================
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity testbench is
+end entity testbench;
+
+
+architecture behav of testbench is
+
+  --============================================================================
+  -- Constant declarations
+  --============================================================================
+  constant c_clk_per : time := 20 ns;
+  constant c_reset_width : time := 31 ns;
+
+  --============================================================================
+  -- Component declarations
+  --============================================================================
+  component reset_gen is
+    generic
+    (
+    -- Reset time in number of clk_i cycles
+      g_reset_time : positive := 5_000_000
+    );
+    port
+    (
+      clk_i   : in  std_logic;
+      rst_n_o : out std_logic
+    );
+  end component reset_gen;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal clk, rst_n : std_logic := '0';
+
+--==============================================================================
+--  architecture begin
+--==============================================================================
+begin
+
+  -- DUT INSTANTIATION
+  DUT: reset_gen
+    generic map
+    (
+      g_reset_time => 2500000
+    )
+    port map
+    (
+      clk_i   => clk,
+      rst_n_o => rst_n
+    );
+
+  -- CLOCK GENERATION
+  p_clk: process
+  begin
+    clk <= not clk;
+    wait for c_clk_per/2;
+  end process p_clk;
+
+end architecture behav;
+--==============================================================================
+--  architecture end
+--==============================================================================
--- a/hdl/reset_gen/sim/transcript
+++ b/hdl/reset_gen/sim/transcript
+# //  ModelSim SE 10.1 Dec  5 2011 Linux 3.2.0-38-generic-pae
+# //
+# //  Copyright 1991-2011 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
+# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
+# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+# //
+#  
+do run.do
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity reset_gen
+# -- Compiling architecture behav of reset_gen
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity testbench
+# -- Compiling architecture behav of testbench
+# ** Error: testbench.vhd(89): near ";": expecting ',' or ')'
+# ** Error: testbench.vhd(93): Statement cannot be labeled.
+# ** Error: testbench.vhd(99): VHDL Compiler exiting
+# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
+# Error in macro ./run.do line 4
+# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
+#     while executing
+# "vcom -explicit -93 "testbench.vhd""
+do run.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity reset_gen
+# -- Compiling architecture behav of reset_gen
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity testbench
+# -- Compiling architecture behav of testbench
+# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench 
+# ** Note: (vsim-3812) Design is being optimized...
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.testbench(behav)#1
+# Loading work.reset_gen(behav)#1
+# hexadecimal
+# 0 ps
+# 1050 ms
+do run.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity reset_gen
+# -- Compiling architecture behav of reset_gen
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity testbench
+# -- Compiling architecture behav of testbench
+# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench 
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.testbench(behav)#1
+# Loading work.reset_gen(behav)#1
+# hexadecimal
+# 0 ps
+# 1050 ms
+do run.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity reset_gen
+# -- Compiling architecture behav of reset_gen
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity testbench
+# -- Compiling architecture behav of testbench
+# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench 
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.testbench(behav)#1
+# Loading work.reset_gen(behav)#1
+# hexadecimal
+# 0 ps
+# 262500 us
+do run.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity reset_gen
+# -- Compiling architecture behav of reset_gen
+# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package NUMERIC_STD
+# -- Compiling entity testbench
+# -- Compiling architecture behav of testbench
+# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench 
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.testbench(behav)#1
+# Loading work.reset_gen(behav)#1
+# hexadecimal
+# 0 ps
+# 262500 us
--- a/hdl/reset_gen/syn/Makefile
+++ b/hdl/reset_gen/syn/Makefile
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := conv_ttl_blo_v2.xise
+ISE_CRAP := *.b conv_ttl_blo_v2_summary.html *.tcl conv_ttl_blo_v2.bld conv_ttl_blo_v2.cmd_log *.drc conv_ttl_blo_v2.lso *.ncd conv_ttl_blo_v2.ngc conv_ttl_blo_v2.ngd conv_ttl_blo_v2.ngr conv_ttl_blo_v2.pad conv_ttl_blo_v2.par conv_ttl_blo_v2.pcf conv_ttl_blo_v2.prj conv_ttl_blo_v2.ptwx conv_ttl_blo_v2.stx conv_ttl_blo_v2.syr conv_ttl_blo_v2.twr conv_ttl_blo_v2.twx conv_ttl_blo_v2.gise conv_ttl_blo_v2.unroutes conv_ttl_blo_v2.ut conv_ttl_blo_v2.xpi conv_ttl_blo_v2.xst conv_ttl_blo_v2_bitgen.xwbt conv_ttl_blo_v2_envsettings.html conv_ttl_blo_v2_guide.ncd conv_ttl_blo_v2_map.map conv_ttl_blo_v2_map.mrp conv_ttl_blo_v2_map.ncd conv_ttl_blo_v2_map.ngm conv_ttl_blo_v2_map.xrpt conv_ttl_blo_v2_ngdbuild.xrpt conv_ttl_blo_v2_pad.csv conv_ttl_blo_v2_pad.txt conv_ttl_blo_v2_par.xrpt conv_ttl_blo_v2_summary.xml conv_ttl_blo_v2_usage.xml conv_ttl_blo_v2_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
+		xtclsh run.tcl
+
+
+#target for cleaing all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+    
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
+USER:=$(HDLMAKE_USER)#take the value from the environment
+SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
+R_NAME:=conv_ttl_blo_v2
+
+__test_for_remote_synthesis_variables:
+ifeq (x$(USER),x)
+	@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
+endif
+ifeq (x$(SERVER),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
+endif
+
+CWD := $(shell pwd)
+
+FILES := ../rtl/reset_gen.vhd \
+../top/conv_ttl_blo_v2.ucf \
+../top/conv_ttl_blo_v2.vhd \
+run.tcl \
+conv_ttl_blo_v2.xise
+
+#target for running simulation in the remote location
+remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
+__send_back: __do_synthesis
+__do_synthesis: __send
+__send: __test_for_remote_synthesis_variables
+
+__send:
+		ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
+		rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
+
+__do_synthesis:
+		ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
+
+__send_back: 
+		cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
+
+#target for removing stuff from the remote location
+cleanremote:
+		ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
+
--- a/hdl/reset_gen/syn/Manifest.py
+++ b/hdl/reset_gen/syn/Manifest.py
+target = "xilinx"
+action = "synthesis"
+syn_device  = "xc6slx45t"
+syn_grade   = "-3"
+syn_package = "fgg484"
+syn_top     = "conv_ttl_blo_v2"
+syn_project = "conv_ttl_blo_v2.xise"
+
+modules = {
+    "local" : [
+      "../rtl",
+      "../top"
+      ]
+    }
--- a/hdl/reset_gen/syn/conv_ttl_blo_v2.bit
+++ b/hdl/reset_gen/syn/conv_ttl_blo_v2.bit
--- a/hdl/reset_gen/syn/conv_ttl_blo_v2.gise
+++ b/hdl/reset_gen/syn/conv_ttl_blo_v2.gise
--- a/hdl/reset_gen/syn/conv_ttl_blo_v2.ppr
+++ b/hdl/reset_gen/syn/conv_ttl_blo_v2.ppr
+<?xml version="1.0"?>
+<Project Version="4" Minor="36">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<FileSet Dir="sim_1" File="fileset.xml"/>
+	<RunSet Dir="runs" File="runs.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Id" Val="0cf3dbab5dac4bc0bc49e09ec271be31"/>
+		<Option Name="Part" Val="xc6slx45tfgg484-3"/>
+		<Option Name="CompiledLibDir" Val="$PCACHEDIR/compxlib"/>
+		<Option Name="TargetLanguage" Val="VHDL"/>
+		<Option Name="TargetSimulator" Val="ISim"/>
+		<Option Name="Board" Val=""/>
+		<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
+		<Option Name="ActiveSimSet" Val=""/>
+		<Option Name="CxlOverwriteLibs" Val="1"/>
+		<Option Name="CxlFuncsim" Val="1"/>
+		<Option Name="CxlTimesim" Val="1"/>
+		<Option Name="CxlCore" Val="1"/>
+		<Option Name="CxlEdk" Val="0"/>
+		<Option Name="CxlExcludeCores" Val="1"/>
+		<Option Name="CxlExcludeSubLibs" Val="0"/>
+	</Config>
+</Project>
+
--- a/hdl/reset_gen/syn/conv_ttl_blo_v2.xise
+++ b/hdl/reset_gen/syn/conv_ttl_blo_v2.xise
--- a/hdl/reset_gen/syn/run.tcl
+++ b/hdl/reset_gen/syn/run.tcl
+project open conv_ttl_blo_v2.xise
+process run {Generate Programming File} -force rerun_all
--- a/hdl/reset_gen/top/Manifest.py
+++ b/hdl/reset_gen/top/Manifest.py
+files = [
+      "conv_ttl_blo_v2.ucf",
+      "conv_ttl_blo_v2.vhd"
+    ]
--- a/hdl/reset_gen/top/conv_ttl_blo_v2.ucf
+++ b/hdl/reset_gen/top/conv_ttl_blo_v2.ucf
--- a/hdl/reset_gen/top/conv_ttl_blo_v2.vhd
+++ b/hdl/reset_gen/top/conv_ttl_blo_v2.vhd
--- a/hdl/rtm_detector/.gitignore
+++ b/hdl/rtm_detector/.gitignore
-#Ignore swap files
-rtl/.*.*.swo
-rtl/.*.*.swp
-rtl/.swp
-rtl/.swo
-
--- a/hdl/rtm_detector/Manifest.py
+++ b/hdl/rtm_detector/Manifest.py
+modules = {"local" : "rtl" }
--- a/hdl/rtm_detector/rtl/Manifest.py
+++ b/hdl/rtm_detector/rtl/Manifest.py
+files = "rtm_detector.vhd"
--- a/hdl/rtm_detector/rtl/rtm_detector_pkg.vhd
+++ b/hdl/rtm_detector/rtl/rtm_detector_pkg.vhd