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Conv TTL Blocking - Gateware
Commit 96eb529f authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Instantiated WRPC in conv-common-gw

parent 93240baa
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Showing with 342 additions and 14 deletions
conv-common-gw @ 105019a2
Subproject commit 6da4b6e4ec50b6a429d6ab42b07ffb7853a6e0aa
Subproject commit 105019a292c6ccff0d09d884fb4d93bd9417bc04
syn/Release/conv_ttl_blo.xise
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top/Release/conv_ttl_blo.ucf
View file @ 96eb529f
......@@ -335,14 +335,16 @@ NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
#-----------------------------------------------------------------------------
# FPGA MGT lines
#-----------------------------------------------------------------------------
#NET "mgt_clk0_p_i" LOC = A10;
#NET "mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
NET "mgt_refclk0_p_i" LOC = A10;
NET "mgt_refclk0_n_i" LOC = B10;
NET "mgt_refclk0_p_i" TNM_NET = "mgt_refclk0";
TIMESPEC TS_MGT_REFCLK0 = PERIOD "mgt_refclk0" 125 MHz HIGH 50%;
NET "mgt_rx0_p_i" LOC = D7;
NET "mgt_rx0_n_i" LOC = C7;
NET "mgt_tx0_p_o" LOC = B6;
NET "mgt_tx0_n_o" LOC = A6;
#=============================================================================
# OTHER SIGNALS
......
top/Release/conv_ttl_blo.vhd
View file @ 96eb529f
......@@ -122,6 +122,14 @@ entity conv_ttl_blo is
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- FPGA Multi-Gigabit Transceiver connections
mgt_refclk0_p_i : in std_logic;
mgt_refclk0_n_i : in std_logic;
mgt_tx0_p_o : out std_logic;
mgt_tx0_n_o : out std_logic;
mgt_rx0_p_i : in std_logic;
mgt_rx0_n_i : in std_logic;
-- Thermometer data port
thermometer_b : inout std_logic;
......@@ -320,6 +328,7 @@ begin
g_with_man_trig => true,
g_man_trig_pwidth => 24,
g_with_thermometer => true,
g_with_wr => true,
g_bicolor_led_columns => c_bicolor_led_cols,
g_bicolor_led_lines => c_bicolor_led_lines
)
......@@ -384,13 +393,21 @@ begin
-- SFP lines
sfp_los_i => sfp_los_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_present_i => sfp_mod_def0_i,
sfp_rate_select_o => sfp_rate_select_o,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_scl_b => sfp_mod_def1_b,
sfp_sda_b => sfp_mod_def2_b,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_tx_fault_i => sfp_tx_fault_i,
-- FPGA Multi-Gigabit Transceiver connections
mgt_refclk0_p_i => mgt_refclk0_p_i,
mgt_refclk0_n_i => mgt_refclk0_n_i,
mgt_tx0_p_o => mgt_tx0_p_o,
mgt_tx0_n_o => mgt_tx0_n_o,
mgt_rx0_p_i => mgt_rx0_p_i,
mgt_rx0_n_i => mgt_rx0_n_i,
-- Switch inputs (for readout from converter status register)
sw_gp_i => sw_gp,
sw_other_i => (others => '0'),
......
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