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Conv TTL Blocking
Commit 00387791 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Add firmware support for TTL pulse repetition test (test01). 

Apart from this, a watchdog counter has been integrated into the
i2c_slave VHDL module; it resets the slave FSM after one second
if the master does not cycle the SCL line.
parent 8ab2fb99
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Showing with 2665 additions and 361 deletions
hdl/pts/rtl/Manifest.py
View file @ 00387791
files = [
"pts_regs.vhd",
"pulse_cnt_wb.vhd",
"incr_counter.vhd",
"clk_info_wb_slave.vhd"
]
hdl/pts/rtl/pulse_cnt_wb.vhd 0 → 100644
View file @ 00387791
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse counter registers
---------------------------------------------------------------------------------------
-- File : pulse_cnt_wb.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_wb.wb
-- Created : Thu Apr 18 18:16:52 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_cnt_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH7 output'
pulse_cnt_ch7o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH7 input'
pulse_cnt_ch7i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH8 output'
pulse_cnt_ch8o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH8 input'
pulse_cnt_ch8i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH9 output'
pulse_cnt_ch9o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH9 input'
pulse_cnt_ch9i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH10 output'
pulse_cnt_ch10o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH10 input'
pulse_cnt_ch10i_val_i : in std_logic_vector(31 downto 0)
);
end pulse_cnt_wb;
architecture syn of pulse_cnt_wb is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch7o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch7i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch8o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch8i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch9o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch9i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch10o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch10i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/pts/rtl/pulse_cnt_wb.wb 0 → 100644
View file @ 00387791
peripheral {
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
hdl_entity = "pulse_cnt_wb";
prefix = "pulse_cnt";
reg {
name = "CH1 output";
prefix = "ch1o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH1 input";
prefix = "ch1i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 output";
prefix = "ch2o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 input";
prefix = "ch2i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 output";
prefix = "ch3o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 input";
prefix = "ch3i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 output";
prefix = "ch4o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 input";
prefix = "ch4i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 output";
prefix = "ch5o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 input";
prefix = "ch5i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 output";
prefix = "ch6o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 input";
prefix = "ch6i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH7 output";
prefix = "ch7o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH7 input";
prefix = "ch7i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH8 output";
prefix = "ch8o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH8 input";
prefix = "ch8i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH9 output";
prefix = "ch9o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH9 input";
prefix = "ch9i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH10 output";
prefix = "ch10o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH10 input";
prefix = "ch10i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/pts/syn/Makefile
View file @ 00387791
......@@ -41,6 +41,7 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../rtl/pts_regs.vhd \
../rtl/pulse_cnt_wb.vhd \
../rtl/incr_counter.vhd \
../rtl/clk_info_wb_slave.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
......@@ -133,13 +134,275 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../rtm_detector/rtl/rtm_detector.vhd \
../../vme64x_i2c/rtl/i2c_slave.vhd \
../../vme64x_i2c/rtl/vme64x_i2c.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
../../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd \
../../../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd \
../../../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd \
../../../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd \
../../../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd \
../../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
../../../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
../../../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd \
../../../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd \
../../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd \
../../../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd \
../../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
../../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
../../../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
../../../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
../../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd \
../../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd \
../../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd \
../../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd \
../../../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
../../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd \
../../../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd \
../../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd \
../../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd \
../../../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd \
../../../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd \
../../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
../../../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd \
../../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
../../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
../../../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd \
../../../../ip_cores/wr-cores/modules/wrc_core/wbp_mux.vhd \
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../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
run.tcl \
conv_ttl_blo_v2.xise
......
hdl/pts/syn/conv_ttl_blo_v2.gise
View file @ 00387791
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366030704">
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<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366030704">
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366030704">
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366387848">
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<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366030704">
<transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1366387909" xil_pn:in_ck="7459507639272444710" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1366030730" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366030730">
<transform xil_pn:end_ts="1366387909" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366387909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1366030741" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366030730">
<transform xil_pn:end_ts="1366387921" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366387909">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,8 +131,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1366030831" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366030741">
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<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pcf"/>
......@@ -144,7 +145,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1366030895" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366030831">
<transform xil_pn:end_ts="1366388300" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366388222">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,8 +159,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
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<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bgn"/>
......@@ -169,7 +171,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
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<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/pts/syn/conv_ttl_blo_v2.ppr 0 → 100644
View file @ 00387791
<?xml version="1.0"?>
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
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<DefaultPromote Dir="$PROMOTEDIR"/>
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<Option Name="Board" Val=""/>
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<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>
hdl/pts/syn/conv_ttl_blo_v2.xise
View file @ 00387791
......@@ -22,6 +22,9 @@
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<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
<properties>
......@@ -81,6 +84,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -339,41 +343,47 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries/>
<libraries>
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<library xil_pn:name="fifo_generator_v6_1"/>
</libraries>
<files>
<file xil_pn:name="../top/conv_ttl_blo_v2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../top/conv_ttl_blo_v2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
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<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -385,13 +395,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -415,43 +425,43 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
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......@@ -460,25 +470,25 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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......@@ -535,16 +545,16 @@
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......@@ -553,7 +563,7 @@
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......@@ -595,7 +605,7 @@
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......@@ -616,10 +626,10 @@
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......@@ -628,23 +638,889 @@
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<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<bindings/>
......
hdl/pts/top/Manifest.py
View file @ 00387791
......@@ -7,9 +7,13 @@ modules = {
"local" : [
"../../../../ip_cores/general-cores",
"../../reset_gen",
"../../pulse_generator",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../../vme64x_i2c",
"../rtl"
]
],
"git" : "git://ohwr.org/hdl-core-lib/wr-cores.git"
}
fetchto = "../../../../ip_cores"
hdl/pts/top/conv_ttl_blo_v2.ucf
View file @ 00387791
......@@ -11,7 +11,7 @@
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = "LVCMOS33";
NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "clk20_vcxo_i" LOC = E16;
TIMESPEC TS_clk_i = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
......@@ -27,60 +27,60 @@ NET "fpga_clk_n_i" LOC = G11;
##-- LEDs
##-------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = "LVCMOS33";
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = "LVCMOS33";
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = "LVCMOS33";
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = "LVCMOS33";
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = "LVCMOS33";
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = "LVCMOS33";
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = "LVCMOS33";
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = "LVCMOS33";
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = "LVCMOS33";
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = "LVCMOS33";
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-------------------
##-- Front channel LEDs
##-------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
......@@ -88,27 +88,27 @@ NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-- Rear LEDs
##-------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
......@@ -116,30 +116,36 @@ NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
###-------------------
###-- TTL trigger I/O
###-------------------
#NET "fpga_input_ttl_n_i[1]" LOC = T2;
#NET "fpga_input_ttl_n_i[1]" IOSTANDARD = "LVCMOS33";
#NET "fpga_input_ttl_n_i[2]" LOC = U3;
#NET "fpga_input_ttl_n_i[2]" IOSTANDARD = "LVCMOS33";
#NET "fpga_input_ttl_n_i[3]" LOC = V5;
#NET "fpga_input_ttl_n_i[3]" IOSTANDARD = "LVCMOS33";
#NET "fpga_input_ttl_n_i[4]" LOC = W4;
#NET "fpga_input_ttl_n_i[4]" IOSTANDARD = "LVCMOS33";
#NET "fpga_input_ttl_n_i[5]" LOC = T6;
#NET "fpga_input_ttl_n_i[5]" IOSTANDARD = "LVCMOS33";
#NET "fpga_input_ttl_n_i[6]" LOC = T3;
#NET "fpga_input_ttl_n_i[6]" IOSTANDARD = "LVCMOS33";
#NET "fpga_out_ttl_o[1]" LOC = C1;
#NET "fpga_out_ttl_o[1]" IOSTANDARD = "LVCMOS33";
#NET "fpga_out_ttl_o[2]" LOC = F2;
#NET "fpga_out_ttl_o[2]" IOSTANDARD = "LVCMOS33";
#NET "fpga_out_ttl_o[3]" LOC = F5;
#NET "fpga_out_ttl_o[3]" IOSTANDARD = "LVCMOS33";
#NET "fpga_out_ttl_o[4]" LOC = H4;
#NET "fpga_out_ttl_o[4]" IOSTANDARD = "LVCMOS33";
#NET "fpga_out_ttl_o[5]" LOC = J4;
#NET "fpga_out_ttl_o[5]" IOSTANDARD = "LVCMOS33";
#NET "fpga_out_ttl_o[6]" LOC = H2;
#NET "fpga_out_ttl_o[6]" IOSTANDARD = "LVCMOS33";
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
##-------------------
##-- Inverted TTL I/O
......@@ -147,22 +153,26 @@ NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
##-- Schematics name: INV_IN_*
##---- renamed to INV_IN[*]
##-------------------
#NET "inv_in_n_i[1]" LOC = V2;
#NET "inv_in_n_i[1]" IOSTANDARD = "LVCMOS33";
#NET "inv_in_n_i[2]" LOC = W3;
#NET "inv_in_n_i[2]" IOSTANDARD = "LVCMOS33";
#NET "inv_in_n_i[3]" LOC = Y2;
#NET "inv_in_n_i[3]" IOSTANDARD = "LVCMOS33";
#NET "inv_in_n_i[4]" LOC = AA2;
#NET "inv_in_n_i[4]" IOSTANDARD = "LVCMOS33";
#NET "inv_out_o[1]" LOC = J3;
#NET "inv_out_o[1]" IOSTANDARD = "LVCMOS33";
#NET "inv_out_o[2]" LOC = L3;
#NET "inv_out_o[2]" IOSTANDARD = "LVCMOS33";
#NET "inv_out_o[3]" LOC = M3;
#NET "inv_out_o[3]" IOSTANDARD = "LVCMOS33";
#NET "inv_out_o[4]" LOC = P2;
#NET "inv_out_o[4]" IOSTANDARD = "LVCMOS33";
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##======================================
......@@ -206,23 +216,23 @@ NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
###-- I2C lines
###-------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = "LVCMOS33";
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = "LVCMOS33";
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = "LVCMOS33";
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = "LVCMOS33";
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = "LVCMOS33";
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = "LVCMOS33";
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
......@@ -230,17 +240,17 @@ NET "sda_oe_o" DRIVE = 4;
###-- Geographical Address
###-------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = "LVCMOS33";
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = "LVCMOS33";
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
###-------------------
###-- ROM memory
###-------------------
......@@ -260,26 +270,26 @@ NET "fpga_gap_i" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Thermo for UID
##-------------------
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = "LVCMOS33";
NET "thermometer_b" LOC = B1;
NET "thermometer_b" IOSTANDARD = LVCMOS33;
##-------------------
##-- DACs control
##--
##-- + CMOS 3.3V input
##-------------------
NET "fpga_plldac1_din_o" LOC = AB14;
NET "fpga_plldac1_din_o" IOSTANDARD = "LVCMOS33";
NET "fpga_plldac1_sclk_o" LOC = AA14;
NET "fpga_plldac1_sclk_o" IOSTANDARD = "LVCMOS33";
NET "fpga_plldac1_sync_n_o" LOC = AB15;
NET "fpga_plldac1_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "fpga_plldac1_din_o" LOC = AB14;
NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sclk_o" LOC = AA14;
NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac1_sync_n_o" LOC = AB15;
NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_din_o" LOC = W14;
NET "fpga_plldac2_din_o" IOSTANDARD = "LVCMOS33";
NET "fpga_plldac2_sclk_o" LOC = Y14;
NET "fpga_plldac2_sclk_o" IOSTANDARD = "LVCMOS33";
NET "fpga_plldac2_sync_n_o" LOC = W13;
NET "fpga_plldac2_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "fpga_plldac2_din_o" LOC = W14;
NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sclk_o" LOC = Y14;
NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_plldac2_sync_n_o" LOC = W13;
NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
####-------------------
####-- SFP connection
####-------------------
......@@ -289,49 +299,44 @@ NET "fpga_plldac2_sync_n_o" IOSTANDARD = "LVCMOS33";
## NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_rate_select_o" LOC = C4;
## NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
##NET "fpga_sfp_tx_disable_o" LOC = E4;
## NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_tx_fault_i" LOC = D2;
## NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
####-------------------
####-- FPGA MGT lines
####-------------------
##NET "fpgamgtclk0_p_i" LOC = A10;
## NET "fpgamgtclk0_p_i" IOSTANDARD = "LVDS_12";
##NET "fpgamgtclk0_n_i" LOC = B10;
## NET "fpgamgtclk0_n_i" IOSTANDARD = "LVDS_12";
##NET "mgtsfprx0_p_i" LOC = D7;
## NET "mgtsfprx0_p_i" IOSTANDARD = "LVDS_12";
##NET "mgtsfprx0_n_i" LOC = C7;
## NET "mgtsfprx0_n_i" IOSTANDARD = "LVDS_12";
##NET "mgtsfptx0_p_o" LOC = B6;
## NET "mgtsfptx0_p_o" IOSTANDARD = "LVDS_12";
##NET "mgtsfptx0_n_o" LOC = A6;
## NET "mgtsfptx0_n_o" IOSTANDARD = "LVDS_12";
#
#
##-------------------
##-- FPGA MGT lines
##-------------------
NET "fpga_mgt_clk0_p_i" LOC = A10;
NET "fpga_mgt_clk0_n_i" LOC = B10;
NET "mgt_sfp_rx0_p_i" LOC = D7;
NET "mgt_sfp_rx0_n_i" LOC = C7;
NET "mgt_sfp_tx0_p_o" LOC = B6;
NET "mgt_sfp_tx0_n_o" LOC = A6;
###======================================
###-- ADDITIONAL PINS
###======================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = "LVCMOS33";
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;
NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;
NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = "LVCMOS33";
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
###-------------------
......@@ -355,22 +360,22 @@ NET "fpga_inv_oe_o" SLEW = QUIETIO;
## NET "extra_switch_n_i[7]" LOC = K22;
## NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = "LVCMOS33";
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-------------------
##-- Motherboard and piggyback IDs
##-------------------
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
####-------------------
####-- General purpose
####-------------------
......
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @ 00387791
......@@ -35,7 +35,11 @@ use IEEE.NUMERIC_STD.ALL;
use UNISIM.VCOMPONENTS.ALL;
use work.bicolor_led_ctrl_pkg.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
entity conv_ttl_blo_v2 is
generic
......@@ -65,12 +69,12 @@ entity conv_ttl_blo_v2 is
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
-- fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
-- fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
-- fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
-- fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
-- inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
-- inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
......@@ -107,6 +111,14 @@ entity conv_ttl_blo_v2 is
fpga_sfp_mod_def1_b : inout std_logic;
fpga_sfp_mod_def2_b : inout std_logic;
-- SFP MGT lines
fpga_mgt_clk0_p_i : in std_logic;
fpga_mgt_clk0_n_i : in std_logic;
mgt_sfp_rx0_p_i : in std_logic;
mgt_sfp_rx0_n_i : in std_logic;
mgt_sfp_tx0_p_o : out std_logic;
mgt_sfp_tx0_n_o : out std_logic;
-- TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
......@@ -135,16 +147,21 @@ architecture behav of conv_ttl_blo_v2 is
type t_pts_state is
(
ST_IDLE,
ST_TTLTEST,
ST_PLLTEST,
ST_LEDTEST_1,
ST_LEDTEST_2
);
type t_ttl_pulse_counter is array (10 downto 1)
of unsigned(31 downto 0);
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : NATURAL := 1;
constant c_nr_slaves : NATURAL := 7;
constant c_nr_masters : NATURAL := 1;
constant c_nr_slaves : NATURAL := 11;
-----------------------------------------
-- Memory map
......@@ -160,31 +177,43 @@ architecture behav of conv_ttl_blo_v2 is
-- SFP_I2C [0180-0200]
-----------------------------------------
-- slave order definitions
constant c_slv_pts_regs : natural := 0;
constant c_slv_onewire_mst : natural := 1;
constant c_slv_dac_spi_125 : natural := 2;
constant c_slv_clk_info_125 : natural := 3;
constant c_slv_dac_spi_20 : natural := 4;
constant c_slv_clk_info_20 : natural := 5;
constant c_slv_sfp_i2c : natural := 6;
constant c_slv_pts_regs : natural := 0;
constant c_slv_onewire_mst : natural := 1;
constant c_slv_dac_spi_125 : natural := 2;
constant c_slv_dac_spi_20 : natural := 3;
constant c_slv_clk_info_125 : natural := 4;
constant c_slv_clk_info_20 : natural := 5;
constant c_slv_sfp_i2c : natural := 6;
constant c_slv_minic : natural := 7;
constant c_slv_endpoint : natural := 8;
constant c_slv_dpram : natural := 9;
constant c_slv_pulse_cntrs : natural := 10;
-- base address definitions
constant c_addr_pts_regs : t_wishbone_address := x"00000000";
constant c_addr_onewire_mst : t_wishbone_address := x"00000010";
constant c_addr_dac_spi_125 : t_wishbone_address := x"00000020";
constant c_addr_clk_info_125 : t_wishbone_address := x"00000080";
constant c_addr_dac_spi_20 : t_wishbone_address := x"00000100";
constant c_addr_clk_info_20 : t_wishbone_address := x"00000160";
constant c_addr_sfp_i2c : t_wishbone_address := x"00000180";
constant c_addr_dac_spi_20 : t_wishbone_address := x"00000080";
constant c_addr_clk_info_125 : t_wishbone_address := x"00000100";
constant c_addr_clk_info_20 : t_wishbone_address := x"00000120";
constant c_addr_sfp_i2c : t_wishbone_address := x"00000140";
constant c_addr_endpoint : t_wishbone_address := x"00000200";
constant c_addr_minic : t_wishbone_address := x"00000400";
constant c_addr_dpram : t_wishbone_address := x"00000800";
constant c_addr_pulse_cntrs : t_wishbone_address := x"00000C00";
-- address mask definitions
constant c_mask_pts_regs : t_wishbone_address := x"FFFFFFF0";
constant c_mask_onewire_mst : t_wishbone_address := x"FFFFFFF0";
constant c_mask_dac_spi_125 : t_wishbone_address := x"FFFFFFE0";
constant c_mask_clk_info_125 : t_wishbone_address := x"FFFFFFC0";
constant c_mask_dac_spi_20 : t_wishbone_address := x"FFFFFFE0";
constant c_mask_clk_info_20 : t_wishbone_address := x"FFFFFFE0";
constant c_mask_sfp_i2c : t_wishbone_address := x"FFFFFFE0";
constant c_mask_pts_regs : t_wishbone_address := x"00000FF0";
constant c_mask_onewire_mst : t_wishbone_address := x"00000FF0";
constant c_mask_dac_spi_125 : t_wishbone_address := x"00000FE0";
constant c_mask_dac_spi_20 : t_wishbone_address := x"00000FE0";
constant c_mask_clk_info_125 : t_wishbone_address := x"00000F60";
constant c_mask_clk_info_20 : t_wishbone_address := x"00000F60";
constant c_mask_sfp_i2c : t_wishbone_address := x"00000F60";
constant c_mask_endpoint : t_wishbone_address := x"00000E00";
constant c_mask_minic : t_wishbone_address := x"00000C00";
constant c_mask_dpram : t_wishbone_address := x"00000C00";
constant c_mask_pulse_cntrs : t_wishbone_address := x"00000C00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
......@@ -195,7 +224,11 @@ architecture behav of conv_ttl_blo_v2 is
c_slv_clk_info_125 => c_addr_clk_info_125,
c_slv_dac_spi_20 => c_addr_dac_spi_20,
c_slv_clk_info_20 => c_addr_clk_info_20,
c_slv_sfp_i2c => c_addr_sfp_i2c
c_slv_sfp_i2c => c_addr_sfp_i2c,
c_slv_endpoint => c_addr_endpoint,
c_slv_minic => c_addr_minic,
c_slv_dpram => c_addr_dpram,
c_slv_pulse_cntrs => c_addr_pulse_cntrs
);
-- masks constant for Wishbone crossbar
......@@ -207,9 +240,16 @@ architecture behav of conv_ttl_blo_v2 is
c_slv_clk_info_125 => c_mask_clk_info_125,
c_slv_dac_spi_20 => c_mask_dac_spi_20,
c_slv_clk_info_20 => c_mask_clk_info_20,
c_slv_sfp_i2c => c_mask_sfp_i2c
c_slv_sfp_i2c => c_mask_sfp_i2c,
c_slv_endpoint => c_mask_endpoint,
c_slv_minic => c_mask_minic,
c_slv_dpram => c_mask_dpram,
c_slv_pulse_cntrs => c_mask_pulse_cntrs
);
-- MiniNIC log2 of memory size
constant c_minic_memsize_log2 : natural := 10;
--============================================================================
-- Component declarations
--============================================================================
......@@ -299,6 +339,87 @@ architecture behav of conv_ttl_blo_v2 is
);
end component pts_regs;
-- Pulse generator component
-- (use: TTL and BLO pulse tests)
component pulse_generator is
generic
(
-- Pulse width, in number of clk_i cycles
g_pulse_width : natural := 15;
-- Glitch filter length:
-- g_glitch_filt_len=1 => trigger width should be > 1 clk_i cycle
-- g_glitch_filt_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse type input
-- '1' - TYPE 1 (glitch-sensitive, without output jitter)
-- '0' - TYPE 2 (glitch-insensitive, with output jitter)
pulse_type_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
enable_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- TYPE 1 pulse: none
-- TYPE 2 pulse: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
);
end component pulse_generator;
-- Pulse counter Wishbone regs component
-- use: TTL, BLO tests
component pulse_cnt_wb is
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch7o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch7i_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch8o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch8i_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch9o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch9i_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch10o_val_i : in std_logic_vector(31 downto 0);
pulse_cnt_ch10i_val_i : in std_logic_vector(31 downto 0)
);
end component pulse_cnt_wb;
-- Incremental counter component
-- use: DAC, PLL & VCXO test
component incr_counter is
generic
(
......@@ -323,6 +444,8 @@ architecture behav of conv_ttl_blo_v2 is
); -- counter reahed counter_top_i value
end component incr_counter;
-- Clock info component
-- use: DAC, PLL & VCXO test
component clk_info_wb_slave is
port
(
......@@ -346,28 +469,92 @@ architecture behav of conv_ttl_blo_v2 is
);
end component clk_info_wb_slave;
-- Mini NIC component
-- use: MGTX and SFP test
component xwr_mini_nic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_memsize_log2 : integer;
g_buffer_little_endian : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
snk_i : in t_wrf_sink_in;
txtsu_port_id_i : in std_logic_vector(4 downto 0);
txtsu_frame_id_i : in std_logic_vector(16 - 1 downto 0);
txtsu_tsval_i : in std_logic_vector(28 + 4 - 1 downto 0);
txtsu_tsincorrect_i : in std_logic;
txtsu_stb_i : in std_logic;
txtsu_ack_o : out std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
-- GTP component for Spartan-6 FPGA
-- use: MGTX and SFP test
component wr_gtp_phy_spartan6
generic (
g_simulation : integer;
g_force_disparity : integer;
g_enable_ch0 : integer;
g_enable_ch1 : integer);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic := '0';
ch0_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch0_tx_k_i : in std_logic := '0';
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch1_ref_clk_i : in std_logic := '0';
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk125 : std_logic;
-- Reset signals
-- Global reset signals
signal rst_n, rst : std_logic;
signal rst_fr_reg : std_logic;
-- RTM detection signals
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Signals for pulse generation triggers
signal trig : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_inv : std_logic_vector(g_nr_inv_chan downto 1);
signal trig_ttl, trig_blo : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for blocking and TTL pulse outputs
signal pulse_outputs : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for inverted-TTL pulse outputs
signal inv_outputs : std_logic_vector(g_nr_inv_chan downto 1);
......@@ -399,16 +586,34 @@ architecture behav of conv_ttl_blo_v2 is
signal front_led_ledtest : std_logic_vector(g_nr_ttl_chan downto 1);
signal front_led_plltest : std_logic_vector(g_nr_ttl_chan downto 1);
-- PTS register signals
signal pts_state : t_pts_state;
signal pts_crrt_test : std_logic_vector(3 downto 0);
signal cnt_halfsec : unsigned(25 downto 0);
signal rst_fr_reg : std_logic;
-- TTL test signals
signal first_pulse : std_logic;
signal first_pulse_d0 : std_logic;
signal first_pulse_en : std_logic;
signal ttl_trigs : std_logic_vector(10 downto 1);
signal ttl_trigs_d0 : std_logic_vector(10 downto 1);
signal ttl_trigs_d1 : std_logic_vector(10 downto 1);
signal ttl_trigs_d2 : std_logic_vector(10 downto 1);
signal ttl_pulses : std_logic_vector(10 downto 1);
signal ttl_pulses_d0 : std_logic_vector(10 downto 1);
signal ttl_pulses_d1 : std_logic_vector(10 downto 1);
signal ttl_pulses_d2 : std_logic_vector(10 downto 1);
signal cnt_ttl_in : t_ttl_pulse_counter;
signal cnt_ttl_out : t_ttl_pulse_counter;
-- one-wire master signals
signal owr_pwren : std_logic_vector(0 downto 0);
signal owr_en : std_logic_vector(0 downto 0);
signal owr_in : std_logic_vector(0 downto 0);
-- PTS FSM signals
signal pts_state : t_pts_state;
signal pts_crrt_test : std_logic_vector(3 downto 0);
signal cnt_halfsec : unsigned(25 downto 0);
-- PLL & DAC test signals
signal cnt125 : std_logic_vector(31 downto 0);
signal cnt125_top : std_logic_vector(31 downto 0);
......@@ -436,12 +641,38 @@ architecture behav of conv_ttl_blo_v2 is
signal i2c_sda_to_sfp : std_logic;
signal i2c_sfp_sda_en : std_logic;
-- SFP signals
signal clk_gtp : std_logic;
signal minic_mem_data_out : std_logic_vector(31 downto 0);
signal minic_mem_addr_out : std_logic_vector(c_minic_memsize_log2-1 downto 0);
signal minic_mem_data_in : std_logic_vector(31 downto 0);
signal minic_mem_wr : std_logic;
signal minic_src_out : t_wrf_source_out;
signal minic_src_in : t_wrf_source_in;
signal minic_snk_out : t_wrf_sink_out;
signal minic_snk_in : t_wrf_sink_in;
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_tx_d : std_logic_vector(15 downto 0);
signal phy_tx_k : std_logic_vector( 1 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_error : std_logic;
signal phy_rx_d : std_logic_vector(15 downto 0);
signal phy_rx_clk : std_logic;
signal phy_rx_k : std_logic_vector( 1 downto 0);
signal phy_rx_error : std_logic;
signal phy_rx_bitslide : std_logic_vector( 4 downto 0);
signal dpram_we : std_logic;
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf: IBUFGDS
cmp_125_diff_buf: IBUFDS
generic map
(
DIFF_TERM => TRUE,
......@@ -527,7 +758,7 @@ begin
end process p_i2c_up;
--============================================================================
-- Instantiation and connection the main Wishbone crossbar
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
......@@ -584,7 +815,8 @@ begin
-- The test number is a four-bit fractional with one bit fractional part. It
-- is set via the first four bits of the PTS control register and is used
-- to set the state of the FSM.
pts_state <= ST_PLLTEST when (pts_crrt_test = "1000") else
pts_state <= ST_TTLTEST when (pts_crrt_test = "0100") else
ST_PLLTEST when (pts_crrt_test = "1000") else
ST_LEDTEST_1 when (pts_crrt_test = "1110") else
ST_LEDTEST_2 when (pts_crrt_test = "1111") else
ST_IDLE;
......@@ -599,20 +831,23 @@ begin
if rising_edge(clk125) then
if (rst_n = '0') then
-- pts_state <= ST_IDLE;
cnt_halfsec <= (others => '0');
led_seq <= (others => '0');
cnt_halfsec <= (others => '0');
led_seq <= (others => '0');
first_pulse_en <= '0';
else
case pts_state is
when ST_PLLTEST =>
cnt_halfsec <= cnt_halfsec + 1;
if (cnt_halfsec = 62499999) then
cnt_halfsec <= (others => '0');
led_seq <= led_seq + 1;
if (led_seq = 7) then
led_seq <= (others => '0');
end if;
end if;
when ST_TTLTEST =>
first_pulse_en <= '1';
-- when ST_PLLTEST =>
-- cnt_halfsec <= cnt_halfsec + 1;
-- if (cnt_halfsec = 62499999) then
-- cnt_halfsec <= (others => '0');
-- led_seq <= led_seq + 1;
-- if (led_seq = 7) then
-- led_seq <= (others => '0');
-- end if;
-- end if;
when ST_LEDTEST_1 =>
cnt_halfsec <= cnt_halfsec + 1;
......@@ -642,6 +877,210 @@ begin
end if;
end process p_fsm;
--============================================================================
-- Thermometer test logic
--============================================================================
-- The one-wire master component is used to control the on-board DS18B20
-- thermometer
cmp_onewire_master: wb_onewire_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map
(
clk_sys_i => clk125,
rst_n_i => rst_n,
wb_cyc_i => xbar_master_out(c_slv_onewire_mst).cyc,
wb_sel_i => xbar_master_out(c_slv_onewire_mst).sel,
wb_stb_i => xbar_master_out(c_slv_onewire_mst).stb,
wb_we_i => xbar_master_out(c_slv_onewire_mst).we,
wb_adr_i => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
wb_dat_i => xbar_master_out(c_slv_onewire_mst).dat,
wb_dat_o => xbar_master_in(c_slv_onewire_mst).dat,
wb_ack_o => xbar_master_in(c_slv_onewire_mst).ack,
wb_int_o => open,
wb_stall_o => xbar_master_in(c_slv_onewire_mst).stall,
owr_pwren_o => owr_pwren,
owr_en_o => owr_en,
owr_i => owr_in
);
-- Generate tri-state buffer for thermometer
thermometer_b <= '0' when (owr_en(0) = '1') else
'Z';
owr_in(0) <= thermometer_b;
--============================================================================
-- TTL pulse test logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe: process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '1';
if (oe = '1') then
blo_oe <= '0';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
-- Assign registers to outputs
fpga_oe_o <= oe;
fpga_blo_oe_o <= blo_oe;
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
-- Logic to generate the first "pulse" on CH1; the pulse is actually
-- a continuously high signal which is cut by the pulse generator at the
-- output
p_first_pulse: process(clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
first_pulse <= '0';
first_pulse_d0 <= '0';
elsif (first_pulse_en = '1') then
first_pulse <= '1';
first_pulse_d0 <= first_pulse;
end if;
end if;
end process p_first_pulse;
-- The input to the first channel is multiplexed between the first pulse
-- and the input; the selecting input to the mux is the delayed version
-- of the first pulse, after the first pulse is generated, the mux switches
-- to the channel input.
-- ttl_trigs(1) <= first_pulse when (first_pulse_d0 = '0') else
-- not fpga_input_ttl_n_i(1);
-- Assign the rest of the inputs
ttl_trigs(6 downto 1) <= not fpga_input_ttl_n_i;
ttl_trigs(10 downto 7) <= not inv_in_n_i;
-- Now, generate ten pulse generator blocks connected to the TTL outputs
-- and with the TTL inputs as triggers. External to the FPGA, the inputs of
-- CH2 are expected to be connected to CH1, CH3 to CH2 and so on, until
-- the last INV_TTL output, which is expected to be connected back to the
-- input of CH1.
--
-- Type 1 pulses (non-glich-filtered) with 1us width will be generated by
-- the generator blocks.
gen_ttl_pulse_gens: for i in 1 to 10 generate
cmp_ttl_pulse_gen: pulse_generator
generic map
(
g_pulse_width => 125,
g_glitch_filt_len => 4
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
pulse_type_i => '1',
enable_i => '1',
trig_i => ttl_trigs(i),
pulse_o => ttl_pulses(i)
);
end generate gen_ttl_pulse_gens;
-- Assign the outputs of the pulse_generator components to the TTL and INV-TTL
-- outputs
fpga_out_ttl_o <= ttl_pulses( 6 downto 1);
inv_out_o <= ttl_pulses(10 downto 7);
-- Generate input and output pulse counters
--gen_ttl_pulse_cntrs: for i in 1 to 10 generate
p_cnt_ttl_pulses: process(clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
cnt_ttl_in <= (others => (others => '0'));
cnt_ttl_out <= (others => (others => '0'));
ttl_trigs_d0 <= (others => '0');
ttl_trigs_d1 <= (others => '0');
ttl_trigs_d2 <= (others => '0');
ttl_pulses_d0 <= (others => '0');
ttl_pulses_d1 <= (others => '0');
ttl_pulses_d2 <= (others => '0');
else
-- Resync each channel input and output pulse and increment the
-- corresponding counter on rising edge of the pulse signal
for i in 1 to 10 loop
ttl_trigs_d0(i) <= ttl_trigs(i);
ttl_trigs_d1(i) <= ttl_trigs_d0(i);
ttl_trigs_d2(i) <= ttl_trigs_d1(i);
if (ttl_trigs_d1(i) = '1') and (ttl_trigs_d2(i) = '0') then
cnt_ttl_in(i) <= cnt_ttl_in(i) + 1;
end if;
ttl_pulses_d0(i) <= ttl_pulses(i);
ttl_pulses_d1(i) <= ttl_pulses_d0(i);
ttl_pulses_d2(i) <= ttl_pulses_d1(i);
if (ttl_pulses_d1(i) = '1') and (ttl_pulses_d2(i) = '0') then
cnt_ttl_out(i) <= cnt_ttl_out(i) + 1;
end if;
end loop;
end if;
end if;
end process p_cnt_ttl_pulses;
--end generate gen_ttl_pulse_cntrs;
-- Finally, connect a Wishbone slave component containing the regs for the
-- pulse counters
cmp_pulse_cnt_wb: pulse_cnt_wb
port map
(
rst_n_i => rst_n,
clk_sys_i => clk125,
wb_adr_i => xbar_master_out(c_slv_pulse_cntrs).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_pulse_cntrs).dat,
wb_dat_o => xbar_master_in(c_slv_pulse_cntrs).dat,
wb_cyc_i => xbar_master_out(c_slv_pulse_cntrs).cyc,
wb_sel_i => xbar_master_out(c_slv_pulse_cntrs).sel,
wb_stb_i => xbar_master_out(c_slv_pulse_cntrs).stb,
wb_we_i => xbar_master_out(c_slv_pulse_cntrs).we,
wb_ack_o => xbar_master_in(c_slv_pulse_cntrs).ack,
wb_stall_o => xbar_master_in(c_slv_pulse_cntrs).stall,
pulse_cnt_ch1o_val_i => std_logic_vector(cnt_ttl_out( 1)),
pulse_cnt_ch1i_val_i => std_logic_vector(cnt_ttl_in ( 1)),
pulse_cnt_ch2o_val_i => std_logic_vector(cnt_ttl_out( 2)),
pulse_cnt_ch2i_val_i => std_logic_vector(cnt_ttl_in ( 2)),
pulse_cnt_ch3o_val_i => std_logic_vector(cnt_ttl_out( 3)),
pulse_cnt_ch3i_val_i => std_logic_vector(cnt_ttl_in ( 3)),
pulse_cnt_ch4o_val_i => std_logic_vector(cnt_ttl_out( 4)),
pulse_cnt_ch4i_val_i => std_logic_vector(cnt_ttl_in ( 4)),
pulse_cnt_ch5o_val_i => std_logic_vector(cnt_ttl_out( 5)),
pulse_cnt_ch5i_val_i => std_logic_vector(cnt_ttl_in ( 5)),
pulse_cnt_ch6o_val_i => std_logic_vector(cnt_ttl_out( 6)),
pulse_cnt_ch6i_val_i => std_logic_vector(cnt_ttl_in ( 6)),
pulse_cnt_ch7o_val_i => std_logic_vector(cnt_ttl_out( 7)),
pulse_cnt_ch7i_val_i => std_logic_vector(cnt_ttl_in ( 7)),
pulse_cnt_ch8o_val_i => std_logic_vector(cnt_ttl_out( 8)),
pulse_cnt_ch8i_val_i => std_logic_vector(cnt_ttl_in ( 8)),
pulse_cnt_ch9o_val_i => std_logic_vector(cnt_ttl_out( 9)),
pulse_cnt_ch9i_val_i => std_logic_vector(cnt_ttl_in ( 9)),
pulse_cnt_ch10o_val_i => std_logic_vector(cnt_ttl_out(10)),
pulse_cnt_ch10i_val_i => std_logic_vector(cnt_ttl_in (10))
);
--============================================================================
-- PLL test logic
-- * test OSC3 -- 20MHz VCXO
......@@ -825,8 +1264,7 @@ begin
--============================================================================
-- SFP EEPROM test logic
-- * test bicolor LEDs and its driving circuit (IC1)
-- * test front panel LED logic and driving circuit (IC5)
-- * test J1 SFP connector using an SFP loopback module
--============================================================================
-- First, instantiate an I2C master to handle SFP communication
cmp_sfp_eeprom_i2c: wb_i2c_master
......@@ -862,6 +1300,164 @@ begin
fpga_sfp_mod_def2_b <= i2c_sda_to_sfp when (i2c_sfp_sda_en = '0') else 'Z';
i2c_sda_fr_sfp <= fpga_sfp_mod_def2_b;
--============================================================================
-- SFP EEPROM test logic
-- * test J1 SFP connector using an SFP loopback module
--============================================================================
-- First, instantiate an IBUFGDS for MGT clock
cmp_mgt_clk_ibufds: IBUFDS
generic map
(
DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "DEFAULT"
)
port map
(
I => fpga_mgt_clk0_p_i,
IB => fpga_mgt_clk0_n_i,
O => clk_gtp
);
-- Connect the MINIC module to the crossbar
cmp_sfp_minic: xwr_mini_nic
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_memsize_log2 => c_minic_memsize_log2,
g_buffer_little_endian => true
)
port map
(
clk_sys_i => clk125,
rst_n_i => rst_n,
mem_data_o => minic_mem_data_out,
mem_addr_o => minic_mem_addr_out,
mem_data_i => minic_mem_data_in,
mem_wr_o => minic_mem_wr,
src_o => minic_src_out,
src_i => minic_src_in,
snk_o => minic_snk_out,
snk_i => minic_snk_in,
txtsu_port_id_i => "00000",
txtsu_frame_id_i => x"0000",
txtsu_tsval_i => x"00000000",
txtsu_tsincorrect_i => '0',
txtsu_stb_i => '0',
wb_i => xbar_master_out(c_slv_minic),
wb_o => xbar_master_in(c_slv_minic)
);
-- Connect the endpoint buffer RAM
cmp_sfp_dpram: generic_dpram
generic map
(
g_data_width => 32,
g_size => 2**c_minic_memsize_log2,
g_with_byte_enable => false,
g_dual_clock => false
)
port map
(
rst_n_i => rst_n,
clka_i => clk125,
bwea_i => "0000",
wea_i => dpram_we,
aa_i => xbar_master_out(c_slv_dpram).adr(c_minic_memsize_log2+1 downto 2),
da_i => xbar_master_out(c_slv_dpram).dat,
qa_o => xbar_master_in(c_slv_dpram).dat,
clkb_i => clk125,
bweb_i => "0000",
web_i => minic_mem_wr,
ab_i => minic_mem_addr_out,
db_i => minic_mem_data_out,
qb_o => minic_mem_data_in
);
-- associate WE to first port of the RAM to WB signals
dpram_we <= xbar_master_out(c_slv_dpram).cyc and xbar_master_out(c_slv_dpram).stb and
xbar_master_out(c_slv_dpram).we;
-- Connect the Endpoint module to the crossbar
cmp_sfp_endpoint: xwr_endpoint
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_simulation => false,
g_tx_force_gap_length => 0,
g_pcs_16bit => false,
g_rx_buffer_size => 1024,
g_with_rx_buffer => true,
g_with_flow_control => false,
g_with_timestamper => true,
g_with_dpi_classifier => false,
g_with_vlans => false,
g_with_rtu => false,
g_with_leds => false,
g_with_dmtd => false
)
port map
(
clk_ref_i => clk125,
clk_sys_i => clk125,
clk_dmtd_i => clk125,
rst_n_i => rst_n,
pps_csync_p1_i => '0',
pps_valid_i => '0',
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_ref_clk_i => clk125,
phy_tx_data_o => phy_tx_d,
phy_tx_k_o => phy_tx_k,
phy_tx_disparity_i => phy_tx_disparity,
phy_tx_enc_err_i => phy_tx_error,
phy_rx_data_i => phy_rx_d,
phy_rx_clk_i => phy_rx_clk,
phy_rx_k_i => phy_rx_k,
phy_rx_enc_err_i => phy_rx_error,
phy_rx_bitslide_i => phy_rx_bitslide,
src_o => minic_snk_in,
src_i => minic_snk_out,
snk_o => minic_src_in,
snk_i => minic_src_out,
wb_i => xbar_master_out(c_slv_endpoint),
wb_o => xbar_master_in(c_slv_endpoint)
);
-- Finally, connect the GTP transceiver to the endpoint signals
cmp_gtp_xceiver: wr_gtp_phy_spartan6
generic map
(
g_simulation => 0,
g_force_disparity => 1,
g_enable_ch0 => 1,
g_enable_ch1 => 0
)
port map
(
gtp_clk_i => clk_gtp,
ch0_ref_clk_i => clk125,
ch0_tx_data_i => phy_tx_d(7 downto 0),
ch0_tx_k_i => phy_tx_k(0),
ch0_tx_disparity_o => phy_tx_disparity,
ch0_tx_enc_err_o => phy_tx_error,
ch0_rx_rbclk_o => phy_rx_clk,
ch0_rx_data_o => phy_rx_d(7 downto 0),
ch0_rx_k_o => phy_rx_k(0),
ch0_rx_enc_err_o => phy_rx_error,
ch0_rx_bitslide_o => phy_rx_bitslide(3 downto 0),
ch0_rst_i => phy_rst,
ch0_loopen_i => phy_loopen,
pad_txn0_o => mgt_sfp_tx0_n_o,
pad_txp0_o => mgt_sfp_tx0_p_o,
pad_rxn0_i => mgt_sfp_rx0_n_i,
pad_rxp0_i => mgt_sfp_rx0_p_i
);
--============================================================================
-- LED test logic
-- * test bicolor LEDs and its driving circuit (IC1)
......@@ -973,7 +1569,7 @@ begin
(
clk_i => clk125,
rst_n_i => rst_n,
led_intensity_i => "0011111",
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
......@@ -986,75 +1582,6 @@ begin
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
--============================================================================
-- Thermometer test
--============================================================================
-- The one-wire master component is used to control the on-board DS18B20
-- thermometer
cmp_onewire_master: wb_onewire_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map
(
clk_sys_i => clk125,
rst_n_i => rst_n,
wb_cyc_i => xbar_master_out(c_slv_onewire_mst).cyc,
wb_sel_i => xbar_master_out(c_slv_onewire_mst).sel,
wb_stb_i => xbar_master_out(c_slv_onewire_mst).stb,
wb_we_i => xbar_master_out(c_slv_onewire_mst).we,
wb_adr_i => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
wb_dat_i => xbar_master_out(c_slv_onewire_mst).dat,
wb_dat_o => xbar_master_in(c_slv_onewire_mst).dat,
wb_ack_o => xbar_master_in(c_slv_onewire_mst).ack,
wb_int_o => open,
wb_stall_o => xbar_master_in(c_slv_onewire_mst).stall,
owr_pwren_o => owr_pwren,
owr_en_o => owr_en,
owr_i => owr_in
);
-- Generate tri-state buffer for thermometer
thermometer_b <= '0' when (owr_en(0) = '1') else
'Z';
owr_in(0) <= thermometer_b;
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe: process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '0';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
fpga_oe_o <= oe;
fpga_blo_oe_o <= blo_oe;
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
--============================================================================
-- RTM detection logic
......
hdl/pulse_generator/rtl/pulse_generator.vhd
View file @ 00387791
......@@ -79,6 +79,9 @@ entity pulse_generator is
-- '0' - TYPE 2 (glitch-insensitive, with output jitter)
pulse_type_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
enable_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
......@@ -180,7 +183,9 @@ begin
if (pulse_rst = '1') then
pulse_type1 <= '0';
elsif rising_edge(trig_i) then
pulse_type1 <= '1';
if (enable_i = '1') then
pulse_type1 <= '1';
end if;
end if;
end process p_pulse_type1;
......@@ -192,7 +197,7 @@ begin
pulse_type1_d0 <= '0';
pulse_type1_d1 <= '0';
pulse_type1_d2 <= '0';
else
elsif (enable_i = '1') then
pulse_type1_d0 <= pulse_type1;
pulse_type1_d1 <= pulse_type1_d0;
pulse_type1_d2 <= pulse_type1_d1;
......@@ -206,10 +211,11 @@ begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_type2 <= '0';
elsif (state = ST_PULSE_TYPE2) then
pulse_type2 <= '1';
else
elsif (enable_i = '1') then
pulse_type2 <= '0';
if (state = ST_PULSE_TYPE2) then
pulse_type2 <= '1';
end if;
end if;
end if;
end process p_pulse_type2;
......@@ -241,7 +247,7 @@ begin
pulse_rst <= '1';
width_cnt <= (others => '0');
trig_degl_d0 <= '0';
else
elsif (enable_i = '1') then
-- Deglitched trigger delay
trig_degl_d0 <= trig_degl;
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 00387791
......@@ -78,39 +78,38 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1363103684">
<transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366299832">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1363103684">
<transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1363103684">
<transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1363103684">
<transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1363103684">
<transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1363103684">
<transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1363103684">
<transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363164504" xil_pn:in_ck="-88236163103343582" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363164492">
<transform xil_pn:end_ts="1366299846" xil_pn:in_ck="-88236163103343582" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
......@@ -125,26 +124,22 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1363104090" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1363104090">
<transform xil_pn:end_ts="1366299846" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366299846">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1363164509" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363164504">
<transform xil_pn:end_ts="1366299856" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366299846">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bld"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363164539" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363164509">
<transform xil_pn:end_ts="1366299892" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366299856">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_v2_map.map"/>
......@@ -155,11 +150,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1363164570" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363164539">
<transform xil_pn:end_ts="1366299928" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366299892">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ncd"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pad"/>
......@@ -171,11 +164,10 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1363164588" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363164570">
<transform xil_pn:end_ts="1366299949" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366299928">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bgn"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bit"/>
......@@ -187,18 +179,18 @@
<transform xil_pn:end_ts="1363164589" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363164588">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impact.cmd"/>
<outfile xil_pn:name="_impact.log"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1363164570" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363164561">
<transform xil_pn:end_ts="1366299928" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366299917">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twr"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twx"/>
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 00387791
......@@ -127,6 +127,7 @@ architecture behav of conv_ttl_blo_v2 is
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
......@@ -156,6 +157,9 @@ architecture behav of conv_ttl_blo_v2 is
-- '0' - TYPE 2 (glitch-insensitive, with output jitter)
pulse_type_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
enable_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
......@@ -268,6 +272,7 @@ begin
port map
(
clk_i => clk_125,
rst_i => '0',
rst_n_o => rst_n
);
......@@ -324,6 +329,7 @@ begin
clk_i => clk_125,
rst_n_i => rst_n,
pulse_type_i => EXTRA_SWITCH(1),
enable_i => '1',
trig_i => trig(i),
pulse_o => pulse_outputs(i)
);
......@@ -339,6 +345,7 @@ begin
(
clk_i => clk_125,
rst_n_i => rst_n,
enable_i => '1',
pulse_type_i => EXTRA_SWITCH(1),
trig_i => trig(i),
pulse_o => pulse_leds(i)
......@@ -375,6 +382,7 @@ begin
clk_i => clk_125,
rst_n_i => rst_n,
pulse_type_i => EXTRA_SWITCH(1),
enable_i => '1',
trig_i => trig_inv(i),
pulse_o => inv_outputs(i)
);
......
hdl/vme64x_i2c/rtl/i2c_slave.vhd
View file @ 00387791
......@@ -182,6 +182,11 @@ architecture behav of i2c_slave is
-- Bit counter on RX & TX
signal bit_cnt : unsigned(2 downto 0);
-- Watchdog counter signals
signal watchdog_cnt : unsigned(26 downto 0);
signal watchdog_rst : std_logic;
signal rst_fr_watchdog : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
......@@ -277,16 +282,17 @@ begin
p_fsm: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= ST_IDLE;
bit_cnt <= (others => '0');
rxsr <= (others => '0');
txsr <= (others => '0');
sda_o <= '0';
sda_en_o <= '0';
done_p_o <= '0';
op_o <= '0';
stat_o <= c_i2cs_idle;
if (rst_n_i = '0') or (rst_fr_watchdog = '1') then
state <= ST_IDLE;
watchdog_rst <= '1';
bit_cnt <= (others => '0');
rxsr <= (others => '0');
txsr <= (others => '0');
sda_o <= '0';
sda_en_o <= '0';
done_p_o <= '0';
op_o <= '0';
stat_o <= c_i2cs_idle;
-- I2C start condition
elsif (sda_falling = '1') and (scl_degl = '1') then
......@@ -306,11 +312,12 @@ begin
-- for a start condition.
---------------------------------------------------------------------
when ST_IDLE =>
bit_cnt <= (others => '0');
sda_o <= '0';
sda_en_o <= '0';
done_p_o <= '0';
stat_o <= c_i2cs_idle;
bit_cnt <= (others => '0');
sda_o <= '0';
sda_en_o <= '0';
done_p_o <= '0';
watchdog_rst <= '1';
stat_o <= c_i2cs_idle;
---------------------------------------------------------------------
-- ST_STA
......@@ -320,9 +327,11 @@ begin
-- SCL, we go into the address state.
---------------------------------------------------------------------
when ST_STA =>
bit_cnt <= (others => '0');
watchdog_rst <= '0';
bit_cnt <= (others => '0');
if (scl_falling = '1') then
state <= ST_ADDR;
watchdog_rst <= '1';
state <= ST_ADDR;
end if;
---------------------------------------------------------------------
......@@ -334,10 +343,14 @@ begin
-- ADDR_ACK state.
---------------------------------------------------------------------
when ST_ADDR =>
-- Clear watchdog reset
watchdog_rst <= '0';
-- Shifting in is done on falling edge of SCL
if (scl_falling = '1') then
rxsr <= rxsr(6 downto 0) & sda_degl;
bit_cnt <= bit_cnt + 1;
watchdog_rst <= '1';
rxsr <= rxsr(6 downto 0) & sda_degl;
bit_cnt <= bit_cnt + 1;
-- Shifted in 8 bits, go to ADDR_ACK. Check to see if received
-- address is ours and set op_o if so.
......@@ -359,6 +372,9 @@ begin
-- R/W bit received via I2C.
---------------------------------------------------------------------
when ST_ADDR_ACK =>
-- Clear watchdog reset
watchdog_rst <= '0';
-- Clear done pulse
done_p_o <= '0';
......@@ -371,6 +387,7 @@ begin
if (rxsr(7 downto 1) = i2c_addr_i) then
sda_o <= ack_n_i;
if (scl_falling = '1') then
watchdog_rst <= '1';
sda_en_o <= '0';
if (rxsr(0) = '0') then
state <= ST_RD;
......@@ -390,8 +407,12 @@ begin
-- Shift in bits sent by the master.
---------------------------------------------------------------------
when ST_RD =>
-- Clear watchdog reset
watchdog_rst <= '0';
-- Shifting occurs on falling edge of SCL
if (scl_falling = '1') then
watchdog_rst <= '1';
rxsr <= rxsr(6 downto 0) & sda_degl;
bit_cnt <= bit_cnt + 1;
......@@ -409,6 +430,9 @@ begin
-- Send ACK/NACK, as received from external command
---------------------------------------------------------------------
when ST_RD_ACK =>
-- Clear watchdog reset
watchdog_rst <= '0';
-- Clear done pulse
done_p_o <= '0';
......@@ -419,6 +443,7 @@ begin
-- based on the ACK received by external command, we read the next
-- bit (ACK) or go back to idle state (NACK)
if (scl_falling = '1') then
watchdog_rst <= '1';
sda_en_o <= '0';
if (ack_n_i = '0') then
state <= ST_RD;
......@@ -442,14 +467,17 @@ begin
-- Shift out the eight bits of TXSR.
---------------------------------------------------------------------
when ST_WR =>
watchdog_rst <= '0';
-- slave writes, so enable output
sda_en_o <= '1';
sda_o <= txsr(7);
sda_en_o <= '1';
sda_o <= txsr(7);
-- Shift TXSR on falling edge of SCL
if (scl_falling = '1') then
txsr <= txsr(6 downto 0) & '0';
bit_cnt <= bit_cnt + 1;
watchdog_rst <= '1';
txsr <= txsr(6 downto 0) & '0';
bit_cnt <= bit_cnt + 1;
-- Eight bits sent, disable SDA end go to WR_ACK
if (bit_cnt = 7) then
......@@ -470,8 +498,11 @@ begin
-- state.
---------------------------------------------------------------------
when ST_WR_ACK =>
watchdog_rst <= '0';
done_p_o <= '0';
if (scl_falling = '1') then
watchdog_rst <= '1';
if (sda_degl = '0') then
state <= ST_WR_LOAD_TXSR;
else
......@@ -490,6 +521,30 @@ begin
end if;
end process p_fsm;
--============================================================================
-- Watchdog counter process
-- Resets the FSM after one second. The watchdog_rst signal is controlled by
-- the FSM and resets the watchdog if the I2C master still controls the
-- slave, signaled by the SCL line going low. If for one second the master
-- does not toggle the SCL line, the FSM gets reset.
--============================================================================
p_watchdog: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (watchdog_rst = '1') then
watchdog_cnt <= (others => '0');
rst_fr_watchdog <= '0';
else
watchdog_cnt <= watchdog_cnt + 1;
rst_fr_watchdog <= '0';
if (watchdog_cnt = 124999999) then
watchdog_cnt <= (others => '0');
rst_fr_watchdog <= '1';
end if;
end if;
end if;
end process p_watchdog;
end architecture behav;
--==============================================================================
-- architecture end
......
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