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Conv TTL Blocking
Commit 0a562a82 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Merged with code-cleanup branch.

parents 9a13e613 18145f41
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hdl/IMAGES/image1/.gitignore
View file @ 0a562a82
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#Ignore autotrash from ISE #Ignore autotrash from ISE
project/* project/*
project/*/ project/*/
!project/image1.gise # !project/image1.gise
!project/image1.xise !project/image1.xise
!project/image1.tcl !project/image1.tcl
#!project/waveform/ #!project/waveform/
......
hdl/IMAGES/image1/constraints/V2/BloV2.ucf
View file @ 0a562a82
...@@ -7,8 +7,8 @@ ...@@ -7,8 +7,8 @@
##---------------------------------------- ##----------------------------------------
NET "rst_i" LOC = N20; NET "RST" LOC = N20;
NET "rst_i" IOSTANDARD = LVTTL; NET "RST" IOSTANDARD = LVTTL;
#NET "FPGA_SYSRESET_N" LOC = L20; #NET "FPGA_SYSRESET_N" LOC = L20;
NET "MR_N" LOC = T22; NET "MR_N" LOC = T22;
NET "MR_N" IOSTANDARD = LVTTL; NET "MR_N" IOSTANDARD = LVTTL;
...@@ -371,18 +371,18 @@ NET "LEVEL" IOSTANDARD = LVCMOS33; ...@@ -371,18 +371,18 @@ NET "LEVEL" IOSTANDARD = LVCMOS33;
##-- ##--
##-- + ACT: CMOS 3.3V input ##-- + ACT: CMOS 3.3V input
##------------------- ##-------------------
NET "fpga_rtmm_n_i[0]" LOC = V21; NET "FPGA_RTMM_N[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33; NET "FPGA_RTMM_N[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22; NET "FPGA_RTMM_N[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33; NET "FPGA_RTMM_N[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22; NET "FPGA_RTMM_N[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33; NET "FPGA_RTMM_N[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22; NET "FPGA_RTMP_N[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33; NET "FPGA_RTMP_N[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22; NET "FPGA_RTMP_N[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33; NET "FPGA_RTMP_N[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21; NET "FPGA_RTMP_N[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33; NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
###------------------- ###-------------------
###-- General purpose ###-- General purpose
###-- ###--
......
hdl/IMAGES/image1/project/image1.gise deleted 100644 → 0
View file @ 9a13e613
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hdl/IMAGES/image1/rtl/image1_core.vhd
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This diff is collapsed.
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ 0a562a82
...@@ -119,38 +119,38 @@ package image1_pkg is ...@@ -119,38 +119,38 @@ package image1_pkg is
c_mask_trigleds_wb, c_mask_trigleds_wb,
c_MASK_I2C_SLAVE); c_MASK_I2C_SLAVE);
component basic_trigger_top -- component basic_trigger_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6; -- generic(g_NUMBER_OF_CHANNELS : NATURAL := 6;
g_CLK_PERIOD : TIME := 20 ns; -- g_CLK_PERIOD : TIME := 20 ns;
g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns; -- g_OUTPUT_PULSE_LENGTH : TIME := 1000 ns;
g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns); -- g_LED_BLINKING_LENGTH : TIME := (10**6)*250 ns);
port (clk_i : in STD_LOGIC; -- port (clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC; -- rst_i : in STD_LOGIC;
--
led_ttl_o : out STD_LOGIC; -- led_ttl_o : out STD_LOGIC;
--
fpga_o_en : out STD_LOGIC; -- fpga_o_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC; -- fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC; -- fpga_o_inv_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC; -- fpga_o_blo_en : out STD_LOGIC;
--
level_i : in STD_LOGIC; -- level_i : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable -- switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the -- manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given -- --! 24V rail after a security given
--! delay -- --! delay
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); -- pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); -- pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); -- pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); -- pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); -- led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); -- led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
--
inv_i : in STD_LOGIC_VECTOR(4 downto 1); -- inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1)); -- inv_o : out STD_LOGIC_VECTOR(4 downto 1));
end component; -- end component;
-- component i2c_slave_top -- component i2c_slave_top
......
hdl/IMAGES/image1/top/image1_top.vhd
View file @ 0a562a82
...@@ -48,7 +48,7 @@ entity image1_top is ...@@ -48,7 +48,7 @@ entity image1_top is
); );
port port
( (
rst_i : in std_logic; RST : in std_logic;
CLK20_VCXO : in std_logic; CLK20_VCXO : in std_logic;
FPGA_CLK_P : in std_logic; --Using the 125MHz clock FPGA_CLK_P : in std_logic; --Using the 125MHz clock
FPGA_CLK_N : in std_logic; FPGA_CLK_N : in std_logic;
...@@ -102,8 +102,8 @@ entity image1_top is ...@@ -102,8 +102,8 @@ entity image1_top is
-- RTM identifiers, should match with the expected values -- RTM identifiers, should match with the expected values
-- TODO: add matching -- TODO: add matching
fpga_rtmm_n_i : in std_logic_vector(2 downto 0); FPGA_RTMM_N : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0) FPGA_RTMP_N : in std_logic_vector(2 downto 0)
); );
end image1_top; end image1_top;
...@@ -114,54 +114,68 @@ architecture Behavioral of image1_top is ...@@ -114,54 +114,68 @@ architecture Behavioral of image1_top is
generic generic
( (
g_NUMBER_OF_CHANNELS : NATURAL := 6 g_NUMBER_OF_CHANNELS : NATURAL := 6
); port );
port
( (
rst_i : in std_logic; rst_i : in std_logic;
clk_20_i : in std_logic; clk_20_i : in std_logic;
clk_125_i : in std_logic; clk_125_i : in std_logic;
-- LEDs -- LEDs
led_array_o : out t_led_array_o; led_array_o : out t_led_array_o;
led_front_n_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
-- I/Os for pulses -- I/Os for pulses
led_front_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1); pulse_front_n_i : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
led_rear_n : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1); pulse_front_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front_n : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1); pulse_rear_i : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1); pulse_rear_o : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in std_logic_vector(g_NUMBER_OF_CHANNELS downto 1); inv_n_i : in std_logic_vector(4 downto 1);
pulse_o_rear : out std_logic_vector(g_NUMBER_OF_CHANNELS downto 1); inv_o : out std_logic_vector(4 downto 1);
inv_i_n : in std_logic_vector(4 downto 1);
inv_o : out std_logic_vector(4 downto 1);
-- Lines for the i2c_slave -- Lines for the i2c_slave
i2c_slave_i : in t_i2c_slave_i; i2c_slave_i : in t_i2c_slave_i;
i2c_slave_o : out t_i2c_slave_o; i2c_slave_o : out t_i2c_slave_o;
-- FPGA Geographical address pins (reused for i2c address) -- FPGA Geographical address pins (reused for i2c address)
FPGA_GA : in std_logic_vector(4 downto 0); fpga_ga_i : in std_logic_vector(4 downto 0);
FPGA_GAP : in std_logic; fpga_gap_i : in std_logic;
-- Pins of the SPI interface to write into the Flash memory -- Pins of the SPI interface to write into the Flash memory
spi_master_i : in t_spi_master_i; spi_master_i : in t_spi_master_i;
spi_master_o : out t_spi_master_o; spi_master_o : out t_spi_master_o;
-- RTM identifiers, should match with the expected values
-- TODO: add matching
fpga_o_en : out std_logic; -- Enable signals
fpga_o_blo_en : out std_logic; fpga_en_o : out std_logic;
fpga_o_ttl_en : out std_logic; fpga_blo_en_o : out std_logic;
fpga_o_inv_en : out std_logic; fpga_ttl_en_o : out std_logic;
level_i : in std_logic; fpga_inv_en_o : out std_logic;
switch_i : in std_logic; -- General enable
manual_rst_n_o : out std_logic; -- It allows power sequencing of the -- Level and switch inputs
-- 24V rail after a security given delay level_i : in std_logic;
rtmm_i : in std_logic_vector(2 downto 0); switch_i : in std_logic;
rtmp_i : in std_logic_vector(2 downto 0)
-- Manual reset, allows power sequencing of the
-- 24V rail after a security given delay
manual_rst_n_o : out std_logic;
-- RTM identifiers
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0)
); );
end component; end component image1_core;
signal clk_125 : std_logic; signal clk_125 : std_logic;
signal s_led_array : t_led_array_o := c_led_array_default; signal s_led_array : t_led_array_o := c_led_array_default;
signal s_i2c_slave_i : t_i2c_slave_i; signal i2c_slave : t_i2c_slave_i;
signal s_i2c_slave_o : t_i2c_slave_o; signal s_i2c_slave_o : t_i2c_slave_o;
signal s_spi_master_i : t_spi_master_i; signal s_spi_master_i : t_spi_master_i;
signal s_spi_master_o : t_spi_master_o; signal s_spi_master_o : t_spi_master_o;
signal s_rtm_i : t_rtm_i; signal s_rtm_i : t_rtm_i;
signal s_switch_i : std_logic_vector(1 downto 1); signal switch : std_logic_vector(1 downto 1);
signal rtmm, rtmp : std_logic_vector(2 downto 0); signal rtmm, rtmp : std_logic_vector(2 downto 0);
...@@ -180,65 +194,65 @@ begin ...@@ -180,65 +194,65 @@ begin
O => clk_125 O => clk_125
); );
LED_CTRL0 <= s_led_array.CTRL0; LED_CTRL0 <= s_led_array.CTRL0;
LED_CTRL0_OEN <= s_led_array.CTRL0_OEN; LED_CTRL0_OEN <= s_led_array.CTRL0_OEN;
LED_CTRL1 <= s_led_array.CTRL1; LED_CTRL1 <= s_led_array.CTRL1;
LED_CTRL1_OEN <= s_led_array.CTRL1_OEN; LED_CTRL1_OEN <= s_led_array.CTRL1_OEN;
LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0; LED_MULTICAST_2_0 <= s_led_array.MULTICAST_2_0;
LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1; LED_MULTICAST_3_1 <= s_led_array.MULTICAST_3_1;
LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN; LED_WR_GMT_TTL_TTLN <= s_led_array.WR_GMT_TTL_TTLN;
LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR; LED_WR_LINK_SYSERROR <= s_led_array.WR_LINK_SYSERROR;
LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW; LED_WR_OK_SYSPW <= s_led_array.WR_OK_SYSPW;
LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C; LED_WR_OWNADDR_I2C <= s_led_array.WR_OWNADDR_I2C;
s_i2c_slave_i.SCL_I <= SCL_I; i2c_slave.SCL_I <= SCL_I;
s_i2c_slave_i.SDA_I <= SDA_I; i2c_slave.SDA_I <= SDA_I;
SCL_O <= s_i2c_slave_o.SCL_O; SCL_O <= s_i2c_slave_o.SCL_O;
SCL_OE <= s_i2c_slave_o.SCL_OE; SCL_OE <= s_i2c_slave_o.SCL_OE;
SDA_O <= s_i2c_slave_o.SDA_O; SDA_O <= s_i2c_slave_o.SDA_O;
SDA_OE <= s_i2c_slave_o.SDA_OE; SDA_OE <= s_i2c_slave_o.SDA_OE;
s_spi_master_i.DIN <= FPGA_PROM_DIN; s_spi_master_i.DIN <= FPGA_PROM_DIN;
FPGA_PROM_CCLK <= s_spi_master_o.CCLK; FPGA_PROM_CCLK <= s_spi_master_o.CCLK;
FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N; FPGA_PROM_CSO_B_N <= s_spi_master_o.CSO_B_N;
FPGA_PROM_MOSI <= s_spi_master_o.MOSI; FPGA_PROM_MOSI <= s_spi_master_o.MOSI;
rtmm <= not fpga_rtmm_n_i; rtmm <= not FPGA_RTMM_N;
rtmp <= not fpga_rtmp_n_i; rtmp <= not FPGA_RTMP_N;
s_switch_i <= EXTRA_SWITCH; switch <= EXTRA_SWITCH;
cmp_image1_core: image1_core cmp_image1_core: image1_core
generic map(g_NUMBER_OF_CHANNELS => 6) generic map(g_NUMBER_OF_CHANNELS => 6)
port map port map
( (
rst_i => rst_i, rst_i => RST,
clk_20_i => CLK20_VCXO, clk_20_i => CLK20_VCXO,
clk_125_i => clk_125, clk_125_i => clk_125,
led_array_o => s_led_array, led_array_o => s_led_array,
led_front_n => PULSE_FRONT_LED_N, led_front_n_o => PULSE_FRONT_LED_N,
led_rear_n => PULSE_REAR_LED_N, led_rear_n_o => PULSE_REAR_LED_N,
pulse_i_front_n => FPGA_INPUT_TTL_N, pulse_front_n_i => FPGA_INPUT_TTL_N,
pulse_o_front => FPGA_OUT_TTL, pulse_front_o => FPGA_OUT_TTL,
pulse_i_rear => FPGA_BLO_IN, pulse_rear_i => FPGA_BLO_IN,
pulse_o_rear => FPGA_TRIG_BLO, pulse_rear_o => FPGA_TRIG_BLO,
inv_i_n => INV_IN_N, inv_n_i => INV_IN_N,
inv_o => INV_OUT, inv_o => INV_OUT,
i2c_slave_i => s_i2c_slave_i, i2c_slave_i => i2c_slave,
i2c_slave_o => s_i2c_slave_o, i2c_slave_o => s_i2c_slave_o,
FPGA_GA => FPGA_GA , fpga_ga_i => FPGA_GA ,
FPGA_GAP => FPGA_GAP, fpga_gap_i => FPGA_GAP,
spi_master_i => s_spi_master_i, spi_master_i => s_spi_master_i,
spi_master_o => s_spi_master_o, spi_master_o => s_spi_master_o,
fpga_o_en => FPGA_OE, fpga_en_o => FPGA_OE,
fpga_o_blo_en => FPGA_BLO_OE, fpga_blo_en_o => FPGA_BLO_OE,
fpga_o_ttl_en => FPGA_TRIG_TTL_OE, fpga_ttl_en_o => FPGA_TRIG_TTL_OE,
fpga_o_inv_en => FPGA_INV_OE, fpga_inv_en_o => FPGA_INV_OE,
level_i => LEVEL, level_i => LEVEL,
switch_i => s_switch_i(1), switch_i => switch(1),
manual_rst_n_o => MR_N, manual_rst_n_o => MR_N,
rtmm_i => rtmm, rtmm_i => rtmm,
rtmp_i => rtmp rtmp_i => rtmp
); );
end Behavioral; end Behavioral;
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ 0a562a82
...@@ -43,10 +43,10 @@ entity basic_trigger_top is ...@@ -43,10 +43,10 @@ entity basic_trigger_top is
led_ttl_o : out std_logic; led_ttl_o : out std_logic;
-- Enable signals -- Enable signals
fpga_o_en : out std_logic; fpga_en_o : out std_logic;
fpga_o_ttl_en : out std_logic; fpga_ttl_en_o : out std_logic;
fpga_o_inv_en : out std_logic; fpga_inv_en_o : out std_logic;
fpga_o_blo_en : out std_logic; fpga_blo_en_o : out std_logic;
level_i : in std_logic; level_i : in std_logic;
switch_i : in std_logic; switch_i : in std_logic;
...@@ -55,14 +55,14 @@ entity basic_trigger_top is ...@@ -55,14 +55,14 @@ entity basic_trigger_top is
manual_rst_n_o : out std_logic; manual_rst_n_o : out std_logic;
-- Front and rear pulse signals -- Front and rear pulse signals
pulse_i_front : in std_logic_vector(g_number_of_channels downto 1); pulse_front_i : in std_logic_vector(g_number_of_channels downto 1);
pulse_o_front : out std_logic_vector(g_number_of_channels downto 1); pulse_front_o : out std_logic_vector(g_number_of_channels downto 1);
pulse_i_rear : in std_logic_vector(g_number_of_channels downto 1); pulse_rear_i : in std_logic_vector(g_number_of_channels downto 1);
pulse_o_rear : out std_logic_vector(g_number_of_channels downto 1); pulse_rear_o : out std_logic_vector(g_number_of_channels downto 1);
-- Front and rear LED signals -- Front and rear LED signals
led_o_front : out std_logic_vector(g_number_of_channels downto 1); led_front_o : out std_logic_vector(g_number_of_channels downto 1);
led_o_rear : out std_logic_vector(g_number_of_channels downto 1); led_rear_o : out std_logic_vector(g_number_of_channels downto 1);
-- Inverting inputs and outputs -- Inverting inputs and outputs
inv_i : in std_logic_vector(4 downto 1); inv_i : in std_logic_vector(4 downto 1);
...@@ -131,21 +131,21 @@ begin ...@@ -131,21 +131,21 @@ begin
led_ttl_o <= level; led_ttl_o <= level;
-- pulse signal assignments -- pulse signal assignments
pulse_in_front <= pulse_i_front when (level = '0') else pulse_in_front <= pulse_front_i when (level = '0') else
not pulse_i_front; not pulse_front_i;
pulse_in <= pulse_in_front or pulse_i_rear; pulse_in <= pulse_in_front or pulse_rear_i;
fpga_o_en <= fpga_out_en when (switch_i = '0') else '0'; fpga_en_o <= fpga_out_en when (switch_i = '0') else '0';
fpga_o_ttl_en <= fpga_out_ttl_en; fpga_ttl_en_o <= fpga_out_ttl_en;
fpga_o_inv_en <= fpga_out_inv_en; fpga_inv_en_o <= fpga_out_inv_en;
fpga_o_blo_en <= fpga_out_blo_en; fpga_blo_en_o <= fpga_out_blo_en;
led_o_front <= not(led); -- No need of accurate sync, hence we place led_front_o <= not(led); -- No need of accurate sync, hence we place
led_o_rear <= not(led); -- some combinatorial here. led_rear_o <= not(led); -- some combinatorial here.
pulse_o_front <= pulse_out when level = '0' else pulse_front_o <= pulse_out when level = '0' else
not pulse_out; not pulse_out;
pulse_o_rear <= pulse_out; pulse_rear_o <= pulse_out;
-- As we have one Schmitt inverter in the input, -- As we have one Schmitt inverter in the input,
-- and a buffer in the output, there's no need -- and a buffer in the output, there's no need
......
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 0a562a82
...@@ -38,9 +38,9 @@ entity i2c_regs is ...@@ -38,9 +38,9 @@ entity i2c_regs is
wb_master_stb_o : out STD_LOGIC; wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC; wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0); wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_data_i : in STD_LOGIC_VECTOR (31 downto 0); wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR (31 downto 0); wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR (15 downto 0); wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC; wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC; wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC; wb_master_err_i : in STD_LOGIC;
...@@ -50,9 +50,9 @@ entity i2c_regs is ...@@ -50,9 +50,9 @@ entity i2c_regs is
wb_slave_stb_i : in STD_LOGIC; wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC; wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR (3 downto 0); wb_slave_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_data_i : in STD_LOGIC_VECTOR (31 downto 0); wb_slave_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR (31 downto 0); wb_slave_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR (3 downto 0); wb_slave_adr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_slave_ack_o : out STD_LOGIC; wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC; wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC; wb_slave_err_o : out STD_LOGIC;
...@@ -106,7 +106,7 @@ architecture Behavioral of i2c_regs is ...@@ -106,7 +106,7 @@ architecture Behavioral of i2c_regs is
begin begin
wb_master_we_o <= s_wb_master_we_o; wb_master_we_o <= s_wb_master_we_o;
s_wb_slave_addr <= UNSIGNED(wb_slave_addr_i); s_wb_slave_addr <= UNSIGNED(wb_slave_adr_i);
s_CTR0_slv <= f_STD_LOGIC_VECTOR(s_CTR0); s_CTR0_slv <= f_STD_LOGIC_VECTOR(s_CTR0);
s_LT <= f_LT(LT_i); s_LT <= f_LT(LT_i);
...@@ -147,8 +147,8 @@ begin ...@@ -147,8 +147,8 @@ begin
wb_master_stb_o <= '0'; wb_master_stb_o <= '0';
wb_master_cyc_o <= '0'; wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0'); wb_master_sel_o <= (others => '0');
wb_master_data_o <= (others => '0'); wb_master_dat_o <= (others => '0');
wb_master_addr_o <= (others => '0'); wb_master_adr_o <= (others => '0');
s_dtx <= (others => '0'); s_dtx <= (others => '0');
else else
case wb_state is case wb_state is
...@@ -165,16 +165,16 @@ begin ...@@ -165,16 +165,16 @@ begin
wb_master_cyc_o <= '1'; wb_master_cyc_o <= '1';
wb_master_stb_o <= '1'; wb_master_stb_o <= '1';
wb_master_sel_o <= X"F"; wb_master_sel_o <= X"F";
wb_master_addr_o <= s_wb_addr_rd; wb_master_adr_o <= s_wb_addr_rd;
when S1N_WB_NOOP => when S1N_WB_NOOP =>
wb_master_cyc_o <= '1'; wb_master_cyc_o <= '1';
wb_master_stb_o <= '1'; wb_master_stb_o <= '1';
wb_master_sel_o <= X"F"; wb_master_sel_o <= X"F";
wb_master_addr_o <= s_wb_addr_rd; wb_master_adr_o <= s_wb_addr_rd;
when S1_PF_WB_DATA_OUT => when S1_PF_WB_DATA_OUT =>
s_DTX <= wb_master_data_i; s_DTX <= wb_master_dat_i;
when S2P_WB_WR_RQT => when S2P_WB_WR_RQT =>
null; null;
...@@ -184,16 +184,16 @@ begin ...@@ -184,16 +184,16 @@ begin
wb_master_stb_o <= '1'; wb_master_stb_o <= '1';
s_wb_master_we_o <= '1'; s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F"; wb_master_sel_o <= X"F";
wb_master_data_o <= f_ch_endian(DRXA_i); wb_master_dat_o <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0); wb_master_adr_o <= DRXB_i(15 downto 0);
when S2N_WB_NOOP => when S2N_WB_NOOP =>
wb_master_cyc_o <= '1'; wb_master_cyc_o <= '1';
wb_master_stb_o <= '1'; wb_master_stb_o <= '1';
s_wb_master_we_o <= '1'; s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F"; wb_master_sel_o <= X"F";
wb_master_data_o <= f_ch_endian(DRXA_i); wb_master_dat_o <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0); wb_master_adr_o <= DRXB_i(15 downto 0);
when S3_WB_ACK => when S3_WB_ACK =>
-- null; -- null;
...@@ -229,7 +229,7 @@ begin ...@@ -229,7 +229,7 @@ begin
s_wb_slave_ack <= '1'; s_wb_slave_ack <= '1';
case s_wb_slave_addr is case s_wb_slave_addr is
-- when c_CTR0_addr => -- when c_CTR0_addr =>
-- s_CTR0 <= f_CTR0(wb_slave_data_i); -- s_CTR0 <= f_CTR0(wb_slave_dat_i);
when others => when others =>
s_wb_slave_ack <= '0'; s_wb_slave_ack <= '0';
s_wb_slave_err <= '1'; s_wb_slave_err <= '1';
...@@ -238,15 +238,15 @@ begin ...@@ -238,15 +238,15 @@ begin
s_wb_slave_ack <= '1'; s_wb_slave_ack <= '1';
case s_wb_slave_addr is case s_wb_slave_addr is
when c_CTR0_addr => when c_CTR0_addr =>
wb_slave_data_o <= f_STD_LOGIC_VECTOR(s_CTR0); wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_CTR0);
when c_LT_addr => when c_LT_addr =>
wb_slave_data_o <= f_STD_LOGIC_VECTOR(s_LT); wb_slave_dat_o <= f_STD_LOGIC_VECTOR(s_LT);
when c_DTX_addr => when c_DTX_addr =>
wb_slave_data_o <= s_DTX; wb_slave_dat_o <= s_DTX;
when c_DRXA_addr => when c_DRXA_addr =>
wb_slave_data_o <= DRXA_i; wb_slave_dat_o <= DRXA_i;
when c_DRXB_addr => when c_DRXB_addr =>
wb_slave_data_o <= DRXB_i; wb_slave_dat_o <= DRXB_i;
when others => when others =>
s_wb_slave_ack <= '0'; s_wb_slave_ack <= '0';
s_wb_slave_err <= '1'; s_wb_slave_err <= '1';
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ 0a562a82
...@@ -68,10 +68,10 @@ entity i2c_slave_core is ...@@ -68,10 +68,10 @@ entity i2c_slave_core is
clk_i : in std_logic; clk_i : in std_logic;
rst_i : in std_logic; rst_i : in std_logic;
-- I2C pins -- I2C pins
sda_oen : out std_logic; sda_en_o : out std_logic;
sda_i : in std_logic; sda_i : in std_logic;
sda_o : out std_logic; sda_o : out std_logic;
scl_oen : out std_logic; scl_en_o : out std_logic;
scl_i : in std_logic; scl_i : in std_logic;
scl_o : out std_logic; scl_o : out std_logic;
...@@ -150,7 +150,7 @@ architecture Behavioral of i2c_slave_core is ...@@ -150,7 +150,7 @@ architecture Behavioral of i2c_slave_core is
-- i2c signals -- i2c signals
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
signal s_sda_o : std_logic; signal s_sda_o : std_logic;
signal s_sda_oen : std_logic; signal s_sda_en_o : std_logic;
signal s_bit_done : std_logic; signal s_bit_done : std_logic;
...@@ -244,7 +244,7 @@ begin ...@@ -244,7 +244,7 @@ begin
s_watchdog_cnt <= to_integer(UNSIGNED(s_watchdog_cnt_slv)); s_watchdog_cnt <= to_integer(UNSIGNED(s_watchdog_cnt_slv));
scl_o <= '1'; scl_o <= '1';
scl_oen <= '0'; scl_en_o <= '0';
sda_o <= s_sda_o; sda_o <= s_sda_o;
...@@ -266,22 +266,22 @@ begin ...@@ -266,22 +266,22 @@ begin
end case; end case;
end process; end process;
sda_oen <= s_sda_oen; sda_en_o <= s_sda_en_o;
p_sda_oen: process(state) p_sda_en_o: process(state)
begin begin
s_sda_oen <= '0'; s_sda_en_o <= '0';
case state is case state is
when S2A_I2C_ADDR_ACK => when S2A_I2C_ADDR_ACK =>
s_sda_oen <= '1'; s_sda_en_o <= '1';
when S3A_WISHBONE_ADDR_ACK => when S3A_WISHBONE_ADDR_ACK =>
s_sda_oen <= '1'; s_sda_en_o <= '1';
when S5RA_READ_SDA_ACK => when S5RA_READ_SDA_ACK =>
s_sda_oen <= '1'; s_sda_en_o <= '1';
when S5W1A_I2C_ADDR_ACK => when S5W1A_I2C_ADDR_ACK =>
s_sda_oen <= '1'; s_sda_en_o <= '1';
when S5W2_WRITE_SDA => when S5W2_WRITE_SDA =>
s_sda_oen <= '1'; s_sda_en_o <= '1';
when others => when others =>
null; null;
end case; end case;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
View file @ 0a562a82
...@@ -163,10 +163,10 @@ package i2c_slave_pkg is ...@@ -163,10 +163,10 @@ package i2c_slave_pkg is
clk_i : in STD_LOGIC; clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC; rst_i : in STD_LOGIC;
sda_oen : out STD_LOGIC; sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC; sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC; sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC; scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC; scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC; scl_o : out STD_LOGIC;
...@@ -189,9 +189,9 @@ package i2c_slave_pkg is ...@@ -189,9 +189,9 @@ package i2c_slave_pkg is
wb_master_stb_o : out STD_LOGIC; wb_master_stb_o : out STD_LOGIC;
wb_master_cyc_o : out STD_LOGIC; wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0); wb_master_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_data_i : in STD_LOGIC_VECTOR (31 downto 0); wb_master_dat_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR (31 downto 0); wb_master_dat_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR (15 downto 0); wb_master_adr_o : out STD_LOGIC_VECTOR (15 downto 0);
wb_master_ack_i : in STD_LOGIC; wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC; wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC; wb_master_err_i : in STD_LOGIC;
...@@ -200,9 +200,9 @@ package i2c_slave_pkg is ...@@ -200,9 +200,9 @@ package i2c_slave_pkg is
wb_slave_stb_i : in STD_LOGIC; wb_slave_stb_i : in STD_LOGIC;
wb_slave_cyc_i : in STD_LOGIC; wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0); wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0); wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0); wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0); wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC; wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC; wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC; wb_slave_err_o : out STD_LOGIC;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ 0a562a82
...@@ -32,10 +32,10 @@ entity i2c_slave_top is ...@@ -32,10 +32,10 @@ entity i2c_slave_top is
); );
port port
( (
sda_oen : out STD_LOGIC; sda_en_o : out STD_LOGIC;
sda_i : in STD_LOGIC; sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC; sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC; scl_en_o : out STD_LOGIC;
scl_i : in STD_LOGIC; scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC; scl_o : out STD_LOGIC;
...@@ -46,9 +46,9 @@ entity i2c_slave_top is ...@@ -46,9 +46,9 @@ entity i2c_slave_top is
wb_master_cyc_o : out STD_LOGIC; wb_master_cyc_o : out STD_LOGIC;
wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0); wb_master_sel_o : out STD_LOGIC_VECTOR(3 downto 0);
wb_master_we_o : out STD_LOGIC; wb_master_we_o : out STD_LOGIC;
wb_master_data_i : in STD_LOGIC_VECTOR(31 downto 0); wb_master_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_master_data_o : out STD_LOGIC_VECTOR(31 downto 0); wb_master_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_master_addr_o : out STD_LOGIC_VECTOR(15 downto 0); wb_master_adr_o : out STD_LOGIC_VECTOR(15 downto 0);
wb_master_ack_i : in STD_LOGIC; wb_master_ack_i : in STD_LOGIC;
wb_master_rty_i : in STD_LOGIC; wb_master_rty_i : in STD_LOGIC;
wb_master_err_i : in STD_LOGIC; wb_master_err_i : in STD_LOGIC;
...@@ -57,9 +57,9 @@ entity i2c_slave_top is ...@@ -57,9 +57,9 @@ entity i2c_slave_top is
wb_slave_cyc_i : in STD_LOGIC; wb_slave_cyc_i : in STD_LOGIC;
wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0); wb_slave_sel_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_we_i : in STD_LOGIC; wb_slave_we_i : in STD_LOGIC;
wb_slave_data_i : in STD_LOGIC_VECTOR(31 downto 0); wb_slave_dat_i : in STD_LOGIC_VECTOR(31 downto 0);
wb_slave_data_o : out STD_LOGIC_VECTOR(31 downto 0); wb_slave_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
wb_slave_addr_i : in STD_LOGIC_VECTOR(3 downto 0); wb_slave_adr_i : in STD_LOGIC_VECTOR(3 downto 0);
wb_slave_ack_o : out STD_LOGIC; wb_slave_ack_o : out STD_LOGIC;
wb_slave_rty_o : out STD_LOGIC; wb_slave_rty_o : out STD_LOGIC;
wb_slave_err_o : out STD_LOGIC; wb_slave_err_o : out STD_LOGIC;
...@@ -100,10 +100,10 @@ begin ...@@ -100,10 +100,10 @@ begin
clk_i => wb_clk_i, clk_i => wb_clk_i,
rst_i => wb_rst_i, rst_i => wb_rst_i,
sda_oen => sda_oen, sda_en_o => sda_en_o,
sda_i => sda_i, sda_i => sda_i,
sda_o => sda_o, sda_o => sda_o,
scl_oen => scl_oen, scl_en_o => scl_en_o,
scl_i => scl_i, scl_i => scl_i,
scl_o => scl_o, scl_o => scl_o,
...@@ -133,9 +133,9 @@ begin ...@@ -133,9 +133,9 @@ begin
wb_master_stb_o => wb_master_stb_o, wb_master_stb_o => wb_master_stb_o,
wb_master_cyc_o => wb_master_cyc_o, wb_master_cyc_o => wb_master_cyc_o,
wb_master_sel_o => wb_master_sel_o, wb_master_sel_o => wb_master_sel_o,
wb_master_data_i => wb_master_data_i, wb_master_dat_i => wb_master_dat_i,
wb_master_data_o => wb_master_data_o, wb_master_dat_o => wb_master_dat_o,
wb_master_addr_o => wb_master_addr_o, wb_master_adr_o => wb_master_adr_o,
wb_master_ack_i => wb_master_ack_i, wb_master_ack_i => wb_master_ack_i,
wb_master_rty_i => wb_master_rty_i, wb_master_rty_i => wb_master_rty_i,
wb_master_err_i => wb_master_err_i, wb_master_err_i => wb_master_err_i,
...@@ -144,9 +144,9 @@ begin ...@@ -144,9 +144,9 @@ begin
wb_slave_stb_i => wb_slave_stb_i, wb_slave_stb_i => wb_slave_stb_i,
wb_slave_cyc_i => wb_slave_cyc_i, wb_slave_cyc_i => wb_slave_cyc_i,
wb_slave_sel_i => wb_slave_sel_i, wb_slave_sel_i => wb_slave_sel_i,
wb_slave_data_i => wb_slave_data_i, wb_slave_dat_i => wb_slave_dat_i,
wb_slave_data_o => wb_slave_data_o, wb_slave_dat_o => wb_slave_dat_o,
wb_slave_addr_i => wb_slave_addr_i, wb_slave_adr_i => wb_slave_adr_i,
wb_slave_ack_o => wb_slave_ack_o, wb_slave_ack_o => wb_slave_ack_o,
wb_slave_rty_o => wb_slave_rty_o, wb_slave_rty_o => wb_slave_rty_o,
wb_slave_err_o => wb_slave_err_o, wb_slave_err_o => wb_slave_err_o,
......
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