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Updating documentation and m25p32 core.

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hdl/m25p32/rtl/m25p32_buff.vhd
View file @ 1ea34945
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
---------------------------------------------------------------------------------
-- Company: CERN, BE-CO
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 08:26:02 06/18/2012
......
hdl/m25p32/rtl/m25p32_core.vhd
View file @ 1ea34945
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 23:57:51 06/10/2012
......
hdl/m25p32/rtl/m25p32_pkg.vhd
View file @ 1ea34945
......@@ -76,7 +76,7 @@ package m25p32_pkg is
--! Attribute length for every register
attribute a_length : INTEGER;
attribute a_length : NATURAL;
----------------------------------------
-- ConTRol 0 Register
......@@ -146,17 +146,17 @@ package m25p32_pkg is
----------------------------------------
-- BIT NAME DESCRIPTION
-- 7-0 PAGE PAGE
-- 15-8 SECT SECTor
-- 23-16 y Reserved
-- 13-8 SECT SECTor
-- 15-14 y Reserved
----------------------------------------
type r_BUF is
record
PAGE : UNSIGNED (7 downto 0);
SECT : UNSIGNED (13 downto 8);
y : STD_LOGIC_VECTOR(23 downto 14);
y : STD_LOGIC_VECTOR(15 downto 14);
end record;
attribute a_length of r_BUF : type is 24;
attribute a_length of r_BUF : type is 16;
type r_DBUF is array (0 to 1) of r_BUF;
......@@ -297,7 +297,7 @@ package m25p32_pkg is
return r_CTR0;
function f_CTR1 (signal r_register : in STD_LOGIC_VECTOR(23 downto 0))
return r_CTR1;
function f_BUF (signal r_register : in STD_LOGIC_VECTOR(23 downto 0))
function f_BUF (signal r_register : in STD_LOGIC_VECTOR(15 downto 0))
return r_BUF;
function f_FMOH (signal r_register : in STD_LOGIC_VECTOR(31 downto 0))
return r_FMOH;
......@@ -447,13 +447,13 @@ package body m25p32_pkg is
--! @brief Translation from STD_LOGIC_VECTOR to r_BUF record
--! @param r_register STD_LOGIC_VECTOR to be translated
-----------------------------------------------------------------------------
function f_BUF (signal r_register : in STD_LOGIC_VECTOR(23 downto 0))
function f_BUF (signal r_register : in STD_LOGIC_VECTOR(15 downto 0))
return r_BUF is
variable v_BUF : r_BUF;
begin
v_BUF.PAGE := unsigned(r_register(7 downto 0));
v_BUF.SECT := unsigned(r_register(13 downto 8));
v_BUF.y := r_register(23 downto 14);
v_BUF.y := r_register(15 downto 14);
return v_BUF;
end f_BUF;
......
hdl/m25p32/rtl/m25p32_regs.vhd
View file @ 1ea34945
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
......
hdl/m25p32/rtl/m25p32_top.vhd
View file @ 1ea34945
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 01:22:27 06/11/2012
......
hdl/m25p32/test/m25p32_top_tb.vhd
View file @ 1ea34945
......@@ -23,6 +23,7 @@ library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.m25p32_pkg.ALL;
use work.serializer_sim_pkg.ALL;
entity m25p32_top_tb is
end m25p32_top_tb;
......@@ -81,12 +82,32 @@ architecture Behavioral of m25p32_top_tb is
signal s_reg_data_wb : STD_LOGIC_VECTOR (31 downto 0);
--! Signals for
signal s_rst : STD_LOGIC;
signal s_enable : STD_LOGIC;
signal s_serial_data : STD_LOGIC;
signal s_serial_clock : STD_LOGIC;
signal s_clk : STD_LOGIC;
signal s_serial_frame_rcved : STD_LOGIC;
signal s_parallel_frame : STD_LOGIC_VECTOR (c_SERIAL_LENGTH - 1
downto 0);
signal s_inst_rcved : inst_parallel;
signal s_addr_rcved : addr_parallel;
signal s_data_rcved : data_parallel;
begin
s_FMOH_slv <= f_STD_LOGIC_VECTOR(s_FMOH);
s_SR_m25p32_slv <= f_STD_LOGIC_VECTOR(s_SR_m25p32);
--! Connections for the serializaer
s_rst <= wb_rst_i;
s_serial_data <= prom_mosi_o;
s_serial_clock <= prom_cclk_o;
s_clk <= wb_clk;
--! Connections for the m25p32
uut: m25p32_top port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
......@@ -107,8 +128,20 @@ begin
prom_cs0_b_n_o => prom_cs0_b_n_o,
prom_din_i => prom_din_i);
--! Connections for the serializer
tester_uut: serializer_sim port map(
rst_i => s_rst,
enable_i => s_enable,
serial_data_i => s_serial_data,
serial_clock_i => s_serial_clock,
clk_i => s_clk,
serial_frame_rcved_o => s_serial_frame_rcved,
parallel_frame_o => s_parallel_frame);
clk_i_process :process
--! @brief Process that generates the wb_clk
clk_i_process : process
begin
wb_clk <= '0';
wait for c_WISHBONE_PERIOD/2;
......@@ -117,8 +150,31 @@ begin
end process;
--! @brief Process that shows the instructions received from
--! serializer_sim.vhd
--! @param wb_clk The wb_clk that clocks the output of serializer_sim.vhd
p_rcved_serial : process(wb_clk)
begin
if rising_edge(wb_clk) then
--! When we don't have certanity about what we have received,
--! the line goes to blue ('Z');
s_inst_rcved.inst <= (others => 'Z');
s_addr_rcved.addr <= (others => 'Z');
s_data_rcved.data <= (others => 'Z');
--! Formatting for better ModelSim view
if s_serial_frame_rcved = '1' then
s_inst_rcved <= f_INST_PARALLEL (s_parallel_frame);
s_addr_rcved <= f_ADDR_PARALLEL (s_parallel_frame);
s_data_rcved <= f_DATA_PARALLEL (s_parallel_frame);
end if;
end if;
end process;
--! @brief Testbench
m25p32_access : process
--! @brief Init procedure for the test
procedure init_cond is
begin
--! We reset the wishbone bus
......@@ -135,6 +191,8 @@ begin
s_reg_data_wb <= (others => '0');
end procedure;
--! @brief For controlling the m25p32
--! @param
procedure set_FMOH (m25p32_instruction: t_operations;
page : INTEGER;
sector : INTEGER) is
......@@ -215,6 +273,9 @@ begin
begin
--! This line is cosmetic because this register is not loaded in the
--! core until a call to send_instruction procedure is issued.
s_FMOH <= c_FMOH_default;
......
hdl/m25p32/test/serializer_sim.vhd
View file @ 1ea34945
......@@ -45,38 +45,44 @@ use work.serializer_sim_pkg.ALL;
entity serializer_sim is
generic(
g_SERIAL_LENGTH : NATURAL := c_SERIAL_LENGTH;
g_PARALLEL_LENGTH : NATURAL := c_PARALLEL_LENGTH;
g_SERIAL_LENGTH : NATURAL := c_SERIAL_LENGTH
); port(
rst_i : in STD_LOGIC;
enable_i : in STD_LOGIC;
serial_data_i : in STD_LOGIC_VECTOR (c_SERIAL_LENGTH - 1 downto 0);
serial_data_i : in STD_LOGIC;
serial_clock_i : in STD_LOGIC;
FMOH_i : in STD_LOGIC_VECTOR (r_FMOH'a_length - 1 downto 0);
clk_i : in STD_LOGIC;
serial_frame_rcved_o : out STD_LOGIC;
parallel_frame_o : out STD_LOGIC_VECTOR (8*c_PARALLEL_LENGTH - 1 downto 0)
parallel_frame_o : out STD_LOGIC_VECTOR (c_SERIAL_LENGTH - 1 downto 0)
);
end serializer_sim;
architecture Behavioral of serializer_sim is
signal s_inst : inst_parallel;
signal s_addr : addr_parallel;
signal s_data : data_parallel;
signal s_inst : inst_parallel;
signal s_addr : addr_parallel;
signal s_data : data_parallel;
signal s_counter : INTEGER;
signal reset_cnt : STD_LOGIC;
signal s_counter : INTEGER;
signal reset_cnt : STD_LOGIC;
begin
parallel_frame_o(parallel_data_o'length - 1 downto parallel_data_o'length - 1
- inst_parallel'a_length) <= s_inst;
parallel_frame_o(parallel_data_o'length - parallel_inst'a_length - 1
downto parallel_data_o'length - 1
- inst_parallel'a_length
- addr_parallel'a_length) <= s_addr;
parallel_frame_o(data_parallel_o'length - 1 downto 0) <= s_data;
parallel_frame_o(c_SERIAL_LENGTH - 1
downto c_SERIAL_LENGTH - 1
- (inst_parallel'a_length - 1))
<= f_STD_LOGIC_VECTOR(s_inst);
parallel_frame_o( c_SERIAL_LENGTH
- inst_parallel'a_length - 1
downto c_SERIAL_LENGTH - 1
- inst_parallel'a_length
- (addr_parallel'a_length - 1))
<= f_STD_LOGIC_VECTOR(s_addr);
parallel_frame_o(data_parallel'a_length - 1
downto 0)
<= f_STD_LOGIC_VECTOR(s_data);
p_serial_clock :process(serial_clock_i, reset_cnt)
......@@ -94,13 +100,13 @@ begin
s_counter <= s_counter + 1;
--! We capture the signal at the sampling time
if s_counter < 8*c_SIZE_BLOCKS(0) then
s_inst.inst(8*c_s_counter) <= serial_data_i;
elsif (s_counter < 8*(c_SIZE_BLOCKS(1)+c_SIZE_BLOCKS(0))
s_inst.inst(s_counter) <= serial_data_i;
elsif (s_counter < 8*(c_SIZE_BLOCKS(1)+c_SIZE_BLOCKS(0)))
and (s_counter >= 8* c_SIZE_BLOCKS(0)) then
s_addr.inst(s_counter - 8* c_SIZE_BLOCKS(0)) <= serial_data_i;
s_addr.addr(s_counter - 8* c_SIZE_BLOCKS(0)) <= serial_data_i;
else
s_data.inst(s_counter - 8*(c_SIZE_BLOCKS(1) + c_SIZE_BLOCKS(0)))
<= serial_data_i;
s_data.data(s_counter - 8*(c_SIZE_BLOCKS(1) + c_SIZE_BLOCKS(0)))
<= serial_data_i;
end if;
else
end if;
......@@ -117,6 +123,7 @@ begin
reset_cnt <= '0';
if rst_i = '1' then
reset_cnt <= '1';
--! Add all the logic here to generate serial_frame_rcved_o
end if;
end if;
end process;
......
hdl/m25p32/test/serializer_sim_pkg.vhd
View file @ 1ea34945
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hdl/spi_master_multifield/doc/spiSpecs.tex
View file @ 1ea34945
%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage[pdfborder = 0 0 0 1]{hyperref}
\usepackage{graphicx}
%%\usepackage{draftwatermark}
%%\SetWatermarkLightness{0.9}
%%\SetWatermarkScale{5}
\begin{document}
\title{SPI multifield HDL core}
\title{\textbf{{\LARGE SPI multifield HDL core}}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{July 20, 2012}
\maketitle
\hypersetup{
colorlinks = true,
urlcolor = blue
pdftitle = {SPI multifield HDL core},
pdfauthor = {Carlos Gil Soriano},
pdfsubject = {Reference guide for SPI multifield HDL core},
pdfkeywords = {SPI, VHDL, core, register, mapping}
}
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.5,
keepaspectratio]{../../../doc/OHWR/Pictures/Figures/OHRlogo.png}
\includegraphics[scale=0.25,
keepaspectratio]{../../../doc/OHWR/Pictures/Figures/CERN-Logo.png}
\end{center}
\end{figure}
\begin{abstract}
A configurable SPI multifield HDL core is shown. This core is able to
......@@ -33,7 +51,7 @@
\vspace{2cm}
\begin{center}
\begin{tabular}{|p{2.5cm}|p{3.5cm}|p{3cm}|}
\begin{tabular}{|p{2.5cm}|p{3.75cm}|p{3cm}|}
\hline
\multicolumn{3}{|c|}{\textbf{Revision history}}\\
\hline
......@@ -41,14 +59,34 @@
\textbf{HDL version} & \textbf{Module} & \textbf{Date}\\
\hline
0.1 & SPI master multifield & July 20, 2012\\
\hline
\hline
\end{tabular}
\end{center}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
Copyright CERN 2012.\\
This documentation describes Open Hardware and is licensed under the
CERN OHL v.1.1.\\
You may redistribute and modify this documentation under the terms of the CERN
OHL v.1.1. (\url{http://ohwr.org/cernohl}). This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.\\
Please see the CERN OHL variable.1.1 for applicable conditions.\\
\pagebreak
\setcounter{tocdepth}{3}
\tableofcontents
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\section{Structure}
The SPI module contains several blocks related the following way:\\
......
hdl/spi_master_multifield/rtl/spi_master_core.vhd
View file @ 1ea34945
......@@ -46,27 +46,26 @@ use work.ctdah_pkg.ALL;
entity spi_master_core is
generic(
g_INST_LENGTH : NATURAL := 1;
g_ADDR_LENGTH : NATURAL := 3;
g_DATA_LENGTH : NATURAL := 256;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
g_INST_LENGTH : NATURAL := 1;
g_ADDR_LENGTH : NATURAL := 3;
g_DATA_LENGTH : NATURAL := 256;
g_CLK_I_PERIOD : NATURAL := c_CLK_I_PERIOD);
port(
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
clk_i : in STD_LOGIC;
inst_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (15 downto 0);
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
spi_clk_o : out STD_LOGIC;
spi_cs_n_o : out STD_LOGIC
);
inst_i : in STD_LOGIC_VECTOR (8*g_INST_LENGTH - 1 downto 0);
addr_i : in STD_LOGIC_VECTOR (8*g_ADDR_LENGTH - 1 downto 0);
data_i : in STD_LOGIC_VECTOR (8*g_DATA_LENGTH - 1 downto 0);
SPI0_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI1_i : in STD_LOGIC_VECTOR (31 downto 0);
SPI2_o : out STD_LOGIC_VECTOR (15 downto 0);
spi_mosi_o : out STD_LOGIC;
spi_miso_i : in STD_LOGIC;
spi_clk_o : out STD_LOGIC;
spi_cs_n_o : out STD_LOGIC);
end spi_master_core;
architecture Behavioral of spi_master_core is
......
hdl/trigger/doc/Trigger.tex 0 → 100755
View file @ 1ea34945
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