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Conv TTL Blocking
Commit 1edb77ce authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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top level: pulse width now 1.2us 

- renamed vme64x_i2c to elma_i2c
- continued modifications on ug-conv-ttl-blo
parent 2b8f54e4
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doc/ug/fig/conv-sys-bd.svg
View file @ 1edb77ce
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
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<defs <defs
id="defs4"> id="defs4">
<marker <marker
...@@ -82,8 +82,8 @@ ...@@ -82,8 +82,8 @@
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...@@ -119,7 +119,7 @@ ...@@ -119,7 +119,7 @@
<dc:format>image/svg+xml</dc:format> <dc:format>image/svg+xml</dc:format>
<dc:type <dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" /> rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title> <dc:title />
</cc:Work> </cc:Work>
</rdf:RDF> </rdf:RDF>
</metadata> </metadata>
...@@ -805,7 +805,7 @@ ...@@ -805,7 +805,7 @@
id="tspan11103" id="tspan11103"
x="432.28348" x="432.28348"
y="81.496063" y="81.496063"
style="font-size:16px;font-style:italic;font-weight:bold;text-align:center;text-anchor:middle">CONV-TTL-BLO[-RTM]</tspan></text> style="font-size:16px;font-style:italic;font-weight:bold;text-align:center;text-anchor:middle">CONV-TTL-RTM[-BLO]</tspan></text>
<text <text
xml:space="preserve" xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
......
doc/ug/fig/pulse-def.pdf
View file @ 1edb77ce
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doc/ug/fig/pulse-def.svg
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doc/ug/ug-conv-ttl-blo.tex
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hdl/vme64x_i2c/rtl/Manifest.py → hdl/elma_i2c/rtl/Manifest.py
View file @ 1edb77ce
files = [ files = [
"i2c_slave_pkg.vhd", "i2c_slave_pkg.vhd",
"i2c_slave.vhd", "i2c_slave.vhd",
"vme64x_i2c.vhd" "elma_i2c.vhd"
] ]
modules = { modules = {
......
hdl/vme64x_i2c/rtl/vme64x_i2c.vhd → hdl/elma_i2c/rtl/elma_i2c.vhd
View file @ 1edb77ce
...@@ -58,7 +58,7 @@ use ieee.numeric_std.all; ...@@ -58,7 +58,7 @@ use ieee.numeric_std.all;
use work.i2c_slave_pkg.all; use work.i2c_slave_pkg.all;
entity vme64x_i2c is entity elma_i2c is
port port
( (
-- Clock, reset -- Clock, reset
...@@ -90,9 +90,9 @@ entity vme64x_i2c is ...@@ -90,9 +90,9 @@ entity vme64x_i2c is
wbm_rty_i : in std_logic; wbm_rty_i : in std_logic;
wbm_err_i : in std_logic wbm_err_i : in std_logic
); );
end entity vme64x_i2c; end entity elma_i2c;
architecture behav of vme64x_i2c is architecture behav of elma_i2c is
--============================================================================ --============================================================================
-- Type declarations -- Type declarations
......
hdl/release/syn/Makefile
View file @ 1edb77ce
...@@ -42,9 +42,9 @@ FILES := ../top/conv_ttl_blo_v2.ucf \ ...@@ -42,9 +42,9 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \ ../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \ ../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../reset_gen/rtl/reset_gen.vhd \ ../../reset_gen/rtl/reset_gen.vhd \
../../vme64x_i2c/rtl/i2c_slave_pkg.vhd \ ../../elma_i2c/rtl/i2c_slave_pkg.vhd \
../../vme64x_i2c/rtl/i2c_slave.vhd \ ../../elma_i2c/rtl/i2c_slave.vhd \
../../vme64x_i2c/rtl/vme64x_i2c.vhd \ ../../elma_i2c/rtl/elma_i2c.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \ ../../glitch_filt/rtl/glitch_filt.vhd \
../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \ ../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \ ../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 1edb77ce
...@@ -72,34 +72,35 @@ ...@@ -72,34 +72,35 @@
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1370529254"> <transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1370529254"> <transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1370529254"> <transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1370529254"> <transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1370529254"> <transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1370529254"> <transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529254" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1370529254"> <transform xil_pn:end_ts="1370609192" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529270" xil_pn:in_ck="1402893700349391657" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1370529254"> <transform xil_pn:end_ts="1370609208" xil_pn:in_ck="-4867058225791759267" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1370609192">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -117,11 +118,11 @@ ...@@ -117,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529270" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1370529270"> <transform xil_pn:end_ts="1370609208" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1370609208">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529279" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1370529270"> <transform xil_pn:end_ts="1370609217" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1370609208">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
...@@ -130,7 +131,7 @@ ...@@ -130,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/> <outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529315" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1370529279"> <transform xil_pn:end_ts="1370609256" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1370609217">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
...@@ -143,7 +144,7 @@ ...@@ -143,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/> <outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/> <outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529353" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1370529315"> <transform xil_pn:end_ts="1370609294" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1370609256">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
...@@ -157,7 +158,7 @@ ...@@ -157,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/> <outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529375" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1370529353"> <transform xil_pn:end_ts="1370609316" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1370609294">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -169,7 +170,7 @@ ...@@ -169,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1370529353" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1370529342"> <transform xil_pn:end_ts="1370609294" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1370609283">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo_v2.xise
View file @ 1edb77ce
...@@ -350,7 +350,7 @@ ...@@ -350,7 +350,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file> </file>
<file xil_pn:name="../rtl/conv_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file> </file>
<file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
...@@ -359,19 +359,19 @@ ...@@ -359,19 +359,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file> </file>
<file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="../../vme64x_i2c/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../elma_i2c/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="../../vme64x_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../elma_i2c/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="../../vme64x_i2c/rtl/vme64x_i2c.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../elma_i2c/rtl/elma_i2c.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file> </file>
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
...@@ -644,7 +644,7 @@ ...@@ -644,7 +644,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
</files> </files>
......
hdl/release/top/Manifest.py
View file @ 1edb77ce
...@@ -7,7 +7,7 @@ modules = { ...@@ -7,7 +7,7 @@ modules = {
"local" : [ "local" : [
"../../reset_gen", "../../reset_gen",
"../rtl", "../rtl",
"../../vme64x_i2c", "../../elma_i2c",
"../../ctb_pulse_gen", "../../ctb_pulse_gen",
"../../rtm_detector", "../../rtm_detector",
"../../bicolor_led_ctrl", "../../bicolor_led_ctrl",
......
hdl/release/top/conv_ttl_blo_v2.ucf
View file @ 1edb77ce
...@@ -62,7 +62,8 @@ NET "mr_n_o" LOC = T22; ...@@ -62,7 +62,8 @@ NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33; NET "mr_n_o" IOSTANDARD = LVCMOS33;
# NET "clk20_vcxo_i" LOC = E16; # NET "clk20_vcxo_i" LOC = E16;
# TIMESPEC TS_clk_i = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %; # NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
# TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12; NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11; NET "fpga_clk_n_i" LOC = G11;
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 1edb77ce
...@@ -230,7 +230,7 @@ architecture behav of conv_ttl_blo_v2 is ...@@ -230,7 +230,7 @@ architecture behav of conv_ttl_blo_v2 is
-- I2C bridge -- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers) -- (use: convert I2C transfers into WB transfers on memmapped registers)
component vme64x_i2c is component elma_i2c is
port port
( (
-- Clock, reset -- Clock, reset
...@@ -262,7 +262,7 @@ architecture behav of conv_ttl_blo_v2 is ...@@ -262,7 +262,7 @@ architecture behav of conv_ttl_blo_v2 is
wbm_rty_i : in std_logic; wbm_rty_i : in std_logic;
wbm_err_i : in std_logic wbm_err_i : in std_logic
); );
end component vme64x_i2c; end component elma_i2c;
component conv_regs is component conv_regs is
port ( port (
...@@ -387,7 +387,7 @@ begin ...@@ -387,7 +387,7 @@ begin
--============================================================================ --============================================================================
i2c_addr <= "10" & fpga_ga_i; i2c_addr <= "10" & fpga_ga_i;
cmp_i2c_bridge : vme64x_i2c cmp_i2c_bridge : elma_i2c
port map port map
( (
-- Clock, reset -- Clock, reset
...@@ -563,7 +563,7 @@ begin ...@@ -563,7 +563,7 @@ begin
cmp_ttl_pulse_gen : ctb_pulse_gen cmp_ttl_pulse_gen : ctb_pulse_gen
generic map generic map
( (
g_pulse_width => 125, g_pulse_width => 150,
g_glitch_filt_len => 4 g_glitch_filt_len => 4
) )
port map port map
......
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