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Conv TTL Blocking
Commit 222e55cc authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Basic functionality with immunity to no input channel while in INV-TTL mode and… 

Basic functionality with immunity to no input channel while in INV-TTL mode and documentation update.
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old-ug-conv-ttl-blo.pdf
userGuide.pdf
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@misc{StandardBlocking,
author= "C. Gil Soriano",
title= {{Standard Blocking Output Signal Definition for CTDAH board}},
month= sep,
year= 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
\ No newline at end of file
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\@writefile{toc}{\contentsline {paragraph}{Acknowledgements}{ii}{section*.1}}
\@writefile{toc}{\contentsline {paragraph}{System Description and Purpose}{ii}{section*.2}}
\@writefile{toc}{\contentsline {section}{\numberline {1}General schema}{1}{section.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}CERN Repetitors needs}{1}{subsection.1.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}Front and Rear boards}{1}{subsection.1.2}}
\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces Functional block schema}}{2}{figure.1}}
\@writefile{toc}{\contentsline {section}{\numberline {2}Panels}{3}{section.2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.1}Front Panel: CONT-TTL-BLO}{3}{subsection.2.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.2}Rear Panel: CONV-TTL-RTM-BLO}{3}{subsection.2.2}}
\@writefile{toc}{\contentsline {section}{\numberline {3}Power-up and System Monitoring}{4}{section.3}}
\@writefile{toc}{\contentsline {subsection}{\numberline {3.1}Power Supplies}{4}{subsection.3.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {3.2}Board Temperature}{4}{subsection.3.2}}
\citation{StandardBlocking}
\@writefile{toc}{\contentsline {section}{\numberline {4}FPGA Control and Pulse Converter Unit}{5}{section.4}}
\@writefile{toc}{\contentsline {subsection}{\numberline {4.1}Board ID}{5}{subsection.4.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {4.2}HDL control}{5}{subsection.4.2}}
\citation{StandardBlocking}
\@writefile{toc}{\contentsline {subsection}{\numberline {4.3}Pulse Converter Unit}{6}{subsection.4.3}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.1}Input}{6}{subsubsection.4.3.1}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.2}Output}{6}{subsubsection.4.3.2}}
\@writefile{toc}{\contentsline {section}{\numberline {5}On board memory and FPGA reprogramming}{7}{section.5}}
\@writefile{toc}{\contentsline {section}{\numberline {6}Testing methodologies}{8}{section.6}}
\bibstyle{unsrt}
\bibdata{Functional}
\bibcite{StandardBlocking}{1}
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%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\begin{document}
\title{\textbf{{\LARGE CONV-TTL-BLO\\\textit{Standard Blocking Repeater in
VME64x Format}\\\Large
Functional Specifications}}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{Figures/CERN-Logo.png}
\end{center}
\end{figure}
\begin{abstract}
The present document gathers the functional specifications of the CONV-TTL-BLO
project, EDA-02446.\\
\textbf{History of changes}\\
This document version has been checked by:\\
This document version has been approved by:\\
\begin{center}
\begin{tabular}{|p{3.5cm}|p{2.5cm}|p{5cm}|}
\hline
\textbf{Date} & \textbf{Pages} & \textbf{Changes}\\
\hline
\hline
September 14, 2011 & All & Initial submission.\\
\hline
September 21, 2011 & All & Added references to Standard Blocking.\\
\hline
August 21, 2012 & All & Specifications up-to-date.\\
& & Namings corrected.\\
\hline
\end{tabular}
\end{center}
\end{abstract}
\pagebreak
\pagenumbering{roman}
\maketitle{}
\pagebreak
\setcounter{page}{2}
\pagestyle{empty}
\paragraph{Acknowledgements}
This document agregates the functional specifications of the
TTL, inverted-TTL and Standard Blocking \cite{StandardBlocking} to Standard
Blocking output repeater, \textbf{CONV-TTL-BLO}, for the substitution of the following boards: 8 and 16 Channel Repeaters, Level
Converter and LASB-TTL-BLO.
\paragraph{System Description and Purpose}
The Standard Blocking Pulse Converter is a set of two VME64x boards which has
6 channel repeaters. Each channel repeater is a device able to translate TTL and inverted-TTL signals
into Standard Blocking pulses and regenerate Standard Blocking ones. Differing
from previous versions, a FPGA is included in the Pulse Converter to add control to the
repeater and communication through a serial interface in the VME64x connector.
The aim of this document is setting the specifications needed for the
renovation of these devices due to the difficulties faced when it comes to maintenance and
repairing.
\pagebreak
\setcounter{tocdepth}{3}
\tableofcontents
\pagebreak
\pagenumbering{arabic}
\pagestyle{plain}
\setcounter{page}{1}
\section{General schema}
\subsection{CERN Repetitors needs}
The main goal in the design of the Standard Blocking Repeater is fulfulling the
needs of replacing Blocking Repetitors in CERN. According to the documentation
provided by Emmanuel Said, the following number of repetitors are currently installed at
CERN:\\
\begin{center}
\begin{tabular}{|c|c|}
\hline
\textbf{input} & \textbf{amount}\\
\hline
\hline
\multicolumn{2}{|c|}{\textbf{8 Channel Repeaters}}\\
\hline
TTL & 19\\
\hline
inverted-TTL & 202\\
\hline
Blocking $t_P = 1 \mu{}s $ & 7\\
\hline
Blocking $t_P = 1.2 \mu{}s $ & 141\\
\hline
LA-GATE & 11\\
\hline
\multicolumn{2}{|c|}{\textbf{16 Chanel Repeaters}}\\
\hline
Blocking & 60\\
\hline
\end{tabular}
\end{center}
\subsection{Front and Rear boards}
The Standard Blocking Pulse Converter consists of three boards: CONV-TTL-BLO,
CONV-TTL-RTM and CONV-TTL-RTM-BLO . The decision of splitting up the Pulse
Converter lies in easing substition and repairing of damaged parts and help the
operator in interconnecting the inputs and the outputs.\\
A Pulse Converter can host a maximum of 6 channel repeaters due to the size
limitations of the Rear Panel dimensions.\\
The Front Board, CONV-TTL-BLO is the board that holds the major part of active
components, such as the FPGA and the Pulse Converter Units. This board is
responsible of controlling and monitoring the Pulse Converter activity.\\
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.57, keepaspectratio]{Figures/BLOschema.png}
\caption{Functional block schema}
\end{center}
\end{figure}
\pagebreak
The Rear Board system is composed of a Rear Transistion Module (CONV-TTL-RTM)
which acts as a completely passive motherboard to the mezzanine for the Rear Panel
(CONV-TTL-RTM-BLO) which holds all the inputs and outputs.\\
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\textbf{Board} & \textbf{Location} & \textbf{Parts} &
\textbf{Connectivity}\\
\hline
\hline
\textbf{CONV-TTL-} &&&\\
\textbf{BLO} & FRONT & Active & VME64x Serial Control Lines\\
\hline
\textbf{CONV-TTL-} &&&\\
\textbf{RTM} & REAR & Passive & Motherboard\\
\hline
\textbf{CONV-TTL-} &&&\\
\textbf{RTM-BLO}& ubindexEAR & Passive & Input\textbackslash Output Connectors\\
\hline
\end{tabular}
\end{center}
\section{Panels}
\subsection{Front Panel: CONT-TTL-BLO}
The front board, CONV-TTL-BLO, offers in the Front Panel:
\begin{itemize}
\item Power OK, System Fail LEDs and input signal (TTL or TTL\_N) indicator.
\item An SFP connector to allow precise timestamping via White Rabbit.
\item Three White Rabbit Status LEDs.
\item For every channel: a pulse activity indicator and TTL level input/output
connectors.
\end{itemize}
\subsection{Rear Panel: CONV-TTL-RTM-BLO}
The Rear Board, CONV-TTL-RTM-BLO, offers in the Rear Panel:
\begin{itemize}
\item The Rear Panel must hold six channels. Each channel has four
connectors: one input, three outputs.
\item Every channels has a LED indicator, in the fashion as in the front
panel.
\end{itemize}
\pagebreak
\section{Power-up and System Monitoring}
The System Monitor Unit consists on a HDL core that control critical parts of
both the front and rear boards.
\subsection{Power Supplies}
The power supply domains must be monitored by the FPGA trough a DAC and a
power-up sequence must be specified so as to improve reliability. Reports must
be available through VME64x serial lines.
\subsection{Board Temperature}
The board temperature must be monitored by the FPGA. Reports must
be available through VME64x serial lines.
\pagebreak
\section{FPGA Control and Pulse Converter Unit}
FPGA control will handle all the system logs of the input pulses and parameters
of the output ones: pulse width and time between pulses.
The configuration of this two paramters is important in two aspects:
\begin{description}
\item[Pulse width] Initially the output pulse width is set to 1.2 $\mu$$s$,
following the Standard Blocking definition \cite{StandardBlocking}. Input pulses
wider than 1.2 $\mu$$s$ will be cropped to 1.2 $\mu$$s$ output ones. However, as
different applications could require different pulse width, a configuration
register in the FPGA will be used to add this functionality.\\In electrical
terms, changing the pulse width out of bounds will produce that the current in
the transformer will be higher than the saturation current. In this case,
irreversible damage will be produced. HDL control must take care of this issue.
\item[Time between pulses] Initially the time between pulses is set to
2 $\mu$$s$. Any pulse received within this time frame after a pulse was
outputted will not be regenerated and registered as "Time between pulses violation" in the HDL control.\\It is
important to monitor this parameter because it can produce physical damage to
the transformer. Due to the remaining magnetizing current built up during the
pulse on state, the circuit needs time to draining it off thanks
to a snubber circuit. Subsequently, time between pulses is dependent of the
pulse width and must be set so as to not leave too much remaining current in the
transformer. If the remaining current is not low and input pulses are received
too often, the transformer current can build above the saturation one producing
irreversible damage.
\end{description}
\subsection{Board ID}
A Board ID must be specified to distinguish between different hardware versions
of the Front and Read Board. By reading the value of the board ID, different
approaches can be taken in the HDL control. For instance, if we consider that a
manufacturer is not able to dispatch a 1m$H$ primary inductance transformer so
that it must be replaced for a 470 $\mu$$H$ one, both the \textit{pulse width}
and \textit{time between pulses} parameters must be adapted to this different
part.
\subsection{HDL control}
The FPGA control is governed by a HDL core which must calculate the bounds of
the \textit{pulse width} and \textit{time between pulses} parameters
depending on the Board ID.\\ Then, as previously stated, it must monitor
the \textit{input pulse width} and eventually correct the \textit{time between
pulses} so as to avoid damage to the output pulse transformer due to the
remaining magnetizing current.\\
Furthermore, an event log should be carried out so that it can be reported back
through either serial VME64x P1 lines or front USB connector.
\subsection{Pulse Converter Unit}
The Pulse Converter Unit is the part of the circuit that receives and
adapt the input signal to the FPGA and converts a control signal from the FPGA
to Standard Blocking output -it goes to the Rear Panel- and TTL --it goes to the
Front Panel.
\subsubsection{Input}
TTL, inverter-TTL and Standard Blocking levels must be translated to pass the
signal to the FPGA. \emph{Due to attenuation produced for the long distance
connections made, signals that were outputted as Standard Blocking levels will
be accepted if the received high level is above 10V}. Protection
Circuitry must be used. External line termination should be placed.
\subsubsection{Output}
The output circuity must generate a Standard Blocking signal
\cite{StandardBlocking} compliant:
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\textbf{Pulse Width} & \textbf{Pulse Height} & \textbf{Rise Time} & \textbf{Fall
Time}\\
\hline
1.2 $\mu{}s$ & 24V & 150 $\pm$ 75 $ns$ & 150 $\pm$ 75 $ns$\\
\hline
\end{tabular}
\end{center}
it should be noted that the \textit{Pulse Width} can be configured within the
Standard Blocking pulse width range.
\pagebreak
\section{On board memory and FPGA reprogramming}
A PROM memory must be installed to hold the FPGA bitstream. The size of the PROM
memory should be at least the required to install two uncompressed FPGA
bitstreams.\\
FPGA can be reprogrammed through the external JTAG interface or by means of the
VME64x serial connection.
\pagebreak
\section{Testing methodologies}
The testing process of the FPGA should cover the following areas:
\begin{itemize}
\item Testbench of the HDL power-up related code --power domains, daisy-chain
configuration.
\item Testbench of the HDL control circuit.
\item Verification of the input reflection.
\item Verification of the output pulse shape.
\end{itemize}
\pagebreak
\pagebreak
\bibliographystyle{unsrt}
\bibliography{Functional}
\end{document}
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\ifx\hyper@anchor\@undefined
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\citation{HeinzeReport}
\@writefile{toc}{\contentsline {section}{\numberline {1}Boards and compatibility}{1}{section.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}Repetitors and Blocking Generators}{1}{subsection.1.1}}
\citation{HeinzeLAPF}
\citation{ClaudeDoc}
\citation{CTDACSchematics}
\citation{2222AFairchild}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}Receivers}{2}{subsection.1.2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {1.3}Uses of boards}{2}{subsection.1.3}}
\@writefile{toc}{\contentsline {section}{\numberline {2}Standard Blocking Output Signal Definition}{3}{section.2}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.1}Criteria}{3}{subsection.2.1}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.2}Target use}{3}{subsection.2.2}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.2.1}Repetitor Boards}{3}{subsubsection.2.2.1}}
\bibstyle{unsrt}
\bibdata{BlockingSpecification.bib}
\bibcite{HeinzeReport}{1}
\bibcite{HeinzeLAPF}{2}
\bibcite{ClaudeDoc}{3}
\bibcite{CTDACSchematics}{4}
\bibcite{2222AFairchild}{5}
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@misc{HeinzeReport,
author= "W. Heinze",
title= {{Adapting TTL to Blocking Level with 3U Cards}},
month= nov,
year= 1994,
howpublished = "CERN, PS-CO, Note 94-83",
note = "{\url{https://edms.cern.ch/file/817779/1/TTL_BLO_cards.pdf}}"
}
@misc{HeinzeLAPF,
title= {{LAPF: A TTL to Blocking Converter in Euroformat with Pulse Former}},
howpublished= "CERN, PS-CO",
author= "W. Heinze",
month= mar,
year= 1993,
note = "{\url{https://edms.cern.ch/file/817773/1/LAPF_TTL_BLO_Note.pdf}}"
}
@UNPUBLISHED{ClaudeDoc,
title= {{Distributeur de Timing en Chasis Europe Notice Descriptive}},
note= "CERN, PS-CO-WP, Note 87-028",
author= "C. Dehavay",
month= feb,
year= 1987
}
@misc{CTDACSchematics,
title= {{CTDAC schematics}},
howpublished= "CERN, TS-DEM",
author= "P. Nouchi",
month= may,
year= 2007,
note = "{\url{https://edms.cern.ch/file/842138/1/EDA-01632-V1-0_sch.pdf}}"
}
@misc{2222AFairchild,
title= {{2222A Fairchild Semiconductors Datasheet}},
author= "Fairchild Semiconductors",
month= aug,
year= 2010,
note = "{\url{www.fairchildsemi.com/ds/PN/PN2222A.pdf}}"
}
doc/Blocking/[pulse]BlockingSpecification/BlockingSpecification.tex deleted 100755 → 0
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%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{colortbl}
\begin{document}
\title{\textbf{{\LARGE Standard Blocking Output Signal Definition for CTDAH board}}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{February 23, 2012}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{Figures/CERN-Logo.png}
\end{center}
\end{figure}
\begin{abstract}
The aim of this document is defining the Standard Blocking Output Signal of the Pulse
Converter Unit. This shape is compatible with previous versions, depending
upon its use.\\
\textbf{History of changes}\\
This document version has been checked by:\\
This document version has been approved by:\\
\begin{center}
\begin{tabular}{|p{3cm}|p{1.5cm}|p{5cm}|}
\hline
\textbf{Date} & \textbf{Pages} & \textbf{Changes}\\
\hline
\hline
September 19, 2011& All & Initial submission\\
\hline
September 21, 2011& All& Scope reduced to Standard Blocking Output Signal
definition\\
\hline
\end{tabular}
\end{center}
\end{abstract}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{2}
\pagestyle{empty}
\setcounter{tocdepth}{3}
\tableofcontents
\pagebreak
\pagenumbering{arabic}
\pagestyle{plain}
\setcounter{page}{1}
\section{Boards and compatibility}
\subsection{Repetitors and Blocking Generators}
Five Pulse Conversion boards outputting the so-called ''Blocking'' pulse
are known to be working at CERN. Three of them were reported and studied by W.
Heinze \cite{HeinzeReport}:
\begin{itemize}
\item \textbf{Level Converter -LA boards-}\\
Due to the VAC transformer ZKB 407/115, the output level is 35 V or 18 V
depending on the applied voltage to the A30 pin in the 96 pin DIN connector
--either 24 V for the 35 V output or 12 V for the 18 V one. The length of the
pulse is 1 $\mu{}s$.
\item \textbf{LAPF-TTL-BLO}\\
This board was used to provide 4 $\mu{}s$ pulses to SAC and LAF boards. For
these boards, a longer pulse width is required due to the input low pass
filter applied in SAC and LAF boards to avoid LINAC noisy environment. It uses
the same transformer as Level Converter and the output level is reported to be the same.
\item \textbf{LASB-TTL-BLO}\\
It uses a VAC 409/27 transformer. It outputs a pulse with a high level of
either 23V or 11V depending upon the voltage supplied to the A30 pin in the 96
pin DIN connector --24 V or 12 V, respectivelly.
\end{itemize}
Apart from these three boards, two more are
actually running in CERN facilities: an 8 Channel Repeater and a 16 channel one.
Both Channel Repeater boards use the same subcircuit in every channel to
output the signal. The main differences between them lie in the power supply
they use and the daisy-chain connector included in the 8 channel version. Thanks
to the daisy-channel two boards can copy the same input by means of a short
interconnecting cable.\\
The output level is 24V for the 8 Channel Repeater and
30V for the 16 channel version. This is due to the use of different power
supplies because of different stocks when they were made. The length of the
pulses ranges from 1.2 $\mu{}s$ to 1.4 $\mu{}s$.
The table below summarizes the information of the repetitors systems:
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\textbf{Board} & \textbf{Input Level} & \multicolumn{2}{|c|}{\textbf{Output
Signal}}\\
\hline
&&Level&Pulse width\\
\hline
& TTL & & \\
8 Channel Repeater & inverted-TTL & 24V & [1.2 $\mu${}$s$,
1.4 $\mu${}$s$]\\ & 10V to 30V & & \\
\hline
\hline
& TTL &&\\
16 Channel Repeater & inverted-TTL & 30V & [1.2 $\mu{}s$, 1.4
$\mu{}s$]\\ & 10V to 30V& & \\
\hline
\hline
LASB -TTL-BLO & TTL & 11V or 23V & 1.5 $\mu{}s$\\
& inverted-TTL & & \\
\hline
\hline
LAPF-TTL-BLO & TTL & 18V or 35V&4 $\mu{}s$\\
& inverted-TTL & &\\
\hline
\hline
Level Adapter & TTL & 18V or 35V & 1$\mu{}s$\\
& inverted-TTL & &\\
\hline
\end{tabular}
\end{center}
None of the boards specify the design value of the rise time. Only the trailing
edge is reported for LAPF when the circuit is unloaded \cite{HeinzeLAPF}: 0.3
$ms$. Measurements on both 8 and 16 Channel Repeater show a worst-case rise time
of 100 $\mu{}s$ and a fall time of 400 $\mu{}s$ when the outputs are loaded with
50 $\Omega$.
\subsection{Receivers}
Three boards are reported to be Blocking pulse receivers in CERN facilities:
\begin{itemize}
\item \textbf{LA-BLO-TTL, LAF-BLO-TTL, CTDAC}\\
By reading the schematics \cite{ClaudeDoc} \cite{CTDACSchematics}, an input
threshold detection around 4.5 V can be inferred from the input net consisting of the 10
$K\Omega$, 1.5 $K\Omega$ and the 2N2222A NPN switching transistor --$V_{BE}$
should be around 0.6 V by \cite{2222AFairchild}.\\It is not documented the
reason why this input value threshold is set.
\end{itemize}
\subsection{Uses of boards}
The boards are used as:
\begin{itemize}
\item \textbf{Repetitors}
The 8 and 16 Channel Repeaters, LASB and Level Adapter are used as repetitors.
\item \textbf{Control signal}
LAPF is intended to interface VME SAC/LAF boards.
\end{itemize}
\pagebreak
\section{Standard Blocking Output Signal Definition}
As it was shown in the previous section, a wide variety of output shapes are
running together. One common type of output shape will be defined to set a
reference for the design of the new CTDAH board.\\
\subsection{Criteria}
The criteria employed to define the output shape is as follows:
\begin{center}
\textit{A board designed for a specific use should be backwards compatible with
existing boards so as to avoid interoperability failure.}
\end{center}
\subsection{Target use}
\begin{center}
\textit{Standard Blocking signals are intended to be used in repetitors.}
\end{center}
\begin{tabular}{p{12cm}}
\rowcolor{yellow}{ \textbf{NOTE}: Due to the fact that just a few boards -5
or less- need a LAPF-TTL-BLO-like shaped pulse, the Standard Blocking signal is
not compatible with wide pulses from LAPF-TTL-BLO boards.}
\end{tabular}
\subsubsection{Repetitor Boards}
To comply with previous designs, the definition for this kind of boards,
\textbf{loaded with 50 $\Omega{}$}, is as follows:
\begin{center}
\begin{tabular}{|c|c|c|}
\hline
\textbf{Parameter} & \textbf{Name} &\textbf{Value} \\
\hline
\hline
$v_{i,H}$ & High level & 24V $\pm$ 1V\\
\hline
\hline
$t_{P_{min}}$&\textit{Minimum pulse width} & 1 $\mu{}s$\\
\hline
$t_{P}$&\textit{Typical pulse width} & 1.2 $\mu{}s$\\
\hline
$t_{P_{max}}$&\textit{Maximum pulse width} & 2 $\mu{}s$\\
\hline
\hline
$t_{r}$&\textit{Rise time} & 150 $ns$ $\pm$ 75 $ns$\\
\hline
\hline
$t_{f}$&\textit{Fall time} & 150 $ns$ $\pm$ 75 $ns$\\
\hline
\end{tabular}
\end{center}
\pagebreak
\bibliographystyle{unsrt}
\bibliography{BlockingSpecification.bib}
\end{document}
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\citation{LinvillIREPaper}
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\bibstyle{unsrt}
\bibdata{BlockingGuidelines}
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\bibcite{StantonBook}{2}
\bibcite{MillmanBook}{3}
\bibcite{LinvillBook}{4}
\bibcite{LinvillIREPaper}{5}
\bibcite{McDonaldIEEEPaper}{6}
\bibcite{NormanIEEPaper}{7}
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@ARTICLE{IEEEStandard,
journal={ANSI/IEEE Std 390-1987},
title={{IEEE} Standard for Pulse Transformers},
year={1987},
keywords={IEEE standards;bipolar pulses;blocking oscillators;coupling devices;electronic circuits;positive feedback;pulse transformers;unipolar pulses;equivalent circuits;pulse transformers;standards;testing;},
doi={10.1109/IEEESTD.1987.79640},
}
@book{StantonBook,
title={Pulse technology},
author={Stanton, W.A.},
isbn={9780471820802},
lccn={64017153},
year={1964},
publisher={Wiley}
}
@book{MillmanBook,
title={Pulse, digital, and switching waveforms: devices and circuits for their generation and processing},
author={Millman, J. and Taub, H.},
isbn={9780070855120},
year={1981},
publisher={McGraw-Hill}
}
@book{LinvillBook,
title={Transistors and active circuits},
author={Linvill, J.G. and Gibbons, J.F.},
lccn={60015759},
series={McGraw-Hill electrical and electronic engineering series},
year={1961},
publisher={McGraw-Hill}
}
@ARTICLE{LinvillIREPaper,
author={Linvill, J.G. and Mattson, R.H.},
journal={Proceedings of the IRE}, title={Junction Transistor Blocking Oscillators},
year={1955},
month={nov. },
volume={43},
number={11},
pages={1632 -1639},
keywords={},
doi={10.1109/JRPROC.1955.277989},
ISSN={0096-8390},}
@ARTICLE{KorzekwaIREPaper,
author={ Korzekwa, S.},
journal={Circuit Theory, IRE Transactions on}, title={Transistor Blocking Oscillator Analysis},
year={1961},
month={dec},
volume={8},
number={4},
pages={ 473 - 479},
keywords={ Solid-state circuits;},
doi={10.1109/TCT.1961.1086851},
ISSN={0096-2007},}
@ARTICLE{NormanIEEPaper,
author={Norman, P. and Smith, E.J.E.},
journal={Proceedings of the IEE - Part B: Electronic and Communication Engineering}, title={The design of transistor blocking oscillators},
year={1959},
month={may },
volume={106},
number={18},
pages={1251 -1259},
keywords={oscillators;oscillators;oscillators;},
doi={10.1049/pi-b-2.1959.0229},
ISSN={0369-8890},}
@ARTICLE{McDonaldIEEEPaper,
author={ McDonald, J.},
journal={Circuit Theory, IEEE Transactions on}, title={Circuit Models to Predict Switching Performance of Nanosecond Blocking Oscillators},
year={1964},
month={dec},
volume={11},
number={4},
pages={ 442 - 448},
keywords={},
doi={10.1109/TCT.1964.1082353},
ISSN={0018-9324},}
@misc{StandardBlocking,
author= "C. Gil Soriano",
title= {{Standard Blocking Output Signal Definition for CTDAH board}},
month= sep,
year= 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
\ No newline at end of file
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\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\begin{document}
\title{\textbf{{\LARGE A Triggered Monostable Blocking Oscillator\\\Large Used in
legacy \textit{Channel Repeaters}}}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{August 21, 2012}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{Figures/CERN-Logo.png}
\end{center}
\end{figure}
\begin{abstract}
Along this document, a complete description of the previous generation of
repetitors is offered. It allows the designer to better understand the
requirementes for good interoperability between the different types of
repetitors.\\
\textbf{History of changes}\\
This document version has been checked by:\\
This document version has been approved by:\\
\begin{center}
\begin{tabular}{|p{3cm}|p{1.5cm}|p{5cm}|}
\hline
\textbf{Date} & \textbf{Pages} & \textbf{Changes}\\
\hline
\hline
August 30, 2011 & All & Initial submission\\
\hline
September 21, 2011 & All & Deleted pulse definition chapter.\\
& & Moved to Standard Blocking Definition Document \cite{StandardBlocking}\\
\hline
August 21, 2012 & All & Minor changes in the title page.\\
\hline
\end{tabular}
\end{center}
\end{abstract}
\pagenumbering{roman}
\maketitle{}
\pagebreak
\setcounter{page}{2}
\pagestyle{empty}
\paragraph{System Description and Purpose}
This documents exposes how to design a Monostable Blocking Oscillator used in
old \textit{Channel Repetitor} boards.
A blocking oscillator offers an easy, and low-cost way of obtaining a sharp
pulse of fixed width.\\
By following the instructions given here, an \textit{optimal} Monostable
Blocking Oscillator can be built.
\pagebreak
\setcounter{tocdepth}{3}
\tableofcontents
\pagebreak
\pagenumbering{arabic}
\pagestyle{plain}
\setcounter{page}{1}
\section{Triggered Monostable Blocking Oscillator}
\subsection{References and tips}
A blocking oscillator is usually employed in synchronization applications due to
its simplicity, the little number of elements required -one BJT, a transformer,
few diodes, resistances and capacitors- and the sharp slope of the rising edge it provides. Because of these reasons, a monostable blocking oscillator is selected for the pulse conversion over other possibilities --such as flyback converters, for instance.\\ An intuitive introduction to pulse converters can be found in
\cite{StantonBook}, where the blocking oscillator is sketched pretty
simplisticly. Millman's book, \cite{MillmanBook}, of{}fers an easy and
straightforward view on the pulse top state of the circuit.\\
The more mathematical insight of the switching state is found in Linvill's
classical literature \cite{LinvillBook} and \cite{LinvillIREPaper}, which warns the reader of the aproximations taken out for
the sake of simplicity. It should be noted that, for a proper switching
analysis, some values of the model -such as base resistance- are usually
difficult to find in the datasheet of the manufacturers, and must be inferred
--a Ning-Tang method for the base resistance, i.e. Apart from this, it is a
good advice to carefully checking these values in the SPICE models
provided by the manufacturers. Some manufacturer's base
resistance parameter model corresponds to the intrinsic value of it and not to the intrinsic plus extrinsic one, as it is requiered for a good matching with
the mathematical analysis. This will produce a misleading simulation which will
turn out into an unexpected outcome for the designer. Thus, we encourage not to
give 100\% confidence to the simulation results due to this innacuracies with
respect to the aproximate model used in the analysis.\\ A comprehensive study of the
switching state based on an extension of Linvill's aproximation is done in \cite{McDonaldIEEEPaper}. However, we have considered it as overcomplicated compared to the more reasonable original Linvill's aproximation.\\
Last but not least, Norman's guide for the design of monostable blocking oscillator \cite{NormanIEEPaper} constituted the invaluable help which serves as
the reference of this design.
\subsection{Topologies evaluated}
Three blocking oscillators circuits were considered for the Pulse Converter
Units in CTDAH. The first two are positively collector-emitter feedbacked and
the later has a base-collector feedback.
\begin{description}
\item \textbf{Circuit 1}\\
This circuit can be found in \cite{LinvillIREPaper}. The main drawbacks it
presents lay on the charge it produces the output load and a worse triggering
option compared to Circuit 2.\\
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.3, keepaspectratio]{Figures/LinvillCircuit.png}
\caption{Linvill's circuit, taken from \cite{LinvillIREPaper}}
\end{center}
\end{figure}
\item \textbf{Circuit 2}\\
It is the circuit chosen for the design. With the inclusion of a resistance in
the positive feedback loop it is really simple to accomodate the pulse width
to the designer needs.
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{Figures/NormanCircuit.png}
\caption{Norman's circuit, taken from \cite{NormanIEEPaper}}
\end{center}
\end{figure}
\item \textbf{Circuit 3}\\
However it is the most intuitive among all the designs, the triggering is not
as independent from the input as Circuit 2.
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{Figures/MillmanCircuit.png}
\caption{Millman's circuit, taken from \cite{MillmanBook}}
\end{center}
\end{figure}
\end{description}
\subsection{Analysis of the chosen topology}
The analysis follows the flow pointed out in \cite{NormanIEEPaper}. The complete
mathematical resolution of the switching state from \cite{LinvillBook} is
included. Furthermore, the fixed-point methond algorithm is added to clarify
how the normalized natural frequency of the circuit is gotten.
\\
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.6, keepaspectratio]{Figures/blockingStates.png}
\caption{States and equivalent circuits}
\end{center}
\end{figure}
\vspace{-20pt}
\subsubsection{Switching on}
When it is switching both on and of{}f, an equivalent circuit is shown in
the figure below. Emitter resistance and capacitance are omitted for
simplicity.
The critical value while switching lies on obtaining the \textit{natural
frequency} of the circuit. This value is closely related with the
\textit{transformer turns-ratio} and, given the aproximations of the model, an
optimun turns-ratio can be calculated. If this turns-ratio is used, the fastest
rise time will be achived an no ringing will be obtained, ideally.
\\
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.3, keepaspectratio]{Figures/swCircuit.png}
\caption{Eq. circuit B: switching}
\end{center}
\end{figure}
\vspace{-20pt}
\begin{description}
\item \textbf{Kirchoff's equations}\\
The electrical relationship of the circuit are:
\begin{equation}
\frac{E_1}{R_L} + I_E - ni_L = 0
\end{equation}
\begin{equation}
\frac{E_1}{r_b} + \frac{I_E}{1+\frac{s}{w_o}} - I_E - (n-1)E_1C_ss = 0
\end{equation}
\begin{equation}
i_L - \frac{I_E}{1 + \frac{s}{w_o}} + (n-1)E_1C_ss = 0
\end{equation}
\item \textbf{Fundamental equation}\\
Operating the previous equations yields:
\begin{equation}
(\frac{s}{w_0})^2 + \frac{s}{w_0}\cdot\frac{G_L + g_b}{(n-1)^2 C_c w_0} -
\frac{g_b}{C_c w_0 (n-1)} = 0
\end{equation}
That can be greatly simplified by normalizing the natural frequency and
performing the following changes of variable:
\begin{equation}
x=\frac{s}{w_0} \hspace{25pt} n-1 = \Delta \hspace{25pt} \frac{g_b}{C_c w_0} = k
\hspace{25pt} \frac{g_b + G_L}{C_c w_0} = k
\end{equation}
\begin{equation}
x^2+x(1+\frac{l}{\Delta^2})-\frac{k}{\Delta} = 0
\end{equation}
However, as $\Delta$ is a design parameter we can rewrite the equation to:
\begin{equation}
\Delta^2(x^2+x) - k\Delta + xl = 0
\end{equation}
If a value of the normalized natural frequency of the circuit, $x$, is lower
than $x_{max}$ two possible optimal \textit{turns-ratios} will exist. If it is
higher than $x_{max}$ no real \textit{turns-ratios} exist. We can find an
optimal value of $\Delta$ that corresponds to $x_{max}$, by obtaining a double
root of the previous equation. Hence:
\begin{equation}
k^2 - 4(x_{max}^3 + x_{max}^2)l = 0
\end{equation}
We can get the \textit{normalized natural frequency} by applying
iterations by a fixed-point method, given that it converges --because we expect
a value close to 1
\begin{equation}
x_{max_i} = \frac{k}{2\sqrt{l(x_{max_{i-1}} +1 )}} \hspace{25pt} i = 1,2,3\ldots
\end{equation}
\item \textbf{Results}\\
The expected \textit{rise-time} is:
\begin{equation}
t_{rise}=\frac{2.3}{x_{max}w_0}
\end{equation}
for an optimal \textit{turns-ratio} is:
\begin{equation}
\Delta_{opt} = \frac{k}{2(x_{max}^2+x_{max})} \hspace{25pt} n_{opt} =
\Delta_{opt} +1
\end{equation}
Subsequently, getting a good rise-time depends mainly on choosing the optimal
\textit{turns-ratio} value and using a fast switching bipolar transistor in the
design.\\
\textbf{TIP}: as stated in \cite{NormanIEEPaper}, the triggering signal must be
active for $3t_{rise}$, so as to effectively switching the cirucit state.
\end{description}
\subsubsection{On state}
The on-state is related with the value of the \textit{magnetizing inductance} in
the collector and the \textit{positive feedback resistor}. With this two parameters
the designer is able to chose the \textit{pulse width}.
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.33, keepaspectratio]{Figures/ONstate}
\caption{Eq. circuit A: on-state}
\end{center}
\end{figure}
\begin{description}
\item \textbf{Kirchoff's equations}\\
From the collector we can get the following equation:
\begin{equation}
i_c = \frac{V_p}{n^2(R_L+r_{EBt})} + \frac{V_p}{n^2R_L} + \frac{V_pt}{L}
\end{equation}
During the on-state we can define $h_{FB_t} = \frac{i_c}{i_E}$, thus the
previous equations can be rewritten as:
\begin{equation}
\frac{V_ph_{FB_t}}{n(R_L + r_{EBt})} = \frac{V_p}{n^2(R_L + r_{EBt})} +
\frac{V_p}{n^2R_L} +
\frac{V_pt}{L}
\end{equation}
\item \textbf{Results}\\
When the transistor is close to leave its saturation state, we can change all
its parameters for the large signal model ones. This yields to obtaining the
\textit{width} of the pulse:
\begin{equation}
T_p = \frac{L (h_{FB} - 1)}{n^2[R_E + r_E + (1+h_{FB}r_B)]} - \frac{L}{n^2R_L}
\end{equation}
As it is noted in \cite{NormanIEEPaper}, adding $R_E$ helps to desensitizing
the circuit from $r_E$
\end{description}
\subsubsection{Switch of{}f}
The switch-of{}f state is governed by the same equations of the switch-on state.
\subsubsection{Of{}f state: \textit{Recovery time}}
Of{}f-state is reached when the circuit completely removes all the current from
the \textit{magnetizing inductor} through the snubber consisting of the
\textit{diode} and \textit{discharge resistor}. Once the current is completely
removed, a new triggering can be faced by the monostable oscillator.
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.33, keepaspectratio]{Figures/OFFstate}
\caption{Eq. circuit C: of{}f-state}
\end{center}
\end{figure}
\begin{description}
\item \textbf{Kirchoff's equations}\\
At the end of the on state, the magnetizing current is:
\begin{equation}
I_L = \frac{V_PT_P}{L}
\end{equation}
The magnetizing inductance current must equal the current flowing out of the two
multipoles formed by the diode and the resistor and the diode and the zenner diode. The multipole consisting of the diode and the resistor helps to avoid
overdamping while switching off. In the second case, the current decreases
linearly until the diode acts as an open circuit. From this time on, the only
multipole draining current from the inductor is the one with the resistor. The
discharge equation is:
\begin{equation}
i_L = \frac{V_2}{R_c}[1+ \frac{R_c}{L}(t-t_3)]e^{-\frac{t-t_3}{L/(2R_c)}}
\hspace{25pt} t\geq{t_3}
\end{equation}
The critical damping happens with a snubber resistor value of:
\begin{equation}
R_{c} = \frac{1}{2} \sqrt{\frac{L}{C_s}}
\end{equation}
where $C_s$ is the \textbf{shunt capacitance} formed by the addition of the
\textit{collector capacitance of the bipolar transistor}, the
\textit{transformer self capacitance} and the \textit{wiring capacitance}.\\The
resistance of $R_{snubber}$ should be less than $R_c$, so as to avoid overdamping:
\begin{equation}
R_{snubber} < R_c
\end{equation}
\item \textbf{Implicit equation}\\
The residual current in the inductance, $I_R$, will be:
\begin{equation}
I_R = \frac{V_2}{R_c}[1+ \frac{R_c}{L}(t_4-t_3)]e^{-\frac{t_4-t_3}{L/(2R_c)}}
\hspace{25pt} t=t_4
\end{equation}
that cannot be resolved, but it is bounded by:
\begin{equation}
I_R < \frac{V_2}{R_{snubber}}e^{-\frac{t_4-t_3}{L/R_{snubber}}}
\end{equation}
Thus, operating along the two recovery stages as in \cite{NormanIEEPaper}:
\begin{equation}
T_R = \frac{V_1T_p}{V_2} + \frac{L}{R_{snubber}}(log{\frac{V_2}{R_{snubber}I_R}-1)}
\end{equation}
\item \textbf{Results}\\
First, we must set a threshold for $I_R$.\\
Then, the resistance of $R_{snubber}$ that makes $T_{R_{min}}$ is:
\begin{equation}
R_{snubber} = \frac{V_2}{I_R}
\end{equation}
but must comply with:
\begin{equation}
R_{snubber} < R_{c}
\end{equation}
for avoid overdamping.
\end{description}
\pagebreak
\bibliographystyle{unsrt}
\bibliography{BlockingGuidelines}
\end{document}
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doc/HDL/specifications/HDLSpecifications.tex deleted 100755 → 0
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%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\begin{document}
\title{CONV-TTL-BLO HDL specifications}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
\maketitle
\begin{abstract}
This document tackles with:
\begin{itemize}
\item HDL development priorities
\item Memory mapping
\end{itemize}
\end{abstract}
\\
\tableofcontents
\pagebreak
\section{HDL schema}
The following schema is used as a reference for the HDL development:\\
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.3, keepaspectratio]{Figures/HDLspecs.png}
\caption{CONV-TTL-BLO HDL structure}
\end{center}
\end{figure}
\subsection{Control}
It is the part that bridges the I2C frames to the correct wishbone module. The
tasks it is responsible of are:
\begin{itemize}
\item Correctly power-up the rest of the modules.
\item Provide connectivity of all the wishbone registers via
I2C. It manages control access to the registers.
\end{itemize}
\subsection{I2C slave}
An I2C slave is needed to receive the frames from the VME64x SERA and SERB pins
in P1 connector. This module will communicates with \textit{control hdl module}
in the following fashion:
\begin{itemize}
\item It connects as a wishbone \textbf{slave} to control hdl core and
provides interrupt lines for data reception and transmission.
\end{itemize}
The main reason of implementing a wishbone slave is that by dividing data
reception -\textit{i2c slave}- from control access -\textit{control}- the
development is more reliable and clear.\\ This module offers configuration
registers to ease the task of data assembly --for instance, the communication
schema in ELMA crate.
\subsection{Trigger}
The trigger manages the pulse repetition. The parameters handled that affect the
pulse repetition are:
\begin{itemize}
\item \textbf{Debouncing} stages of the input pulse.
\item \textbf{Pulse length} of the output pulse according to Standard
Blocking definition.
\item \textbf{Minimun spacing between pulses} to let the magnetizing current
of the transformer be drained off. It is also refered in other documents as
\textit{Inactivity timeout upon output pulse is outputted}.
\end{itemize}
The pulses must be time-tagged. It can be achieved either by a
lossy time-tagging via i2c, or with a precise one via White Rabbit. Every
time-tag has appended event identifiers (metadata).
\subsubsection{Time-tagging Format}
The format of the time-tags should be defined. At this moment, an implementation
with 96 bits for timestamping with 32 bits of metadata is the default. A record
of the last 256 time-tags per channel is hold in the FPGA.
\subsection{Multiboot manager}
The task of the \textit{Multiboot manager} is to manage a golden bitstream and
another one to update the FPGA from. From within this module a FPGA
reprogramming command is issued.
\subsection{EEPROM manager}
The module responsible to write into the EEPROM, read it back and reprogramming
the memory module. It should be targeted to interface directly with a MICRON
M25P32-VMF6P memory. It will be able to write the MAC address that will be used
by White Rabbit and block memory parts of the EEPROM.
\subsection{White Rabbit core}
Provides precise timestamping.
\pagebreak
\section{HDL development milestones}
The HDL development is scheduled to tackle with several milestones:
\begin{enumerate}
\item \textit{i2c slave} module: verification
\item \textit{Control} module: reset the rest of HDL cores. Bypassing
i2c instrucctions to wishbone interface.
\item \textit{Multiboot manager} module: multiboot between different
precharged bitstreams.
\item \textit{EEPROM manager} module: write a bitstream through the i2c interface.
\item Integration of White Rabbit core: fine timestamping
\end{enumerate}
\section{Wishbone memory map}
So as to access the devices thanks to \textit{CTDAH control} the
following memory map is proposed:
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
&& \textbf{FIRST} & \textbf{LAST}\\
\textbf{NUMBER}&\textbf{DEVICE} & \textbf{WISHBONE} & \textbf{WISHBONE}\\
&& \textbf{ADDRESS} & \textbf{ADDRESS}\\
\hline
\hline
0 & Control & 0x0100 & 0x01FF \\
\hline
1 & I2C slave & 0x0200 & 0x02FF \\
\hline
2 & Trigger 1 & 0x0300 & 0x03FF \\
\hline
3 & Trigger 2 & 0x0400 & 0x04FF \\
\hline
4 & Trigger 3 & 0x0500 & 0x05FF \\
\hline
5 & Trigger 4 & 0x0600 & 0x06FF \\
\hline
6 & Trigger 5 & 0x0700 & 0x07FF \\
\hline
7 & Trigger 6 & 0x0800 & 0x08FF \\
\hline
8 & Multiboot manager & 0x0900 & 0x09FF \\
\hline
9 & EEPROM manager & 0x0A00 & 0x0AFF \\
\hline
10 & White Rabbit core & 0x0B00 & 0x0BFF \\
\hline
\hline
11 & EEPROM memory & 0x1000 & 0x1FFF \\
\hline
\end{tabular}
\end{center}
%\section{HDL modules}
%\subsection{i2c slave}
%w\subsection{trigger}
%$\section{Functional specifications}
%CTDAH board holds the logic that controls pulse conversion and forwarding.
%Three input and output signal levels can be handled: TTL, inverted-TTL and
%%Standard Blocking.
%The behaviour of the HDL is as follows:
%\begin{itemize}
% \item Everytime an input pulse is detected, the pulse is converted to the
% output level and time-tagged. Glitches are not forwarded.
% \item The input events are detected and logged.
% \item CTDAH communicates with a monitor board via I$^2$C through VME64x
% connector. The monitor board can set CTDAH control parameters, receive
% notifications from it, report problems affecting the backplane and reprogram
% CTDAH FPGA.
%\end{itemize}
%
%A block diagram for the HDL core is shown below:\\
%
%\begin{figure}[htb]
% \begin{center}
% \includegraphics[scale=1, keepaspectratio]{BlockDiagram.png}
% \caption{CTDAH HDL structure}
% \end{center}
%\end{figure}
%
%
%
%\pagebreak
%\section{Technical specifications}
%
%
%
%\subsection{Memory mapping}
%
%
%\subsection{Time tagger register}
%Each time an input event is detected, it is time-tagged in the internal FPGA
%memory.\\
%A time-tag consist of six words. The first two words form the PULSE\_ID field
%and the later four ones, the UTC time-tag:
%
%\begin{center}
%\begin{tabular}{|c|c|}
%\hline
%0 & PULSE\_ID_U\\
%\hline
%1 & PULSE\_ID_L\\
%\hline
%2 & UTC_{UU}\\
%\hline
%3 & UTC_{UL}\\
%\hline
%4 & UTC_{LU}\\
%\hline
%5 & UTC_{LL}\\
%\hline
%\end{tabular}
%\end{center}
%\subsubsection{PULSE\_ID field}
%The PULSE\_ID$_L$ contains the length of the output pulse, in clock cycles. The
%PULSE\_ID$_U$ field is defined as follows:
%\begin{center}
%\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|}
%\hline
%15 & 14 & 13 & 12 & 11 & 10 & 9 & 8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
%\hline
%& & & & & & \tiny{OM1} & \tiny{OM0} & & & & \tiny{IOK} & \tiny{IFL} &
%\tiny{IFS} & \tiny{IM1} &\tiny{IM0}\\
%\hline
%\end{tabular}
%\end{center}
%\\
%\subsubsection{UTC field}
\end{document}
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doc/HDLguide/HDLguide.bib deleted 100755 → 0
View file @ 224a9757
@TECHREPORT{UG380,
institution= "Xilinx Inc.",
title= {{Spartan-6 FPGA Configuration User Guide}},
month= jul,
year= 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
\ No newline at end of file
doc/HDLguide/HDLguide.tex deleted 100755 → 0
View file @ 224a9757
%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{draftwatermark}
\SetWatermarkLightness{0.85}
\SetWatermarkScale{5}
\begin{document}
\title{\textbf{CONV-TTL-BLO \\ User Guide}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
\maketitle
\begin{abstract}
This \textit{User's Guide} covers the following topics:
\begin{itemize}
\item HDL global structure.
\item Golden image memory mapping.
\item Register mapping of all the HDL cores.
\item Instructions for accesing to the functionalities.
\end{itemize}
\end{abstract}
\pagebreak
\tableofcontents
\pagebreak
\section{HDL global structure}
The following schema is used as a reference for the HDL development:\\
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.3, keepaspectratio]{Figures/HDLspecs.png}
\caption{CONV-TTL-BLO HDL structure}
\end{center}
\end{figure}
\subsection{Control}
It is the part that bridges the I2C frames to the correct wishbone module. The
tasks it is responsible of are:
\begin{itemize}
\item Correctly power-up the rest of the modules.
\item Provide connectivity of all the wishbone registers via
I2C. It manages control access to the registers.
\end{itemize}
\subsection{I2C slave}
An I2C slave is needed to receive the frames from the VME64x SERA and SERB pins
in P1 connector. This module will communicates with \textit{control hdl module}
in the following fashion:
\begin{itemize}
\item It connects as a wishbone \textbf{slave} to control hdl core and
provides interrupt lines for data reception and transmission.
\end{itemize}
The main reason of implementing a wishbone slave is that by dividing data
reception -\textit{i2c slave}- from control access -\textit{control}- the
development is more reliable and clear.\\ This module offers configuration
registers to ease the task of data assembly --for instance, the communication
schema in ELMA crate.
\subsection{Trigger}
The trigger manages the pulse repetition. The parameters handled that affect the
pulse repetition are:
\begin{itemize}
\item \textbf{Debouncing} stages of the input pulse.
\item \textbf{Pulse length} of the output pulse according to Standard
Blocking definition.
\item \textbf{Minimun spacing between pulses} to let the magnetizing current
of the transformer be drained off. It is also refered in other documents as
\textit{Inactivity timeout upon output pulse is outputted}.
\end{itemize}
The pulses must be time-tagged. It can be achieved either by a
lossy time-tagging via i2c, or with a precise one via White Rabbit. Every
time-tag has appended event identifiers (metadata).
\subsubsection{Time-tagging Format}
The format of the time-tags should be defined. At this moment, an implementation
with 96 bits for timestamping with 32 bits of metadata is the default. A record
of the last 256 time-tags per channel is hold in the FPGA.
\subsection{Multiboot manager}
The task of the \textit{Multiboot manager} is to manage a golden bitstream
and another one to update the FPGA from. From within this module a FPGA
reprogramming command is issued.
\subsection{EEPROM manager}
The module responsible to write into the EEPROM, read it back and reprogramming
the memory module. It should be targeted to interface directly with a MICRON
M25P32-VMF6P memory. It will be able to write the MAC address that will be used
by White Rabbit and block memory parts of the EEPROM.
\subsection{White Rabbit core}
Provides precise timestamping.
\pagebreak
\section{Golden image memory mapping}
To access the devices thanks to \textit{control module} the
following memory map applies:
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
&& \textbf{FIRST} & \textbf{LAST}\\
\textbf{NUMBER}&\textbf{DEVICE} & \textbf{WISHBONE} & \textbf{WISHBONE}\\
&& \textbf{ADDRESS} & \textbf{ADDRESS}\\
\hline
\hline
0 & \hyperref[sec:control]{Control} & 0x0100 & 0x01FF \\
\hline
1 & \hyperref[sec:I2C]{I2C slave} & 0x0200 & 0x02FF \\
\hline
2 & \hyperref[sec:trigger]{Trigger 1} & 0x0300 & 0x03FF \\
\hline
3 & \hyperref[sec:trigger]{Trigger 2} & 0x0400 & 0x04FF \\
\hline
4 & \hyperref[sec:trigger]{Trigger 3} & 0x0500 & 0x05FF \\
\hline
5 & \hyperref[sec:trigger]{Trigger 4} & 0x0600 & 0x06FF \\
\hline
6 & \hyperref[sec:trigger]{Trigger 5} & 0x0700 & 0x07FF \\
\hline
7 & \hyperref[sec:trigger]{Trigger 6} & 0x0800 & 0x08FF \\
\hline
8 & \hyperref[sec:multiboot]{Multiboot manager} & 0x0900 & 0x09FF \\
\hline
9 & \hyperref[sec:EEPROM]{EEPROM manager} & 0x0A00 & 0x0AFF \\
\hline
10 & White Rabbit core & 0x0B00 & 0x0BFF \\
\hline
\hline
11 & EEPROM memory & 0x1000 & 0x1FFF \\
\hline
\end{tabular}
\end{center}
\pagebreak
\section{Control module}
\label{sec:control}
\pagebreak
\section{I2C slave module}
\label{sec:I2C}
\subsection{Structure}
The i2c module contains several blocks related the following way:\\
-- i2c\_slave\_top.vhd
----- i2c\_regs.vhd
----- i2c\_slave\_core.vhd
--------- FIFO\_dispatcher.vhd
--------- FIFO\_stack.vhd
--------- gc\_counter.vhd
--------- gc\_ff.vhd
--------- i2c\_bit.vhd
\subsection{Interrupting lines offered}
\subsubsection{ind\_wb\_addr}
This interrupting signal issues when a \textit{indirect wishbone address} has
been received. It is notified right after the first CTR0[BIA] + 1 bytes upon the
reception of the I2C byte address packet.
This signal is vital for correctly prefetching when a I2C read operation is
requested.
\subsubsection{inst\_rd}
This signal is issued when a read operation directed by an external master over
the HDL slave core is finished. That means it will be generated after the last
data byte has been sent by the HDL core.
\subsubsection{inst\_wr}
This signal is issued when a write operation directed by an external master over
the HDL slave core is finished. That means it will be generated after the last
data byte has been received.
\subsection{Registers}
\subsubsection{STA}
The STA register is a read-only register. It control the general enable and
reset of the module. It also contains the current value of the finite state
machine of the i2c modue (useful for easy debugging).\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & General ENable\\
\hline
1 & RST & General ReSeT\\
\hline
2 & RD\_WRN\_INST & Reserved\\
\hline
3 & A\_RX &\\
\hline
4 & A\_TX &\\
\hline
8-5 & x & Reserved\\
\hline
15-9 & i2c\_sla\_fsm & i2c fsm\\
\hline
31-16 & Not used\\
\hline
\end{tabular}
\subsubsection{PRE}
The PRE register is a write-read register. Right now it is not used.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & PRE & PREscaler value\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}
\subsubsection{CTR0}
The CTR0 register is a write-read register. It controls the indirect addres
and holds the I2C address (which in the case of \textit{CONV-TTL-BLO} will be
connected to VME64x geographical address pins).\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & general ENable\\
\hline
1 & RST & general ReSeT\\
\hline
2 & PEN & Prescaler ENable\\
\hline
5-3 & x & Reserved\\
\hline
7-6 & BIA & Bytes Indirect Addressing\\
\hline
14-8 & A[6:0] & I2C address\\
\hline
15 & x & Reserved\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}
\subsubsection{CTR1}
The CTR1 register is a write-read register. It shows the fsm of the separate
\textit{read} and \textit{write} fsms.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & RDS & fsm status: ReaD Status\\
\hline
15-8 & WDS & fsm status: WRite Status\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}
\subsubsection{DRXA}
The DRXA register is a read-only register. It holds the last four received
bytes through the I2C. DRX0 has the most recent byte received from the serial
interface. DRX3 has the oldest byte received.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & DRX0 & Data RX register 0\\
\hline
15-8 & DRX1 & Data RX register 1\\
\hline
23-16 & DRX2 & Data RX register 2\\
\hline
31-24 & DRX3 & Data RX register 3\\
\hline
\end{tabular}
\subsubsection{DRXB}
The DRXB register is a read-only register. It holds the fifth and sixth latest
received bytes, respectively.
\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & DRX4 & Data RX register 0\\
\hline
15-8 & DRX5 & Data RX register 1\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}
\subsubsection{DTX}
The DTX register is a write-read register. It shows the fsm of the separate
\textit{read} and \textit{write} fsms.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & RDS & fsm status: ReaD Status\\
\hline
15-8 & WDS & fsm status: WRite Status\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}
\subsection{Internal Memory Mapping}
The internal registers map is as follow:\\
\begin{tabular}{| c | c | c |}
\hline
\textbf{Address} & \textbf{Register} & \textbf{Access} \\
\hline
\hline
\textbf{0x0} & \textit{STA} & Read-only\\
\hline
\textbf{0x1} & \textit{PRE} & Write-read\\
\hline
\textbf{0x2} & \textit{CTR0} & Write-read\\
\hline
\textbf{0x3} & \textit{CTR1} & Write-read\\
\hline
\textbf{0x4} & \textit{DRXA} & Read-only\\
\hline
\textbf{0x5} & \textit{DRXB} & Read-only\\
\hline
\textbf{0x6} & \textit{DTX} & Write-read\\
\hline
\end{tabular}
\subsection{How to use it}
\subsubsection{Initialization}
\begin{enumerate}
\item Perform a reset of the module while module is not enabled:\\
\textit{CTR0: write 0 to EN and 1 to RST.}
\item Load the prescaler:\\
\textit{PRE: set a new value.}
\item Set the I2C address of the slave module:\\
\textit{CTR0[A]: set the I2C address.}
\item Set the rest of bits of CTR0, including EN:\\
\textit{CTR0: set rest of bits.}
\end{enumerate}
\subsubsection{Indirect Write from Master to Slave}
It is a one-phase transaction: one indirect writing is achieved
by signaling only one I2C start condition by the master.
\begin{enumerate}
\item The Master I2C device starts an I2C transaction. In the first byte it
specifies the type of transaction issued as a write.
\item Then, two bytes are received in the slave. At the end of the reception
of the last bit of this second byte (third since the I2C start condition), the
finite state machine in \textit{i2c\_slave\_core.vhd} launches the interrupt
\textit{inst\_wb\_addr}.
\textbf{Address prefetching}: at this point, the Wishbone Address can be
stored.
It is found in \textit{DRX0} and \textit{DRX1} registers:
\begin{itemize}
\item \textit{DRX0}: holds the Wishbone Address Lowest Byte
\item \textit{DRX1}: holds the Wishbone Address Highest Byte
\end{itemize}
\item Following the reception of the two bytes corresponding to the Wishbone
Address, four more bytes will be received. They are the data bytes. Once the
last bit of this fourth byte is received (seventh byte since the I2C start
condition), the finite state machine in \textit{i2c\_slave\_core.vhd} launches
the interrupt \textit{inst\_wr}.
\textbf{Address and Data fetching}: at this point, the \textit{Wishbone
Address} and the \textit{Data} to be written in that address can be both
fetched through the \textit{DRX} registers:
\begin{itemize}
\item \textit{DRX0}: holds the Data Lowest Byte
\item \textit{DRX1}: holds the Data 2$^{nd}$ Lowest Byte
\item \textit{DRX2}: holds the Data 2$^{nd}$ Highest Byte
\item \textit{DRX3}: holds the Data Highest Byte
\item \textit{DRX4}: holds the Wishbone Address Lowest Byte
\item \textit{DRX5}: holds the Wishbone Address Highest Byte
\end{itemize}
\item The Master I2C device stops the I2C transaction.
\end{enumerate}
\subsubsection{Indirect Read from Master to Slave}
It is a two-phases transaction: one indirect read is achieved
by signaling only two I2C start conditions by the master.\\
\textbf{FIRST PHASE}
\begin{enumerate}
\item The Master I2C device starts an I2C transaction. In the first byte it
specifies the type of transaction issued as a write.
\item Then, two bytes are received in the slave. At the end of the reception
of the last bit of this second byte (third since the I2C start condition), the
finite state machine in \textit{i2c\_slave\_core.vhd} launches the interrupt
\textit{inst\_wb\_addr}.
\textbf{Address Prefetching}: at this point, the Wishbone Address can be
stored.
It is found in \textit{DRX0} and \textit{DRX1} registers:
\begin{itemize}
\item \textit{DRX0}: holds the Wishbone Address Lowest Byte
\item \textit{DRX1}: holds the Wishbone Address Highest Byte
\end{itemize}
\textbf{Data Prefetching}: it is a good practice to do the \textit{data
prefetching} of the Wishbone Address (in case this is accessible). The control
logic attached to the \textit{i2c\_slave\_wb} module should perform a
wishbone write to the four \textit{DTX[X]} registers:
\begin{itemize}
\item \textit{DTX0}: holds the Data Lowest Byte
\item \textit{DTX1}: holds the Data 2$^{nd}$ Lowest Byte
\item \textit{DTX2}: holds the Data 2$^{nd}$ Highest Byte
\item \textit{DTX3}: holds the Data Highest Byte
\end{itemize}
so that the data in the transmission registers is up-to-date, in order to be
sent through I2C.
\end{enumerate}\\
\pagebreak
\textbf{SECOND PHASE}
\begin{enumerate}
\item The Master I2C device (re)starts an I2C transaction. In the first byte
it specifies the type of transaction issued as a read. At the end of the
reception of the last bit on the first byte of this \textit{second phase}
(third byte sinc the I2C start condition from the \textit{first phase}), the
finite state machine in \textit{i2c\_slave\_core.vhd} launches the interrupt
\textit{inst\_wb\_addr}.
\item The \textit{i2c\_slave\_wb} module sends the four data bytes in the
following order:
\begin{enumerate}
\item Data Lowest Byte
\item Data 2$^{nd}$ Lowest Byte
\item Data 2$^{nd}$ Highest Byte
\item Data Highest Byte
\end{enumerate}
\item Once the last byte has been already send, the finite state machine in
\textit{i2c\_slave\_core.vhd} launches the interrupt \textit{inst\_rd\_addr}.
\end{enumerate}
\pagebreak
\section{Trigger module}
\label{sec:trigger}
\subsection{Structure}
The trigger module contains several blocks related the following way:\\
-- \textbf{\textit{trigger\_top.vhd}}
----- \textbf{trigger\_regs.vhd}
----- \textbf{trigger\_core.vhd}
--------- debouncer.vhd
--------- monostable.vhd
----- \textbf{TT\_RAMhandler.vhd}
--------- gc\_RAM.vhd (for IDs)
--------- gc\_RAM.vhd (for TTs)
\subsubsection{\textit{trigger\_top.vhd}}
The top module interconnects the three basic building blocks: registers, core
and generic RAM. Each \textit{trigger\_top.vhd} module will control
one output Blocking driver.
Inside \textit{trigger\_top.vhd} there are some constant that are used as
\textit{generic} in both the registers and generic RAMs. The constants are
explained later in the section 'Parameters' and are the following:
\begin{itemize}
\item \textit{c\_RAM\_SIZE }
\item \textit{c\_MAX\_GLITCH\_STAGES }
\item \textit{c\_DEFAULT\_GLITCH\_MASK }
\item \textit{c\_MIN\_PULSE\_LENGTH }
\item \textit{c\_MAX\_PULSE\_LENGTH }
\item \textit{c\_DEFAULT\_PULSE\_LENGTH }
\item \textit{c\_TAGS\_DATA\_WIDTH }
\end{itemize}
\subsubsection{trigger\_regs.vhd}\\
It consist of a core that can be accessed via Wishbone and that contains all the
registers which control this trigger core. The minimum and maximum values and
proceeding for configuring them will be explained in the two next following
sections.
\subsubsection{TT\_RAMhandler.vhd}\\
The TT\_RAMhandler is the component that control reads and writes into the RAM
space used for time-tagging pulses. It is subdivided into two separated blocks
of RAM: one for identification of the input and output pulse shape (so called
''ID Block'') and the other one for time-tagging (''TT Block'').
The idea behind seperating the block memories lies in ease the task of updating
the code in case different widths for the ID and TT fields are decided.
\item[]
\subsection{Behaviour}
Once a pulse has been deglitched, which translates into a delay of
\textit{wb\_clk * cycles to match c\_DEFAULT\_GLITCH\_MASK }, a monostable
will reproduce a pulse with a length determined by the CPL field in CTR0
register. The duration of the output pulse will be hence, \textit{CTR0[CPL] *
wb\_clk}. After this time, a preventive action has been taken to not damage the
coupled inductors in \textbf{CONV-TTL-BLO}. A timeout will be run in which no
input pulse will be replicated. The value of this timeout corresponds to
\textit{CTR0[CPL] * wb\_clk}, which is the same as the outputted pulse.
\begin{description}
\item[Min. Deglitch Mask delay] \textit{wb\_clk * 1}
\item[Max. Deglitch Mask delay] \textit{wb\_clk * bits of
c\_DEFAULT\_GLITCH\_MASK }
\item[Min. input pulse length] \textit{c\_DEFAULT\_GLITCH\_MASK * wb\_clk}
\item[Output pulse length] \textit{CTR0[CPL] * wb\_clk}
\item[Inactivity timeout upon output pulse is done] \textit{CTR0[CPL] * wb\_clk}
\end{description}
\subsection{Parameters}
\subsubsection{ \textit{g\_MAX\_GLITCH\_STAGES} }
It specifies the maximum stages used for debouncing an input signal. The input
signal is validated by bit 0 in CTR0. If CRT0[0] is set to 0. Inputs won't be
replicated (it won't even be deglitched).
The value of this parameters express the length in bits of the parameter that
holds the deglitching mask. The value of the Current deGlitching Mask can be
found in CGM in CTR0 register.
\subsubsection{ \textit{g\_DEFAULT\_GLITCH\_MASK} }
It specifies the default value that it is used for the Current deGlitching Mask
for the CGM field in CTR0 register. Only the lower CGM bits specified by the
values of \textit{g\_MAX\_GLITCH\_STAGES} will be used as deglitching mask. It
should be remarked that the input will be validated against a mask, so values
not monotonical can be accepted. Examples are shown at the end of this document.
\subsubsection{ \textit{g\_MIN\_PULSE\_LENGTH} }
It specifies the default value that it is used for the Minimum Pulse Length
for the MinPL field in CTR1 register.
This field overrides the value of CPL in CTR0 in case the user tries to
configure an output pulse with a width lower than MinPL. Therefore CTR0 will be
MinPL.\\
\textbf {\textit {BOUNDING MUST BE IMPLEMENTED}}
\subsubsection{ \textit{g\_MAX\_PULSE\_LENGTH} }
It specifies the default value that it is used for the Maximum Pulse Length
for the MaxPL field in CTR1 register.
This field overrides the value of CPL in CTR0 in case the user tries to
configure an output pulse with a width longer than MaxPL. Therefore CTR0 will be
MaxPL.\\
\textbf {\textit {BOUNDING MUST BE IMPLEMENTED}}
\subsection{ \textit{g\_DEFAULT\_PULSE\_LENGTH} }
It specifies the default value that it is used for the Current Pulse Length
for the CPL field in CTR0 register.
It should be noted that its value is bounded by MinPL and MaxPL fields of CTR1
register.\\
\textbf {\textit {BOUNDING MUST BE IMPLEMENTED}}
\subsection{Registers}
\subsubsection{STATUS}
The STATUS register is a read-only register. It shows the basic configuration of
the trigger HDL core and the status of the trigger core RAM blocks.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & General ENable\\
\hline
1 & CLR & General CLeaR\\
\hline
3-2 & x & Reserved\\
\hline
4 & EN\_TT & Enable Time-Tagging\\
\hline
5 & CLR\_TT & CLeaR Time-Tagging\\
\hline
7-6 & x & Reserved\\
\hline
8 & EMPTY & RAM empty flag\\
\hline
9 & FULL & RAM full flag\\
\hline
10 & WA & RAM wrapped around\\
\hline
15-11 & x & Reserved\\
\hline
31-16 & CPL & Current Pulse Length\\
\hline
\end{tabular}
\subsubsection{CTR0}
The CTR0 register is a read-write register. It allows setting up the basic
configuration of the trigger HDL core, its RAM blocks and both the deglitching
mask and output pulse length to be used.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & General ENable\\
\hline
1 & CLR & General CLeaR\\
\hline
3-2 & x & Reserved\\
\hline
4 & EN\_TT & Enable Time-Tagging\\
\hline
5 & CLR\_TT & Clear Time-Tagging\\
\hline
7-6 & RDM & time-tagging ReaD Mode\\
\hline
15-8 & CGM & Current Glitch Mask\\
\hline
31-16 & CPL & Current Pulse Length\\
\hline
\end{tabular}
\subsubsection{CTR1}
The CTR1 register is a read-write register. It allows setting up the boundaries
that override invalid values of CPL field in CTR0.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & MinPL & Minimum Pulse Length\\
\hline
31-16 & MaxPL & Maximum Pulse Length\\
\hline
\end{tabular}
\subsubsection{RAM0}
The RAM0 register is a read-write register. It allows setting up the RAM
and the read request to it.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN\_TT & Enable Time-Tagging \\
\hline
1 & CLR\_TT & Clear Time-Tagging \\
\hline
3-2 & RDM & time-tagging ReaD mode\\
\hline
4 & EMPTY & RAM empty\\
\hline
5 & FULL & RAM full\\
\hline
6 & WA & RAM Wrapped Around\\
\hline
7 & RQT & ReQuesT read\\
\hline
31-8 & x & Reserved\\
\hline
\end{tabular}
\subsubsection{RAM1}
The RAM1 register is a read-only register. It shows the current read and write
address configured to be accessed.\\
\begin{tabular}{| l | c | c |}
\hline
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & CRA & Current Read Address\\
\hline
31-16& CWA & Current Write Address\\
\hline
\end{tabular}
\subsubsection{RAM2}
The RAM2 register is a read-write register. It allows setting up the RAM adress
range to be read.\\
\begin{tabular}{| l | c | c |}
\hline
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & SA & Starting read Address\\
\hline
31-16 & EA & Ending read Address\\
\hline
\end{tabular}
\pagebreak
\subsection{Internal Memory Mapping}
The internal registers map is as follow:\\
\begin{tabular}{| c | c | c |}
\hline
\textbf{Address} & \textbf{Register} & \textbf{Access} \\
\hline
\hline
\textbf{0x0} & \textit{STATUS} & Read-only\\
\hline
\textbf{0x1} & \textit{CTR0} & Read-write\\
\hline
\textbf{0x2} & \textit{CTR1} & Read-write\\
\hline
\textbf{0x3} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x4} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x5} & \textit{RAM0} & Read-write\\
\hline
\textbf{0x6} & \textit{RAM1} & Read-only\\
\hline
\textbf{0x7} & \textit{RAM2} & Read-write\\
\hline
\end{tabular}
\subsection{How to use it}
\subsubsection{Initialization}
\begin{enumerate}
\item Disable trigger core before configuring:
\textit{CTR0: write 0 to EN and EN\_TT}\\
\item Set the minimum and maximum pulse lengths:
\textit{CTR1: writes into MinPL and MaxPL}\\
\item Set the deglitching mask and pulse length to be used:
\textit{CTR0: set CGM and CPL}\\
\item Clearing RAM block up before starting:
\textit{RAM0: write 1 to CLR\_TT}\\
\item Disable RAM clearup and enable module:
\textit{CTR0: write 1 to EN and EN\_TT, write 0 to CLR\_TT}\\
\end{enumerate}
\subsubsection{Changing the deglitch mask and stages length}
Three examples are given.\\
\begin {enumerate}
\item[\textbf{Example A}]\\
\begin{itemize}
\item \textbf{ \textit{g\_MAX\_GLITCH\_STAGES} }: 6
\item \textbf{ CTR0[CGM] }: 0x0BAA
\end{itemize}
In this case, only the six less significant bits of CGM field will be used as
mask: ''11 1010''. This mask signal is checked against the sampled input signal.
If it matches, it is considered as a pulse and it will be replicated.\\
\item[\textbf{Example B}]\
The common use will be in the form:
\begin{itemize}
\item \textbf{ \textit{g\_MAX\_GLITCH\_STAGES} }: 6
\item \textbf{ CTR0[CGM] }: 0xFFFF
\end{itemize}
Which translates into \textit{pulses of length \textbf{6 * wb\_clk } or greater should
be replicated}.\\
\item[\textbf{Example C}]\
Reducing the Deglitch Mask delay is achieved by configuring CGM
properly:
\begin{itemize}
\item \textbf{ \textit{g\_MAX\_GLITCH\_STAGES} }: 6
\item \textbf{ CTR0[CGM] }: 0x0007
\end{itemize}
which means \textit{pulses of length \textbf{3 * wb\_clk} or greater should be
replicated}.
\end{enumerate}
\subsubsection{Register writes step-by-step}
\begin{enumerate}
\item Disable trigger core before configuring:
\textit{CTR0: write 0 to EN and EN\_TT}\\
\item Set the minimum and maximum pulse lengths:
\textit{CTR1: writes into MinPL and MaxPL}\\
\item Set the deglitching mask and pulse length to be used:
\textit{CTR0: set CGM and CPL}\\
\item Reenable module:
\textit{CTR0: write 1 to EN and EN\_TT}\\
\end{enumerate}
\subsubsection{Changing the pulse width}
\begin{enumerate}
\item Disable trigger core before configuring:
\textit{CTR0: write 0 to EN and EN\_TT}\\
\item Check/set the minimum and maximum pulse lengths:
\textit{CTR1: read/write into MinPL and MaxPL}\\
\item Set the pulse length to be used:
\textit{CTR0: set CPL}\\
\item Reenable module:
\textit{CTR0: write 1 to EN and EN\_TT}\\
\end{enumerate}
\pagebreak
\section{Multiboot manager}
\label{sec:multiboot}
\subsection{Structure}
\begin{tabular}{|l|}
\hline
\textit{NOTE1:} this module is platform specific. It only works with Spartan
6\\
\hline
\textit{NOTE2:} in case the EEPROM memory is replaced, SPI opcode will\\ change.
User should notice this issue.\\
\hline
\end{tabular}\\
The trigger module contains sever
blocks related the following way:\\
-- \textbf{\textit{multiboot\_top.vhd}}
----- \textbf{multiboot\_regs.vhd}
----- \textbf{multiboot\_core.vhd}
--------- ICAP\_SPARTAN6 (\textit{Xilinx primitive})
\subsubsection{\textit{multiboot\_top.vhd}}
The top file of the module. It interconnects the Wishbone to internal register
module, \textit{multiboot\_regs.vhd}, to the core logic in
\textit{multiboot\_core.vhd}.
No \textit{generics} are implemented in this HDL module.
\subsubsection{multiboot\_regs.vhd}
In this module the registers neeeded for specifiying the memory addresses in
which the FPGA must boot to are defined.
An internal register is defined for selectively controlling operations to be
performed by this module (full ICAP reprogramming process, issuing ICAP
commands, refreshing ICAP registers). The set of operations that can be issued
is restricted for security reasons. The allowed operations are further listed in
the \textit{Register subsection}.
\subsubsection{multiboot\_core.vhd}
It is responsible of accessing ICAP port through the internal
\textit{ICAP\_SPARTAN6 Xilinx primitive}. A finite state machine is implemented
in accordance to Chapter 7 of \cite{UG380}.
\subsubsection{Behaviour}
Following the instructions of \cite{UG380} strictly leads to correct multiboot
of the FPGA. Firstly, registers \textit{GENERAL1}, \textit{GENERAL2},
\textit{GENERAL3} and \textit{GENERAL4} must be programmed with valid values. It
should be keept in mind that the \textit{SPI opcode} in \textit{GENERAL4}
register depends on the \textit{EEPROM chip} mounted on the board.\\
Then, a \textit{full multiboot} command must be performed via ICAP interface
through a write in \textit{CTRL} register in \textit{multiboot module}.
\subsection{Parameters}
No \textit{generic} parameters are offered in this module.
\subsection{Registers}
\subsubsection{CTRL}
The \textit{CTRL} register is a read-write register for \textit{OP} field and a
read-only for \textit{PEND} bit.
It specifies the operations that can be controlled by an user.\\
\begin{tabular}{| l | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
3-0 & OP & OPeration to be performed \\
\hline
4 & PEND & operation PENDing \\
\hline
\end{tabular}\\
Whenever an operation is specified by the user, it is passed to ICAP Xilinx
primitive through \textit{multiboot\_core.vhd} and the bit flag \textit{PEND} is
set to '1' until it is completely finished.\\
\textbf{Operations}\\
The valid operations that can be requested are the following:\\
\begin{tabular}{| c | l |}
\hline
\textbf{OP byte} & \textbf{Operation}\\
\hline
\hline
0x0 & \textbf{Full multiboot process} as specified in \cite{UG380}\\
\hline
0x1 & \textbf{Write GENERAL1} register from \\
& \textit{multiboot\_regs.vhd} into FPGA\\
\hline
0x2 & \textbf{Write GENERAL2} register from \\
& \textit{multiboot\_regs.vhd} into FPGA\\
\hline
0x3 & \textbf{Write GENERAL3} register from \\
& \textit{multiboot\_regs.vhd} into FPGA\\
\hline
0x4 & \textbf{Write GENERAL4} register from \\
& \textit{multiboot\_regs.vhd} into FPGA\\
\hline
0x7 & Perform \textbf{IPROG command}\\
\hline
0xD & \textbf{Refresh STAT} register\\
& into \textit{multiboot\_regs.vhd} \\
\hline
\end{tabular}\\
Full multiboot process, \textit{OP} = 0x0, comprises commamnds:
\begin{enumerate}
\item \textit{OP} = 0x1
\item \textit{OP} = 0x2
\item \textit{OP} = 0x3
\item \textit{OP} = 0x4
\item \textit{OP} = 0x7
\end{enumerate}
\subsubsection{STAT}
The \textit{STAT} register is a read-only register. A \textit{refresh operation}
should be completed before retrieving correct \textit{STAT} information.\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & CRC\_ERROR & CRC ERROR detected in bitstream\\
\hline
1 & ID\_ERROR & IDCODE not validated\\
\hline
2 & DCM\_LOCK & DCMs and PLL are locked \\
\hline
3 & GTS\_CFG\_B & Global tristate\\
\hline
4 & GWE & Global Write Enable\\
\hline
5 & GHIGH\_B & GHIGH\\
\hline
6 & DEC\_ERROR & DEC\_ERROR\\
\hline
7 & PART\_SECURED & Decryption is set\\
\hline
8 & HSWAPEN & HWSAPEN\\
\hline
11-9 & MODE & MODE pins\\
\hline
12 & INIT\_B & INIT\_B\\
\hline
13 & DONE & DONE input pins\\
\hline
14 & IN\_PWRDWN & suspend status\\
\hline
15 & SWWD\_STRIKEOUT & config error because of invalid sync\\
\hline
\end{tabular}\\
\subsubsection{GENERAL1}
Bit scrambling is done in VHDL code. Bit order must be as specified below:\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
15-0 & MBT\_ADDR\_L & MultiBoot image ADDRess Lower half\\
\hline
\end{tabular}\\
\subsubsection{GENERAL2}
Bit scrambling is done in VHDL code. Bit order must be as specified below:\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
7-0 & MBT\_ADDR\_L & Multiboot image ADDRess Lower Half\\
\hline
15-8 & SPIO & SPI Opcode\\
\hline
\end{tabular}\\
\subsubsection{GENERAL3}
Bit scrambling is done in VHDL code. Bit order must be as specified below:\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
15-0 & GLD\_ADDR\_L & GolDen image ADDRess Lower half\\
\hline
\end{tabular}\\
\subsubsection{GENERAL4}
Bit scrambling is done in VHDL code. Bit order must be as specified below:\\
\begin{tabular}{| l | c | l |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
7-0 & GLD\_ADDR\_H & GoLDen image ADDRess Higher Half\\
\hline
15-8 & SPIO & SPI Opcode\\
\hline
\end{tabular}\\
\subsection{Internal Memory Mapping}
The Internal Memory Mapping is as follows:\\
\begin{tabular}{| c | c | c |}
\hline
\textbf{Address} & \textbf{Register} & \textbf{Access} \\
\hline
\hline
\textbf{0x0} & \textit{CTRL} & Read-only\\
\hline
\textbf{0x1} & \textit{STAT} & See \textit{STAT} description\\
\hline
\textbf{0x2} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x3} & \multicolumn{2}{l|}{Not used}\\
\hline
\textbf{0x4} & \textit{GENERAL1} & Read-write\\
\hline
\textbf{0x5} & \textit{GENERAL2} & Read-write\\
\hline
\textbf{0x6} & \textit{GENERAL3} & Read-only\\
\hline
\textbf{0x7} & \textit{GENERAL4} & Read-write\\
\hline
\end{tabular}
\subsection{How to use it}
It requieres three parameters to be specified:
\begin{itemize}
\item Address of the Golden Image
\item Address of the Multiboot Image
\item SPI Opcode of the EEPROM serial interface
\end{itemize}
Bad specifications of addresses will not reprogram the FPGA.
\subsubsection{Submitting ICAP instructions}
It can be either a two-step or a single-step process. Two-step processes are
related with changes in \textit{GENERAL[X]} register. Submitting an ICAP
command is a single-step-process (\textit{IPROG} instruction, for instance).
\begin {itemize}
\item[\textbf{Example A:}]\\
\textbf{Full Multiboot Configuration}\\
This is a scenario is useful when the EEPROM memory map has changed for
the allocation of the two FPGA bitstreams.
\begin {enumerate}
\item Write \textit{GENERAL1} register.
\item Write \textit{GENERAL2} register.
\item Write \textit{GENERAL3} register.
\item Write \textit{GENERAL4} register.
\item Write \textit{CTRL} register.\\
\textit{CTRL} should issue a \textbf{Full multiboot process} operation code
(0x0).
\end {enumerate}
\item[\textbf{Example B:}]\\
\textbf{Change an individual Boot Look Up Address}\\
This is a scenario is useful when the EEPROM memory map has changed for
the allocation of only one of the FPGA bitstreams.
\begin {enumerate}
\item Write \textit{GENERAL[X]} register. Where X={1,3}
\item Write \textit{GENERAL[X+1]} register.
\item Write \textit{CTRL} register.\\
\textit{CTRL} should issue a \textbf{Write GENERAL[X]} operation code.
\item Write \textit{CTRL} register.\\
\textit{CTRL} should issue a \textbf{Write GENERAL[X+1]} operation code.
\end {enumerate}
\item[\textbf{Example C:}]\\
\textbf{Reprogram FPGA without change in Bitstream Location}\\
If the EEPROM memory map has not changed but we want to reload one of the
images, we just issue an \textit{IPROG} instruction through the \textit{ICAP}
interface.
\begin {enumerate}
\item Write \textit{CTRL} register.\\
\textit{CTRL} should issue an \textbf{IPROG} operation code(0x7).
\end {enumerate}
\end {itemize}
\pagebreak
\section{EEPROM manager}
\label{sec:EEPROM}
\pagebreak
\bibliographystyle{unsrt}
\bibliography{UserGuide}
\end{document}
\ No newline at end of file
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____ ____
/ /\/ /
/___/ \ / VENDOR : Xilinx Inc.
\ \ \/ VERSION : 14.2 (P.28xd)
\ \ APPLICATION : /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin/unwrapped/compxlib
/ / CONTENTS : Compilation Log
/___/ /\ FILENAME : compxlib.log
\ \ / \
\___\/\___\
Release 14.2 - /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin/unwrapped/compxlib 14.2 (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
ERROR:Portability:90 - Command line error: Switch "--help" is not allowed.
Usage: compxlib {-arch <arch_name>} [-cfg [<cfg_file>]] [-dir <output_dir>] [-e <dir_parh>] [-exclude_sublib] [-exclude_superseded] [-info <dir_path>] [-intstyle ise|xflow|silent] [-l <language>] {-lib <lib_name>} [-log <log_file>] [-p <dir_path>] {-s
<simulator>} [-source_lib <dir_path>] [-verbose] [-w] [-64bit] {-cfgopt <opt_string>}
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-------------------------------------------------------------------------------
-- LIST OF ISSUES
-------------------------------------------------------------------------------
ISSUE COMMENT
464 A MOSFET got broken. Some captures to detect a broken MOSFET.
523 Problem with the I2C because of unwanted clock stretching and poor
pulling-up of the SCL and SDA lines.
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doc/TransferKnowledge/report.bib deleted 100644 → 0
View file @ 224a9757
@misc{StdBlocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
@misc{FunSpecs,
author = "C. Gil Soriano",
title = {{Standard Blocking Repeater in VME64x Format, Functional Specifications}},
month = aug,
year = 2012,
note = "{\url{http://www.ohwr.org/documents/104}}"
}
@misc{TechFlyback,
author = "C. Gil Soriano",
title = {{Flyback circuit outputting Standard Blocking for CTDAH}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/110}}"
}
@misc{BlockingMono,
author = "C. Gil Soriano",
title = {{A Triggered Monostable Blocking Oscillator Used in legacy Channel
Repeaters}},
month = aug,
year = 2012,
note = "{\url{http://www.ohwr.org/documents/94}}"
}
@misc{issuesReportV1,
author = "C. Gil Soriano",
title = {{Report of issues in CONV-TTL-BLO v1.0 EDA-02446-V1-0}},
month = oct,
year = 2012,
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/show/pcb/doc/issues/conv-ttl-blo?rev=basic_trigger_addingGenerics}}"
}
@TECHREPORT{I2Cdoc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{I2C Slave to Wishbone Master module}",
month = nov,
year = 2012,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/i2c_slave_wb_master/doc/i2cSpecs.pdf}}"
}
@TECHREPORT{SPIdoc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{SPI master multifield HDL core}",
month = oct,
year = 2012,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/spi_master_multifield/doc/spiSpecs.pdf}}"
}
@TECHREPORT{M25P32doc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{m25p32 manager HDL core}",
month = oct,
year = 2012,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/m25p32/doc/m25p32.pdf}}"
}
@TECHREPORT{multibootDoc,
author = "C. Gil Soriano",
institution = "CERN, BE-CO-HT",
title = "{Multiboot HDL module}",
month = jan,
year = 2013,
number = "v0.9",
note =
"{\url{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/changes/hdl/multiboot/doc/multiboot.pdf}}"
}
@TECHREPORT{ELMAspecI2C,
author = "S. Iglesias Gonsalvez",
institution = "CERN, BE-CO-HT",
title = "{ELMA Crates Specification, Access to board data using
SNMP and I2C}",
month = feb,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/227}}"
}
@TECHREPORT{ELMAsysMonDoc,
institution = "ELMA",
title = "{NEW Sysmon Manual}",
number = "v1.11",
note = "{\url{http://www.ohwr.org/documents/226}}"
}
@TECHREPORT{UG380,
institution = "Xilinx Inc.",
title = {{Spartan-6 FPGA Configuration User Guide}},
month = jul,
year = 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
@TECHREPORT{UG381,
institution = "Xilinx Inc.",
title = "{Spartan-6 FPGA SelectIO Resources}",
month = dec,
year = 2010,
number = "v1.4",
note =
"{\url{http://www.xilinx.com/support/documentation/user_guides/ug381.pdf}}"
}
@TECHREPORT{,
institution = "Xilinx Inc.",
title = "{}",
month = jan,
year = 2012,
number = "v0.9",
note =
"{\url{}}"
}
@TECHREPORT{,
institution = "Xilinx Inc.",
title = "{}",
month = jan,
year = 2012,
number = "v0.9",
note =
"{\url{}}"
}
doc/TransferKnowledge/report.tex deleted 100644 → 0
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\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage[table]{xcolor}
\usepackage{tabularx}
%%\usepackage{draftwatermark}
%%\SetWatermarkLightness{0.9}
%%\SetWatermarkScale{5}
\begin{document}
\title{\textbf{Level Conversion Circuits}\\Transfer Knowledge}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{
\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{January 22, 2012}
\hypersetup{
colorlinks = true,
urlcolor = blue
pdftitle = {Level Conversion Circuits Transfer Knowledge},
pdfauthor = {Carlos Gil Soriano},
pdfsubject = {Transfer Knowledge for the CONV-TTL-BLO, CONV-TTL-RS485
and CONV-TTL-RTM-[X] boards},
pdfkeywords = {Blocking, Pulse repetition, legacy systems, basic
functionality, extended functionality, ELMA SPI, VHDL}
}
\pagenumbering{roman}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25,
keepaspectratio]{../OHWR/Pictures/Figures/CERN-Logo.png}
\end{center}
\end{figure}
\begin{abstract}
\href{http://www.ohwr.org/projects/level-conversion}
{Level Conversion Circuits project} aims to replace old legacy systems
targeted for pulse repetition, either in Blocking or RS485 format.\\
A complete list of legacy boards to be superseded can be found in the
wiki page:
\begin{center}
\href{http://www.ohwr.org/projects/level-conversion}
{\textbf{http://www.ohwr.org/projects/level-conversion/wiki}}
\end{center}
\end{abstract}
\vspace{2cm}
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|l|R|}
\hline
\multicolumn{3}{|c|}{\textbf{Revision history}}\\
\hline
\hline
\textbf{HDL version} & \textbf{Module} & \textbf{Date}\\
\hline
0.1 & Preliminary version & January 10, 2012\\
\hline
1.0 & Final version & January 22, 2012\\
\hline
\end{tabularx}
\end{center}
\pagebreak
\pagestyle{plain}
\setcounter{page}{1}
\tableofcontents
\pagebreak
\listoftables
\pagebreak
\listoffigures
\pagebreak
\pagenumbering{arabic}
\pagestyle{plain}
\setcounter{page}{1}
\section{Level Conversion Circuit project structure}
The project aims to substitute old boards by newer ones which will be able to
cope with old functionalities and provide extra features.
Two sets of boards will be replaced, depending upon the pulse shape to be
replaced:
\begin{itemize}
\item \textbf{Blocking pulse}\\
The Blocking pulse is defined in the document \cite{StdBlocking}.
\item \textbf{RS485 pulse}\\
The RS485 pulse has to be defined.
\end{itemize}
\subsection{CONV-TTL-BLO replacement table}
\begin{table}[!htb]
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\textbf{Board} & \textbf{EDMS ID} & \textbf{Functionality} & \textbf{}\\
\hline
\hline
\href{http://wikis.cern.ch/display/HT/8+Channel+Repeater+-+8+channel+pulse+repeater}
{8 channel repeater} & EDA-01490 & TTL/$\overline{TTL}$/Blocking to Blocking &\\
\hline
16 channel repeater & & TTL/$\overline{TTL}$/Blocking to Blocking &\\
\hline
\href{http://wikis.cern.ch/display/HT/CTDAC+-+Level+adapter+blocking+to+TTL}
{CTDAC} & EDA-01632 & Blocking to TTL/$\overline{TTL}$ &\\
\hline
\href{http://wikis.cern.ch/display/HT/LA-BLO-TTL+-+Level+adapter+BLO+to+TTL}
{LA-BLO-TTL} & AB-001870 & Blocking to TTL/$\overline{TTL}$ &\\
\hline
\href{http://wikis.cern.ch/display/HT/LAF-BLO-TTL+-+Level+adapter+BLO+to+TTL+bar+filtered}
{LAF-BLO-TTL} & AB-001871 & Blocking to TTL/$\overline{TTL}$ &\\
\hline
\href{http://wikis.cern.ch/display/HT/LASB-TTL-BLO+-+Level+adapter+TTL+to+BLO+standard+blocking+level}
{LASB-TTL-BLO} & AB-001873 & TTL/$\overline{TTL}$ to Blocking &\\
\hline
\href{http://wikis.cern.ch/display/HT/LA-GATE+-+High+amplitude+pulse+transmitter}
{LA-GATE} & AB-001876 & TTL/$\overline{TTL}$ to Blocking &\\
\hline
\href{http://wikis.cern.ch/display/HT/LA-TTL-BLO+-+Level+adapter+TTL+to+BLO}
{LA-TTL-BLO} & AB-001874 & TTL/$\overline{TTL}$ to Blocking &\\
\hline
\href{http://wikis.cern.ch/display/HT/LAPF-TTL-BLO+-+Level+adapter+TTL+to+BLO+pulse+former}
{LAPF-TTL-BLO} & AB-001872 & TTL/$\overline{TTL}$ to Blocking
& 4$\mu$s pulse\\
\hline
\end{tabular}
\caption{CONV-TTL-BLO replacement table}
\end{center}
\end{table}
\subsection{CONV-TTL-RS485 replacement table}
\begin{table}[!htb]
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\textbf{Board} & \textbf{EDMS ID} & \textbf{Functionality} \\
\hline
\hline
\href{http://wikis.cern.ch/display/HT/CTDAD+-+RS485+long+distance+pulse+driver}
{CTDAD} & EDA-01600 & TTL to RS485 transmitter \\
\hline
\href{http://wikis.cern.ch/display/HT/CTDCD+-+Timing+cable+driver}
{CTDCD} & EDA-00925 & TTL to RS485 transmitter \\
\hline
\href{http://wikis.cern.ch/display/HT/CTDCD+-+Timing+cable+driver}
{CTDCR} & EDA-00948 & RS422/RS485 receiver \\
\hline
\href{https://edms.cern.ch/nav/I:EDA-00917:V0/I:EDA-00917:V0/TAB4}
{CTDAR} & EDA-00917 & Optical E2000 to RS422 \\
\hline
\href{https://edms.cern.ch/nav/I:AB-001063:V0/I:AB-001063:V0/TAB4}
{CTDLT} & EDA-00916 & TTL to Optical E2000 or RS422 \\
\hline
\end{tabular}
\caption{CONV-TTL-RS485 replacement table}
\end{center}
\end{table}
\subsection{Front and rear panel boards}
Both CONV-TTL-BLO and CONV-TTL-RS485 projects consist on the same set of
boards: a front board and a rear subsystem.
\subsubsection{Front: ACTIVE}
The front board contains all the active components. Is the only one
receiving power from the crate. Consequently, it holds all the communication
with the crate.\\
It offers I/O to front panel that are TTL compatible, and a SFP
connector used for White Rabbit.\\
Status LEDs are offered, as well.
\subsubsection{Rear: PASSIVE}
The passive subsystem consist of two boards:
\begin{itemize}
\item \textbf{Motherboard}\\
The moherboard connects the VME64x P2 interface with the piggyback
connector. It is shared between Blocking and RS485 projects so as
to reduce global BOM.
\item \textbf{Piggyback board}\\
The piggyback board is different in Blocking and RS485 projects.
It offers I/O in the rear panels. The goal of the piggyback is to
offer an easy-to-plug interface to operators.
\end{itemize}
\pagebreak
\section{Repositories structure}
Both \textit{CONV-TTL-BLO} and \textit{CONV-TTL-RS485} share the same
global structure:
\begin{itemize}
\item \textbf{doc}
\item \textbf{hdl}
\item \textbf{pcb}
\end{itemize}
\subsection{CONV-TTL-BLO}
\begin{itemize}
\item \textbf{doc}\\
It holds all the generic design documentation of the board and files
used in OHWR repo:
\begin{itemize}
\item \textbf{OHWR}\\
This subfolder contains pictures used both in the wiki pages of the
issues section.
\end{itemize}
Some extra subfolders are used: Blocking, HDL and HDLguide. The first
contains the source files and output of the documentation for
\cite{FunSpecs}, \cite{StdBlocking} and \cite{BlockingMono}.\\
\item \textbf{hdl}\\
As \textit{CONV-TTL-BLO} and \textit{CONV-TTL-RS485} will share a lot
of IP cores for either basic or extended functionality, all of the IP
cores are located in \textit{CONV-TTL-BLO}. This repository is depicted
below:\\
\begin{itemize}
\item \textbf{IMAGES}
It contains the top files for basic repetition in
\textit{CONV-TTL-BLO}:
\begin{itemize}
\item \textbf{image0}\\
This is the first bitstream with a very coarse basic repetition.
\item \textbf{image1}\\
It corresponds to the image loaded into the \textit{CONV-TTL-BLO
V1} installed in PS facilities. The logic runs at 200 MHz and the
outputs are glitch-free.
\end{itemize}
\item \textbf{basic\_trigger}\\
It contains the IP core with clocked repetition. It is the core
used in image1 bitstream.\\
\item \textbf{basic\_trigger\_async}\\
It contains the IP core with lowest achievable jitter. No profiling
in the place and route (it can lower the jitter value inyected by
the FPGA).\\
\item \textbf{ctdah\_lib}\\
This is the library that contains generic modules used along the
rest of IP cores within this project.\\
\item \textbf{i2c\_slave\_wb\_master}\\
The I2C slave IP core is located here.\\
\item \textbf{m25p32}\\
The M25P32 IP core is located here. It manages access to the Flash
Memory thanks to the SPI core developed for this project.\\
\item \textbf{multiboot}\\
The multiboot IP core is able to access Xilinx's ICAP primitive to
allow SPI Flash Memory reprogramming from a given set of
locations.\\
\item \textbf{rtm\_detector}\\
Just some files to check for proper RTM detection.\\
\item \textbf{spi\_master\_multifield}\\
The SPI master IP core can be found in this folder. It allows
SPI communication to perform writes and read-backs. It is developed
to be used together with M25P32 module.\\
\item \textbf{trigger}\\
This is the folder to work on the extended trigger functionality.\\
\item \textbf{wr\_core\_demo}\\
Some White Rabbit files to perform a test.\\
\end{itemize}
\item \textbf{pcb}\\
\begin{itemize}
\item \textbf{conv-ttl-blo}\\
Files of \textit{CONV-TTL-BLO V1}.\\
\item \textbf{conv-ttl-blo-v2}\\
Files of \textit{CONV-TTL-BLO V2}.\\
\item \textbf{conv-ttl-rtm}\\
Files of \textit{CONV-TTL-RTM V1}.\\
\item \textbf{conv-ttl-rtm-blo}\\
Files of \textit{CONV-TTL-RTM-BLO V1}.\\
\item \textbf{doc}\\
It contains all the reports of the V2 board reviews and a report
with all the issues found in V1 \cite{issuesReportV1}.\\
\end{itemize}
\end{itemize}
\subsubsection{IP core structure}
Every IP core developed (\textit{i2c\_slave\_wb\_master},
\textit{m25p32}, \textit{multiboot},\textit{spi\_master\_multifield}
and \textit{trigger}) follow the same structure:
\begin{itemize}
\item \textbf{doc}\\
It holds the source files for generating beautiful, LaTeXed
documentation, like this document.\\
\item \textbf{project}\\
It holds all the .xise, .gise files and all the temporary ones.
Inside this folder it can be found a \textit{wave.do} file
(typically inside the \textit{waveform} subfolder).\\
\item \textbf{rtl}\\
It holds all the RTL files. All the IP cores follows the following
design schema:\\
\begin{figure}[!htb]
\begin{center}
\includegraphics[scale=1,keepaspectratio]
{./Figures/IPcoreStruct.png}
\end{center}
\caption{IP core structure}
\end{figure}
The \textit{top} files interconnects the \textit{core} (which has
all the logic, controls the FSMs and the outputs) with the
\textit{regs}, responsible for controlling access to internal
registers via \textit{core} or a \textit{wishbone} interface.\\
Additionally the \textit{package} provides the definition of
constants, register structures (defined as records) and translation
functions for them to/from \textit{std\_logic\_vector}.\\
All the cores follow the ESA and CERN@BE-CO-HT good VHDL practices,
Alessandro Rubini's advices on how to write mantainable code and
the comments are \href{http://www.stack.nl/~dimitri/doxygen/}
{doxygenized}.\\
\item \textbf{test}\\
It holds all the test files but the \textit{wishbone\_driver},
which is located in ctdah\_lib folder. The test is written in VHDL
as is as structured as follows:\\
\begin{figure}[!htb]
\begin{center}
\includegraphics[scale=1,keepaspectratio]
{./Figures/testStruct.png}
\end{center}
\caption{IP core testbench structure}
\end{figure}
The dashed lines of both drivers means that the cores are not
intended to be synthesizable.\\
Some of the testbench generates a log file to quickly check the
result of the test. Some others testbenches make use of
\textit{ModelSim SignalSpy} library to be able to read and check
internal signals of given subcomponents, without the need of
modifying files (either definition of VHDL ports or adding
precompiler lines to the code).\\
\end{itemize}
\subsection{CONV-TTL-RS485}
It follows the same structure as \textit{CONV-TTL-BLO}. The IP cores to be
used in this board correspond to the ones developed for
\textit{CONV-TTL-BLO}.
\pagebreak
\section{Blocking boards replacement: CONV-TTL-BLO}
\subsection{Legacy boards}
\subsubsection{Problems faced}
Old Blocking modules employed \textbf{three magnetically coupled inductors
difficult to replace}. Because of this fact, the design of CONV-TTL-BLO
started. Hence, been able to easily replace the components was of paramount
importance since the very beginning of the designing stage.\\
Apart from this point, the need of \textbf{remote control and management} of the
boards had an increased importance. Including a FPGA copes with this
problem.
\subsubsection{Jitter}
Due the simplistic way for controlling the replication of the pulses, these
modules have a low figure of jitter.
\subsection{CONV-TTL-BLO design}
The functional specifications of CONV-TTL-BLO can be found in
\cite{FunSpecs}.
We can divide between basic and extended functionalities.
\subsubsection{Basic functionalities}
Aimed to be fully compliant with legacy systems:
\begin{itemize}
\item Replicate Blocking pulses.
\item Translate to/from TTL and $\overline{TTL}$ from/to Blocking.
\item Provide galvanic isolation in the links.
\item To be glitch-free.
\end{itemize}
The design of the Blocking driver follows a Flyback topology
\cite{TechFlyback}, which inherently provides galvanic isolation. So as to
properly drain up the remaining built-up magnetic current in the inductor,
a snubber circuit was added. The snubber circuit can be found in
\cite{BlockingMono}.\\
Because of the Flyback topology, the three-widing coupled inductor was
replaced by a 1:1 coupled inductor. The selection of this coupled inductor
follows the premise of minizing the chances of being out of stock in the
future.\\
\begin{table}[!htb]
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{8cm}{|l|R|}
\hline
\textbf{Manufacturer} & \textbf{Series}\\
\hline
\hline
Pulse Electronics & PF0552 and PF0553\\
\hline
Coilcraft & MSD1278\\
\hline
Coiltronics & DR74 and DR125\\
\hline
\end{tabularx}
\caption{Coupled inductor series replacements}
\end{center}
\end{table}
In the event of having to choose a different coupled inductor please
check the correct values and margins for:
\begin{itemize}
\item \textit{Saturation current}
\item \textit{Primary inductance}
\item \textit{Coupling ratio}
\item \textit{Footprint}
\end{itemize}
\subsubsection{Extended functionalities}
They provide increased control thanks to the FPGA and the use I2C line of
the VME64x interface by means of \textit{SERA} and \textit{SERB} pins.
\begin{itemize}
\item Selectable pulse length.
\item Time-tagging of repeated pulses via White Rabbit.
\item Log of inputs and repetitions.
\item Remote reprogramming of flash-stored FPGA bitstreams via I2C
interface.
\end{itemize}
\subsubsection{V1 schematics overview}
CONV-TTL-BLO, namely CERN
\href{https://edms.cern.ch/nav/EDA-02446}{EDMS-02446 project}, is
described below.
\begin{itemize}
\item \textbf{TOP page}\\
The top page shows the main blocks in which the project is divided
into.\\
Conceptually, the left part of the schematic corresponds to the front
panel and some clocking resources, used in White Rabbit.\\
In the center we can found the FPGA, a Spartan 6 LX45T, which is the
logic core of the design. This model of Spartan is used is many
others within OWHR and BE-CO-HT, making portability of IP cores
seamless. Due to the fact of being a 6 series, SerDes functionality
will be later on used in V2 to improve sampling jitter of repeated
pulses.\\
All the blocks corresponding to the connections with VME64x
backplane and rear transistion module are over the right part of the
top schematic page.\\
\item \textbf{Power supplies}\\
Power supplies are covered in the next two pages.\\
In the first one, the rails for all the logic ICs and FPGA power is
provided. Decoupling capacitors for the FPGA are found in it. Values
and sizes of the FPGA decoupling network are consistent with the
recommendations of the vendor. All the I/O banks in the FPGA are tied
to 3.3 volts.\\
The second page corresponds the power supply needed for the
generation of the 24 volts amplitude blocking pulses. Correct
dimensioning for impulsive responses, gain and margin budgets were
calculated and verified with Texas Instruments Switcher Pro. It
should be noted here that the Power MOSFET in V1 was changed by a
similar performance one, due to soon obsolescency of the part.\\
Just as a reminder for new designers, the selection of critical
capacitors was taken with the view of a long-lasting worklife of the
boards. Hence, the use of conductive polymer capacitors is
recommended. In this design, OS-CON capacitors are used instead in
electrolitic ones. In designs in which tantalum capacitors are of
expected use, a close look to POSCAP is recommended. In either case,
improved conductance and better temperature behaviour is expected
over electrolitic and tantalum, respectively.
\item \textbf{FPGA}\\
FPGA connections are splitted in two pages: \textit{FPGA BANK} and
\textit{MGTX}.
With regard to \textit{FPGA BANK}, all I/O banks are powered to 3.3
volts, as previously indicated. Banks 0 and 1 hold clocking
resources, VME64x I2C connections, LEDs and some extra features.
Banks 2 and 3 plug all the pulses connections with no particular care
in the connections of the pins. This was a limitation in the
performance of V1, solved in V2. So as to much improve perfomance in
the clocked pulse repetition, \textbf{SerDes functionality} should be
used. By reading the advanced I/O resources guidelines from Xilinx,
connections should be done as in V2: \textbf{two non differential
input sources must not belong to \_P and \_N pins of a same
differential FPGA input.}\\
Obviously, clockless pulse repetition will have the lowest possible
jitter figure.\\
\item \textbf{White Rabbit clocking resources}\\
Just copied from SPEC project, V2 indepently configurable DAC
capability. All the decouplings are exactly the same as in SPEC.
\item \textbf{JTAG}\\
In this page the JATG connection, switches and external Flash memory is
depicted. External reset circuitry is added in V2.
\item \textbf{VME64X}\\
VME64X has two connectors P1 and P2. P1 is used for I2C communication
and P2 serves as a connection from front to rear: Blocking I/O
signals, rear LEDs, motherboard and piggyback IDs.\\
When attaching a V1 into a crate it can produce VME64x conflicts in
other VME64x boards, due to not daisy-chaining \textit{bus grant} and
\textit{interrupt ack} lines. This problem is solved in V2.
\item \textbf{INPUT UNIT}\\
The input unit uses an optocoupler preceeded by a DC rejection filter
(a differentiator). The line is terminated and protected via a TVS.
In V2 a Schimtt trigger is added right after the optocoupling to
sharpen the change of the signal.
\item \textbf{OUTPUT BLO}\\
BCT25244 is used because of two reasons:
\begin{itemize}
\item Powerful drive.
\item Reduce stocks cause it is already used in CTRs.
\end{itemize}
A net is misconnected in V1. Issue solved in V2.\\
An important feature implemented in the design is being
glitches-free. This is achived in different ways:
\begin{itemize}
\item Careful startup of the FPGA.
\item Placing of pull-ups or pull-downs in open enable pins.
\end{itemize}
\item \textbf{OUTPUT UNIT}
The output unit consist of a flyback
\end{itemize}
\subsubsection{Changes from V1 to V2}
While debugging V1, issues appeared.
\begin{itemize}
\item \textbf{Power Supplies}
\begin{itemize}
\item Changes to better adjust the voltage for outputting Blocking 24 volts:\\
Issues \textbf{452, 455, 458}\\
\item Remove some noise and adding better protection:\\
Issues \textbf{504, 517}\\
\item Change of MOSFET due to be obsolete soon:\\
Issue \textbf{638}
\end{itemize}
\item \textbf{Pins misconnections}
\begin{itemize}
\item A floating BCT25244 pin:\\
Issue \textbf{463}\\
\item VME64x Daisy chain misconnected:\\
Issue \textbf{502}
\end{itemize}
\item \textbf{Blocking stage}
\begin{itemize}
\item Removal of speed-up diode (causes increased temperature dependency),
use of 5V plane and including an output resistor to improve RC when no
termination is used in a device:\\
Issue \textbf{462}
\end{itemize}
\item \textbf{Front panel}
\begin{itemize}
\item Replacement of status LEDs for a bicolour LED array.
\end{itemize}
\end{itemize}
\subsubsection{Modification to do on V2}
\begin{itemize}
\item \textbf{Power Supplies}\\
Change the Blocking power supply low resistor feedback to produce
Blocking pulses at 24V and not 21V:\\
Issues \textbf{679}
\end{itemize}
\subsection{Piggyback design}
CONV-TTL-RTM-BLO, namely CERN
\href{https://edms.cern.ch/nav/EDA-02453}{EDMS-02453 project}, is described
below.
\begin{itemize}
\item \textbf{TOP page}\\
It connects the VME64X P2 connector with the double row, one hundred
Semtech connector for the piggyback.\\
\item \textbf{Panel and Leds}\\
Just the connectors and nothing else. The TVSs are already in the
motherboard.
\end{itemize}
\pagebreak
\subsection{VHDL design}
The VHDL design has to achieve two milestones:
\begin{itemize}
\item \textbf{Basic functionality}\\
It covers the repetition of the pulse as in the previous legacy boards.\\
\item \textbf{Extended functionality}\\
It improves the basic functionality by time-tagging via White Rabbit the
pulses, allowing remote monitoring and reprogramming of the device.\\
\end{itemize}
\subsubsection{Basic functionality}
The basic functionality is covered in the design used for the
\textit{CONV-TTL-BLO V1} card installed in the test loop in PS
facilities.\\
The IP core has to:
\begin{enumerate}
\item Detect and replicated received pulses once they are not considered
as glitches.
\item Provide a safe and reliable working life. Not producing glitches at
startup.
\end{enumerate}
The IP core sampling frequency for the inputs is 200MHz. The internal
200MHz system clock is generated from the 125MHz clock. Then the induced
sampled jitter will have a maximum value of 5 ns.\\
The following table shows the configuration of the \textit{CONV-TTL-BLO V1}
board installed in the test sage loop in PS facilities:\\
\begin{table}[!htb]
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|R|}
\hline
\textbf{Parameter} & \textbf{Value}\\
\hline
\hline
Pulse height & 24 volts\\
\hline
Pulse length & 1 $\mu$s\\
\hline
Pulse rise time & 80 ns\\
\hline
Pulse fall time & 100 ns\\
\hline
Minimum worst-case repetition jitter & 5 ns\\
\hline
Channel LEDs blinking length & 250 ms\\
\hline
\end{tabularx}
\caption{Configuration for \textit{CONV-TTL-BLO V1} in PS safe loop test}
\end{center}
\end{table}
\subsubsection{Extended functionality}
As said before, extended functionality consist of three main blocks:
\begin{enumerate}
\item Pulse time-tagging
\item I2C communication: access and monitoring
\item FPGA reprogramming functionality
\end{enumerate}
As points 2 and 3 represented bottlenecks for starting with the PTS,
design priority was given to them.\\
\begin{itemize}
\item \textbf{I2C communication}\\
I2C module is of paramount importance for the development of the rest of
functionalities. Being the link between FPGA and outside world, makes I2C
the first module to develop before PTS can be carried out.\\
\begin{table}[!htb]
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|R|R|R|}
\hline
\textbf{IP core} & \textbf{Core} & \textbf{Test} &
\textbf{Guide}\\
\hline
\hline
\textit{I2C\_slave\_wb\_master} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/show/hdl/i2c_slave_wb_master/rtl?rev=master}{Link} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/show/hdl/i2c_slave_wb_master/test?rev=master}{Link} &
\cite{I2Cdoc}\\
\hline
\end{tabularx}
\caption{\textit{I2C\_slave\_wb\_master} IP core files and documents}
\end{center}
\end{table}
The \textit{I2C\_slave\_wb\_master} is an I2C slave core which provides
wishbone master and slave interfaces. The former one serves a bridge from
I2C to internal wishbone modules. The second one lets the
\textit{I2C\_slave\_wb\_master} core registers to be easilly accessed from
the I2C interface by by-passing the I2C wishbone master interface to the
slave. Providing these two interface lets the IP core be consistent and
homogeneous with the rest of cores designed for \textit{CONV-TTL-BLO} and
\textit{CONV-TTL-RS485}.\\
More information about the IP core can be found in its guide \cite{I2Cdoc}.\\
\item \textbf{SPI Flash Memory reprogramming}\\
In order to reprogram the SPI Flash memory different IP cores are
needed.\\
To start off, a SPI master core is needed to place SPI
transactions into the memory. It should be noted that the core developed
for that has taken into account parametric settings to meet timing.\\
Secondly a M25P32 memory handler was designed to write and read from
memory in an easy and optimal way. Memories from the same family can be
used upon some modifications in the package file. Flash pages will be
written from an internal buffer. Thus, the way to program the Flash
memory consist of writing the internal page buffer of the memory handler
and acknowledge a write into a certain page. By doing this,
in all the pages required by the raw bitstream, the new bitstream will
be loaded correctly.\\
The last of the modules corresponds with the ICAP controller, called
multiboot core. This core instanciates the Xilinx's ICAP primitive
according the Xilinx's recommendation and let the user start a load
bitstream process from the I2C via wishbone bridging.\\
\begin{table}[!htb]
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|R|R|R|}
\hline
\textbf{IP core} & \textbf{Core} & \textbf{Test} &
\textbf{Guide}\\
\hline
\hline
\textit{spi\_master\_multifield} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/spi_master_multifield/rtl}{Link} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/spi_master_multifield/test}{Link} &
\cite{SPIdoc}\\
\hline
\textit{m25p32} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/m25p32/rtl}{Link} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/m25p32/test}{Link} &
\cite{M25P32doc}\\
\hline
\textit{multiboot} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/multiboot/rtl}{Link} &
\href{http://www.ohwr.org/projects/conv-ttl-blo/repository/revisions/master/show/hdl/multiboot/test}{Link} &
\cite{multibootDoc}\\
\hline
\end{tabularx}
\caption{SPI Flash Memory reprogramming IP cores}
\end{center}
\end{table}
\end{itemize}
\pagebreak
\section{RS485 boards replacement: CONV-TTL-RS485}
\subsection{Legacy boards}
\subsubsection{Use}
CONV-TTL-RS485 will be use as a more advance card that CONV-TTL-BLO. It
will be able to replicate pulses as in its Blocking counterpart and
redistribute GMT and timing information.\\
\subsubsection{Additional features}
With regard to legacy designs, CONV-TTL-RS485 will be able to detect
insuficient differential level in the reception lines. Thus, defective
and broken links can be detected.\\
\subsection{CONV-TTL-RS485 design}
\begin{itemize}
\item \textbf{TOP page}\\
The division of this project is the same as CONV-TTL-BLO. The driver
stage for outputting to the rear module has changed from Blocking to
RS485.\\
\item \textbf{Power Supply}\\
In this project the Blocking power supply has been removed. The line
filters added in CONV-TTL-BLO V2 have been added to CONV-TTL-RS485
V1.\\
The decoupling FPGA capacitors are the same and the external reset is
included in this page.\\
It should be remarked that all FPGA I/O banks are powered at 3.3
volts.\\
\item \textbf{FPGA BANK}\\
When CONV-TTL-RS485 was designed, the sampling jitter problem was not
found. Subsequently, a change in the I/O trigger FPGA pins for the pulse
repetition should be carried out in the same fashion as it was from
CONV-TTL-BLO V1 to V2.\\
\item \textbf{CLOCKS}\\
Two changes from CONV-TTL-BLO V1 have been done.\\
The first corresponds to let individual configuration of DACs from
the FPGA. The second is the use of cleaner power supply for the DACs.
Voltage drop in ferrites was measured and it is negligible.\\
\item \textbf{VME64X}\\
All the issues of bad daisy chaining in CONV-TTL-BLO V1 have been
addressed.\\
\item \textbf{MGTX}\\
A four position microswitch to enable network identification (which
accelerator/timing domain the card is attached to) is added to the
board.\\
\item \textbf{FRONT TTL}\\
The problems of missconnections and bad power supplying from
CONV-TTL-BLO V1 has been corrected in RS485. Same antiglitch features
applies for the pull-ups and pull-downs.\\
\item \textbf{FRONT PANEL}\\
In this page the new bicolour LED array was introduced, it works
together with Matthieu's IP core.\\
\item \textbf{INPUT UNIT}\\
By using same signed thresholds in the RS485 receivers, an bad/dead
link detection can be carried out.\\
\item \textbf{OUTPUT UNIT}\\
Same transceivers as in reception are used. They are compliant with
speed link for GMT replication.\\
\item \textbf{JTAG}\\
Changes needed in CONV-TTL-BLO V1 have been carried out here.\\
\end{itemize}
\pagebreak
\section{CONV-TTL-RTM: RTM Motherboard}
The motherboard is shared between both the CONV-TTL-BLO and the
CONV-TTL-RS485. It provides connection to piggybacks from the VME64X P2
connector.
\subsection{CONV-TTL-RTM design}
The RTM motherboard consist of a VME64X P2 connector and a two rows 100 pin
male connector. The signals are bypassed from the P2 connector to the 100
pin connector and, for protection measures, TVS are included.
\pagebreak
\section{ELMA crate}
An updated documentation of the ELMA crate System Monitor card can be found
in
\href{https://edms.cern.ch/file/1160628/1/NewSysmon_Usermanual_Rev_1.11_16.02.2012.pdf}{[EDMS].}
\subsection{How to communicate}
The way ELMA crate System Monitor communicate follows the instruction
specified to Mihai Savu in \cite{ELMAspecI2C}.
Hence, to communicate effectively with both the CONV-TTL-BLO and
CONV-TTL-RS485 will consist of:
\begin{enumerate}
\item A byte for I2C address and operation.
\item Two bytes for Wishbone Addressing.
\item Four bytes of data.
\end{enumerate}
To send the I2C commands from ELMA crate, firstly it should be accessed via
telnet. It should be noted that the crate must be connected to the CERN
socket in which the SysMon is registered to, otherwise the device will
not have access to the network. Once accessed via telnet, two commands
can be issued \textit{writereg} and \textit{readreg}, both specified in
\cite{ELMAsysMonDoc}.\\
A comprehensive explanation of the comunication is found in the
documentation of I2C VHDL core specifically done for this project
\cite{I2Cdoc}.
\subsection{Problems}
\begin{itemize}
\item I2C communication
I2C in ELMA crates runs at low speed 400KHz to 100KHz depending on the
capacitive load attached to the SERA, SERB pins. A better pull-up
strategy could have been carried out to solve these problem.\\
Issues \textbf{497, 500, 523}\\
It should be kept in mind that in \textbf{high capacity crates, this
problem can be more serious.}
\item Chasis not so well-built
1U ELMA crate lacks of the robustness of other crates. When a crate lies
on a table with a card plugged in, some badly cut through hole pins can
touch the chasis, producing shortcircuits.\\
Issue \textbf{537}
\end{itemize}
\pagebreak
\section{People involved in Level Conversion Circuits}
Success in a project is due to the joint work of a team. A list of all the
people involved in the project can be found in the table below. I would like
to take advantage of this line to thank them all again for their help and
work.\\
\begin{table}[!htb]
\begin{center}
\newcolumntype{R}{>{\raggedleft\arraybackslash}X}%
\begin{tabularx}{10cm}{|l|R|}
\hline
\multicolumn{2}{|c|}{\cellcolor{black}\textcolor{white}{\textbf{Design team}}}\\
\hline
\textbf{Erik Van der Bij} & Manager\\
\hline
\textbf{Matthieu Cattin } & Technical supervision - Installation\\
\hline
\textbf{Tomasz Wlostowski} & Technical help\\
\hline
\hline
\multicolumn{2}{|c|}{\cellcolor{black}\textcolor{white}{\textbf{Installation
- operators}}}\\
\hline
\textbf{Claude Dehavay } & Installations manager\\
\hline
\textbf{Emmanuel Said } & Main Blocking/RS485 installator - cabling -
front/rear panel\\
\hline
\textbf{Olivier Barriere} & Installation - front/rear panel\\
\hline
\hline
\multicolumn{2}{|c|}{\cellcolor{black}\textcolor{white}{\textbf{ELMA
crate}}}\\
\hline
\textbf{Magnus Bjork } & ELMA crate CERN's responsible\\
\hline
\textbf{Boehr Timo } & ELMA crate links\\
\hline
\textbf{Frank Weiser } & ELMA crate links\\
\hline
\textbf{Silviu Bodeanu } & ELMA System Monitor responsible\\
\hline
\textbf{Mihai Savu } & ELMA I2C C developer\\
\hline
\hline
\multicolumn{2}{|c|}{\cellcolor{black}\textcolor{white}{\textbf{DEM}}}\\
\hline
\textbf{Betty Magnin } & Manager for PCB design and manufacturing\\
\hline
\textbf{William Billereau} & Manager for PCB design and manufacturing\\
\hline
\textbf{Benoit Civel } & Responsible for layout in
\textit{CONV-TTL-BLO V1}\\
\hline
\textbf{Claude Andouillet} & Responsible for layout in
\textit{CONV-TTL-RTM},\textit{CONV-TTL-RTM-BLO}
and \textit{CONV-TTL-RTM-RS485}\\
\hline
\textbf{Bruno Recoldon } & Responsible for layout in
\textit{CONV-TTL-BLO V2} and
\textit{CONV-TTL-RS485}\\
\hline
\end{tabularx}
\caption{People involved in the project}
\end{center}
\end{table}
\appendix
\section{Development roadmap}
\subsection{CONV-TTL-BLO}
\begin{enumerate}
\item \textbf{Remote reprogramming}\\
Remote reprogramming is the key to wind up the development of the IP core
chain needed to perform the PTS in the boards.\\
To achieve this, the \textit{i2c\_slave\_wb\_master}, \textit{m25p32} and
\textit{multiboot} cores should be put together and thoroughly tested. An
image has been provided and can be found in:
\begin{itemize}
\item \textbf{CONV-TTL-BLO/hdl/IMAGES/image1}
\end{itemize}
It should be noted that \textit{image1\_core.vhd} has been splitted from
\textit{image1\_top.vhd} to allow \textit{image1\_core.vhd} be reused in
RS485.\\
Most of the work to be done in the VHDL will be testing that a new raw
bitstream has been loaded into the FPGA. It should be noted that good
understanding of Xilinx's ICAP is needed \cite{UG380}.\\
\item \textbf{PTS}\\
After having a stable bitstream with the basic repetition plus the IP
core chain indicated above, PTS will be "easilly" carried out. That will
involve quite a lot of work.\\
Unlike other projects, such as \textit{SPEC}, in which the PTS could
send commads directly from the host computer, now the commands should be
by-passed over telnet to the SysMon.\\
\item \textbf{Pulse time-tagging}\\
To precisely time-tagging a White Rabbit core must be included in the
FPGA, then all the pulses will be logged and they will be accessible via
I2C. \textit{trigger} core should be worked on to finally meet the
requirements.\\
\item \textbf{Reduce jitter}\\
Reducing jitter means using either the asynchronous solutions in
\textit{basic\_trigger\_async} or writing an IP core using the SerDes
functionality in Xilinx's Spartan 6. A good look on \cite{UG381} is
recommended.
\end{enumerate}
\subsection{CONV-TTL-RS485}
\begin{enumerate}
\item \textbf{Strongly discuss about datagrams parsing}\\
\textit{CONV-TTL-RS485} will offer more functionalities than
\textit{CONV-TTL-BLO}. Correct dimensioning of the
application memory should be taken into account. The memory
requirements will depend upon Jean-Claude's need for parsing
datagrams and place orders into the accelerators. External
memories could be used to improve performance.\\
\item \textbf{Producing a V2}\\
It should be kept in mind that, in order to improve jitter perfomance,
same changes in FPGA I/Os as in \textit{CONV-TTL-BLO V2} apply.\\
\end{enumerate}
\pagebreak
\bibliography{report}{}
\bibliographystyle{unsrt}
\end{document}
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id="image8503"
x="310.48663"
y="31.21929" />
</g>
</svg>
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......@@ -25,3 +25,8 @@
title = {{RTM detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
@misc{flyback,
title = {{Under the Hood of Flyback SMPS Designs}},
howpublished = {\url{http://focus.ti.com/asia/download/Topic_1_Picard_42pages.pdf}}
}
doc/ug/ug-conv-ttl-blo.tex 100755 → 100644
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......@@ -10,8 +10,10 @@
% \SetWatermarkLightness{0.90}
% \SetWatermarkScale{5}
\usepackage{float}
\restylefloat{table}
%\usepackage{float}
%\restylefloat{table}
\usepackage{color}
\begin{document}
......@@ -19,8 +21,6 @@
\title{\textbf{CONV-TTL-BLO \\ User Guide}}
\author{Theodor-Adrian Stana\\
% \href{mailto:t.stana@cern.ch}{\textbf{\textit{t.stana@cern.ch}}}\\
Carlos Gil Soriano\\
% \href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}
BE-CO-HT\\
}
\date{\today}
......@@ -44,8 +44,7 @@ board in double height VME format. It replaces all the following boards:
\item LASB-TTL-BLO
\item LA-GATE
\item LA-TTL-BLO
\item LAPF-TTL-BLO\footnote{For replacing this board a pulse width of 4us
must be set.}
\item LAPF-TTL-BLO \footnote{These boards have a 4~$\mu$s pulse width.}
\end{itemize}
\end{abstract}
......@@ -62,25 +61,31 @@ board in double height VME format. It replaces all the following boards:
\pagebreak
\section*{List of abbreviations}
\begin{itemize}
\item RTM -- Rear Transition Module
\item RTMM -- RTM Motherboard
\item RTMP -- RTM Piggiback
\end{itemize}
\begin{tabular}{l l}
\textit{FPGA} & Field-Programmable Gate Array \\
\textit{RTM} & Rear Transition Module \\
\textit{RTMM} & RTM Motherboard \\
\textit{RTMP} & RTM Piggyback \\
\textit{SFP} & Small form-factor pluggable (in the context of SFP connectors) \\
\end{tabular}
\pagenumbering{arabic}
\setcounter{page}{1}
%======================================================================================
% SEC: Intro
%======================================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
CONV-TTL-BLO is a board intended for replicating Blocking Pulses, offering six
CONV-TTL-BLO is a board intended for replicating blocking and TTL pulses, offering six
totally independent replication channels. The shape of the pulses is defined in
\cite{StandardBlocking}. CONV-TTL-BLO works together with two more boards:
Sec.~\ref{sec:pulse-def}. CONV-TTL-BLO works together with two more boards:
CONV-TTL-RTM and CONV-TTL-RTM-BLO.\\
\begin{figure}[!htdp]
\begin{figure}[!h]
\begin{center}
\includegraphics[scale=0.55, keepaspectratio]{Figures/BLOschema.png}
\caption{Pulse Repetition system}
......@@ -88,17 +93,17 @@ CONV-TTL-RTM and CONV-TTL-RTM-BLO.\\
\end{center}
\end{figure}
CONV-TTL-BLO contains all the active circuitry and it is connected as a Front Module
to a VME64 backplane. CONV-TTL-RTM and CONV-TTL-RTM-BLO are both connected to the rear
part of the crate and provide, in the rear panel, the connectivity of the I/O Blocking
lines. Every channel offers, in the rear panel, three Blocking Pulse outputs and one
Blocking Pulse input.
CONV-TTL-BLO contains all the active circuitry and is connected as a front module
to a VME64x backplane. CONV-TTL-RTM and CONV-TTL-RTM-BLO are both connected to the rear
part of the crate and provide, in the rear panel, the connectivity of the I/O blocking
lines. Every channel offers, in the rear panel, three blocking pulse outputs and one
blocking pulse input.
CONV-TTL-RTM is a motherboard attached to the Rear Transition Module (RTM) of the P2
VME64 connector. It connects CONV-TTL-BLO to CONV-TTL-RTM-BLO and
provides overvoltage protection for all the I/Os of all the channels.\\
CONV-TTL-RTM is a motherboard attached to the rear transition module (RTM) of the P2
VME64x connector. It connects CONV-TTL-BLO to CONV-TTL-RTM-BLO and
provides overvoltage protection for all the I/Os of all the channels.
CONV-TTL-RTM-BLO is a piggyback board mounted on CONV-TTL-RTM. It contains all the
CONV-TTL-RTM-BLO is an RTM piggyback (RTMP) board mounted on CONV-TTL-RTM. It contains all the
LEMO 00 connectors and channel LEDs that are offered in the rear panel.
\begin{table}[htdp]
......@@ -109,7 +114,7 @@ LEMO 00 connectors and channel LEDs that are offered in the rear panel.
%\begin{turn}{90}
\begin{tabular}{l l l}
\hline
\multicolumn{1}{c}{\textbf{Board}} & \multicolumn{1}{c}{\textbf{Connection}} & \multicolumn{1}{c}{\textbf{Ports}} \\
\multicolumn{1}{c}{\textbf{Board}} & \multicolumn{1}{c}{\textbf{Connection}} & \multicolumn{1}{c}{\textbf{Front panel ports}} \\
\hline
\textit{CONV-TTL-BLO} & Front & SFP \\
& & TTL Blocking triggers \\
......@@ -124,33 +129,137 @@ LEMO 00 connectors and channel LEDs that are offered in the rear panel.
%\end{turn}
\end{table}
\pagebreak
\section{Main Board Front Panel}
\label{sec:mainboard-front-panel}
The front panel of CONV-TTL-BLO boards is shown in Figure~\ref{fp}. It consists
of status LEDs and several ports, divided in three sections from top to bottom:
%======================================================================================
% SEC: Panels
%======================================================================================
%\pagebreak
\section{Getting Started}
\label{sec:getting-started}
This section provides a description on testing CONV-TTL-BLO boards for basic functionality. The following steps should
be followed in order to test the board.
%The steps listed below were run on a Linux Ubuntu 12.04 unit connected to the wired Ethernet interface on the
%CERN network. The steps to follow should be similar on any Linux or Windows machine; some details
%such as ELMA crate IP or TELNET client escape characters may differ in the reader's case.
\begin{enumerate}
\item Plug in a front module card to the ELMA crate. Turn on power to the crate and program
the Spartan-6 FPGA.
\item Check that the \textit{PW} LED lights \textit{green} and the \textit{ERR} LED lights \textit{red}. %and \textit{I2C} LEDs light \textit{red}.
The \textit{TTL\_N} LED may also be lit. If it is and the LED is \textit{green}, then the LEVEL
switch is set for INV-TTL pulses.
\item Make sure the LEVEL switch is set for TTL pulses (see Sec.~\ref{sec:ttl-inp}).
% \item Connect to an ELMA crate via TELNET, using the following command on the command line:
%
% \begin{verbatim}
%$ telnet 137.138.192.90
%Trying 137.138.192.90...
%Connected to 137.138.192.90.
%Escape character is '^]'.
%login:user
%password USER
%%>
% \end{verbatim}
%
% \item If the TELNET access is successful, the user should now be presented with a command line
% to the SysMon board. To test basic SysMon functionality, run a \verb=voltage= command on the
% SysMon, which should output the following:
%
% \begin{verbatim}
%%>voltage
%
%
%----------------------------Sensor List---------------------------
%
%--no--Name-------------Type----Value--Unit---State------------------
%
%* 2 +3.3V Thr 3.31 V Ok
%* 3 +5V Thr 5.01 V Ok
%* 4 +12V Thr 12.09 V Ok
%* 5 -12V Thr -12.38 V Ok
% \end{verbatim}
%
% \item It can now be proceeded to reading a register from the CONV-TTL-BLO boards. The \verb=readreg=
% command can be used for this purpose. Assuming a CONV-TTL-BLO board in VME slot 1, reading register
% I2C\_CTR0 at address 0x40 (see Sec. \ref{sec:internal-regs}) is done as follows:
%
% \begin{verbatim}
%%>readreg 1 17
% Read Data: 004042BC
% \end{verbatim}
%
% \item The output of the command should be as above, yielding the default value of the I2C\_CTR0 register.
% The \textit{I2C} LED on the front panel should also be lit \textit{green} now. It can now be proceeded to checking
% the pulse repetition mechanisms.
\item \label{item:pulse-first} First, connect one end of a cable with LEMO 00 connectors at both ends to the TTL input port of channel 1
on the front panel.
\item Configure a pulse generator to output TTL level pulses (\textit{max. 5V}) at a frequency of about 1~Hz
with a pulse length of approx. 1~$\mu$s and connect the other end of the cable to the pulse generator.
The LED of the corresponding channel should light for 96~ms when a pulse arrives. A TTL pulse should be
replicated at the TTL output of channel 1. Check (using e.g., an oscilloscope) that the TTL pulse has a width of
1~$\mu$s and a 3.3~V amplitude.
\item Connect a CONV-TTL-RTM board (with attached CONV-TTL-BLO-RTM) to the back-plane of the ELMA,
on the same VME slot as the front module. The \textit{ERR} LED should turn off. The rear panel pulse status LED
on channel 1 should be lit for 96~ms to signal pulses are being output on the channel. Check that the pulse width
on the output connectors of the rear panel is approx. 1~$\mu$s and the amplitude 24~V.
\item Disconnect the LEMO cable from the front panel and configure the pulse generator for 15~V pulse amplitude, keeping
the pulse width to approx. 1~$\mu$s.
\item Connect the LEMO cable to the input port of channel 1 on the rear panel. Measure that the output pulse on
channel 1 is a blocking level pulse with approx. 1~${\mu}$s pulse width and 24~V in amplitude.
\item \label{item:pulse-last}Finally, measure on the front panel of the front module that on channel 1 the output pulse is 1~${\mu}$s long and 3.3~V.
\item Repeat steps~\ref{item:pulse-first}-\ref{item:pulse-last} for all remaining five channels.
\end{enumerate}
%======================================================================================
% SEC: Panels
%======================================================================================
\section{Front and Rear Panels}
\label{sec:front-panel}
Two panels exist in the context of the pulse repeater boards. The first of these is the
\textit{front panel}, which corresponds to CONV-TTL-BLO boards and offers various status
LEDs, as well as various connectors for TTL and INV-TTL pulses and White Rabbit.
The second is the \textit{rear panel}, located on the other side of the backplane and
corresponding to CONV-TTL-RTM-BLO boards. The rear panel offers blocking pulse connectors
and status LEDs for pulse arrival confirmation.
\subsection{Front panel}
The front panel of CONV-TTL-BLO boards is shown in Fig.~\ref{fp}. It consists
of status LEDs and several ports, divided in four sections from top to bottom:
\begin{itemize}
\item SFP connector: \textbf{[A]}.
\item Blocking connectors: \textbf{[B]} and \textbf{[C]}.
\item General Purpose connectors: \textbf{[D]} and \textbf{[E]}.
\item System status LEDs;
\item Small form-factor pluggable (SFP) connector;
\item TTL pulse connectors;
\item INV-TTL pulse connectors.
\end{itemize}
\begin{figure}[!htdp]
\begin{center}
\includegraphics[scale=.5, keepaspectratio]{Figures/FrontPanel.png}
\caption{CONV-TTL-BLO Front Panel}
\includegraphics[scale=.5, keepaspectratio]{Figures/front-panel}
\caption{CONV-TTL-BLO panel (front panel)}
\label{fp}
\end{center}
\end{figure}
\subsection{Status LEDs}
In the current version of the CONV-TTL-BLO boards, only several of the status LEDs
\subsubsection{System status LEDs}
In the current version of the CONV-TTL-BLO boards, only several of the system status LEDs
present on the board are used, due to limited firmware support in the FPGA.
The implemented status LEDs are presented in Table \ref{tbl:status-leds}. Unimplemented
status LEDs are off by default.
The implemented LEDs are presented in Table \ref{tbl:status-leds}. Unimplemented
system status LEDs are off by default.
\begin{table}
\caption{Status LEDs on CONV-TTL-BLO front panels}
\caption{System status LEDs on CONV-TTL-BLO front panels}
\label{tbl:status-leds}
\centerline
{
......@@ -163,385 +272,422 @@ status LEDs are off by default.
\textit{ERR} & Error LED. Lights \textit{red} when no rear transition module board is present. \\
\textit{TTL\_N} & Negated-TTL status LED. Lights \textit{green} when negated TTL logic is selected
via the 8$^{th}$ position of the on-board selection switch. \\
\textit{I2C} & I$^2$C status LED. Lights \textit{red} until an I$^2$C transfer has taken place. Once
either a read or a write is successfully completed, the I$^2$C status LED lights \textit{green}
to signal the communication is up. \\
% \textit{I2C} & I$^2$C status LED. Lights \textit{red} until an I$^2$C transfer has taken place. Once
% either a read or a write is successfully completed, the I$^2$C status LED lights \textit{green}
% to signal the communication is up. \\
\hline
\end{tabular}
}
\end{table}
\subsection{SFP connector}
\subsubsection{SFP connector}
This connector is used to add White Rabbit support to the CONV-TTL-BLO boards.
If an optic fibre cable is connected to this socket, White Rabbit precise
time-stamping can be added to CONV-TTL-BLO. Three LEDs above the connector are provisioned to
time-stamping can be added to CONV-TTL-BLO. Four status LEDs above the connector are provisioned to
show the status of the White Rabbit link.
White Rabbit is currently not supported in the CONV-TTL-BLO firmware.
\subsection{TTL triggers}
The TTL triggers correspond to block \textbf{[B]} in Figure~\ref{fp}. The connectors are
LEMO 00 (type EPY). By connecting an external trigger source to one of the connectors a pulse
is replicated in a Blocking Pulse level in the Rear Panel and in a TTL panel
in the Front Panel. All input channels are 50$\Omega$-terminated.
\subsection{Repeated TTL pulses}
These correspond to block \textbf{[C]} in Figure~\ref{fp}. The connectors are
LEMO 00 (type EPA). From these connectors a TTL level Blocking Pulse replica of the Rear Panel
outputs if offered to the Front Panel. The pulse width of this output is
similar to the pulse outputted in the Rear Panel; the rise time and top
pulse level are however different from the Blocking output.
When the pulse is output, the LED of the corresponding channel blinks for 125 ms.
The TTL output lines are not internally terminated.
\subsection{General pupose}
Four dedicated inverters can be found in the lower part of the Front Panel (\textbf{[D]} and \textbf{[E]} in
Figure~\ref{fp}). The output is a TTL inverted version of the TTL input. The inverted-TTL outputs are not internally
terminated.
\pagebreak
\section{Getting Started}
\label{sec:getting-started}
This section provides a reference to testing the CONV-TTL-BLO boards for basic functionality. The steps
listed below were run on a Linux Ubuntu 12.04 unit connected to the wired Ethernet interface on the
CERN network. The steps to follow should be similar on any Linux or Windows machine; some details
such as ELMA crate IP or TELNET client escape characters may differ in the reader's case.
The following steps should be performed for testing board functionality:
\begin{enumerate}
\item Plug in a front module card to the ELMA crate. Turn on power to the crate and program
the Spartan-6 FPGA.
\item Check that the \textit{PW} LED lights \textit{green} and the \textit{ERR} and \textit{I2C} LEDs light \textit{red}.
The \textit{TTL\_N} LED may also be lit. If it is and the LED is \textit{green}, this is not an issue.
\item Connect to an ELMA crate via TELNET, using the following command on the command line:
\subsubsection{TTL triggers}
One side of the dual LEMO 00 (type EPY) connector on the CONV-TTL-BLO boards
are used for the TTL trigger inputs. By connecting an external trigger source to
one of these connectors, a Blocking pulse is generated at the rear panel and
a TTL-level pulse is generated at the front panel. The triggers can be either
TTL, or INV-TTL level.
\begin{verbatim}
$ telnet 137.138.192.90
Trying 137.138.192.90...
Connected to 137.138.192.90.
Escape character is '^]'.
login:user
password USER
%>
\end{verbatim}
All input channels are line-terminated with 50$\Omega$ resistors.
\item If the TELNET access is successful, the user should now be presented with a command line
to the SysMon board. To test basic SysMon functionality, run a \verb=voltage= command on the
SysMon, which should output the following:
\subsubsection{Repeated TTL pulses}
The other side of the dual LEMO 00 connector is used to output a TTL-level replica of the blocking
pulse received at the rear panel, or of the trigger signal arrived on the front panel.
The pulse width of this output is similar to the pulse output in the rear panel;
the rise time and top pulse level are however different from the Blocking output.
\begin{verbatim}
%>voltage
When the pulse is output, the LED of the corresponding channel blinks for 96~ms.
TTL output lines are not internally terminated.
----------------------------Sensor List---------------------------
\subsubsection{General purpose}
Four dedicated inverted-TTL connectors can be found in the lower part of the front panel.
Inverted-TTL outputs are not internally terminated.
--no--Name-------------Type----Value--Unit---State------------------
* 2 +3.3V Thr 3.31 V Ok
* 3 +5V Thr 5.01 V Ok
* 4 +12V Thr 12.09 V Ok
* 5 -12V Thr -12.38 V Ok
\end{verbatim}
\subsection{Rear panel}
\item It can now be proceeded to reading a register from the CONV-TTL-BLO boards. The \verb=readreg=
command can be used for this purpose. Assuming a CONV-TTL-BLO board in VME slot 1, reading register
I2C\_CTR0 at address 0x40 (see Sec. \ref{sec:internal-regs}) is done as follows:
The rear panel on CONV-TTL-BLO-RTM boards is shown in Fig.~\ref{fig:rear-panel}. It contains the
input and output connectors, as well as pulse status LEDs for six blocking-level pulse channels. A blocking-level
pulse at the input connector of a channel is repeated at the three outputs of the same channel in
blocking level and TTL level at the output connector of the corresponding channel on the front panel.
\begin{verbatim}
%>readreg 1 17
Read Data: 004042BC
\end{verbatim}
When a pulse is repeated on the output connector of a channel, the pulse status LED is lit for 96~ms.
\item The output of the command should be as above, yielding the default value of the I2C\_CTR0 register.
The \textit{I2C} LED on the front panel should also be lit \textit{green} now. It can now be proceeded to checking
the pulse repetition mechanisms.
\item First, connect one end of a cable with LEMO 00 connectors at both ends to the front module front panel
TTL input ports.
\item Configure a pulse generator to output TTL level pulses (\textit{max. 5V}) at a frequency of about 3~Hz
with a pulse length of $\geq$1~$\mu$s.
\item Connect the other end of the cable to the pulse generator. The LED of the corresponding channel should
light for 125~ms when a pulse arrives.
\item Connect the corresponding channel output port to an oscilloscope and measure the signal level of the pulse
and that the pulse width is 1~${\mu}$s long.
\item Repeat the operation with the other front channels.
\item Connect a rear transition module (RTM) board to the back-plane of the ELMA, on the same VME slot as the front module.
The \textit{ERR} LED should turn off.
\item Connect the LEMO cable to each channel on the front module front panel in turn to each of the channels.
As with the front module front panel, the LED corresponding to the connected channel on the rear transition module piggyback
(RTMP) front panel should be lit for about 125~ms when a pulse arrives. Measure that the output pulse on the blocking
channels is 1~${\mu}$s long and 24~V in amplitude.
\item Disconnect the LEMO cable from the front module front panel and configure the pulse generator for 15~V pulse amplitude.
\item Connect the LEMO cable to channel 1 the front panel of the RTMP board. Measure the output pulse on the corresponding channel of the
RTMP front panel; it should be 1~${\mu}$s long and 24~V in amplitude.
\item Finally, measure on the front panel of the front module that on channel 1 the output pulse is 1~${\mu}$s long and 3.3~V.
\item Repeat for all other channels.
\end{enumerate}
\begin{figure}
\begin{center}
\includegraphics[scale=.55, keepaspectratio]{Figures/rear-panel}
\caption{CONV-TTL-BLO-RTM panel (rear panel)}
\label{fig:rear-panel}
\end{center}
\end{figure}
\pagebreak
\section{Functional Description}
%======================================================================================
% SEC: Pulse signals
%======================================================================================
\section{Output Pulse Signal}
\label{sec:pulse-def}
The task of CONV-TTL-BLO is to output a Blocking Pulse upon a reception of a
trigger is received. As stated before, CONV-TTL-BLO works together with
CONV-TTL-RTM and CONV-TTL-RTM-BLO in the rear part of the crate.
The system formed by these three boards offers three independent channels for
outputting Blocking Pulses. Refer to Figure~\ref{prs} for a visual,
whole-system, description.
In order for CONV-TTL-BLO boards to work as repeaters, logic is implemented in the
on-board FPGA that reacts to a trigger at either rear or front panel and generates a
pulse at the output.
There are two sources for triggering in every channel: one coming from the
Front Panel (CONV-TTL-BLO) and other coming from the Rear Panel
(CONV-TTL-RTM through CONV-TTL-RTM-BLO).
Extensive work was made by Carlos Gil-Soriano to research existing boards at CERN and
define a standard for pulse levels in repeater boards \cite{StandardBlocking}. Based on
this document and on further tests with two of the existing repeater boards at CERN, output
pulse widths and amplitudes were selected for the converter boards.
The trigger policy is that a Blocking pulse will be outputted whenever
either a trigger in the Front Panel or the Rear Panel is detected.
Three types of pulses are defined in the context of CONV-TTL-BLO boards. They
differ only in signal amplitude and signal rise and fall times, due to the circuitry
used to generate them; pulse widths are the same for all three types. Table~\ref{tbl:pulse-levels}
presents the different types of pulses and Fig.~\ref{fig:pulse-def} shows a graphic representation of
the pulse signal.
\begin{table}[htdp]
\begin{table}[h]
\caption{Trigger sources}
\begin{center}
\begin{tabular}{c c c}
\hline
\textbf{Trigger} & \textbf{Board} & \textbf{Connection} \\
\hline
TTL & CONV-TTL-BLO & Front Panel\\
Blocking & CONV-TTL-RTM-BLO & Rear Panel\\
\label{tbl:pulse-levels}
\centerline
{
\begin{tabular}{l c p{.3\textwidth}}
\hline
\end{tabular}
\vspace{0.5cm}
\begin{tabular}{|c|}
\multicolumn{1}{c}{\textbf{Type}} & \textbf{Pk-pk amplitude} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
\textbf{Global trigger is OR function of the two sources above} \\
TTL & 3.3~V & \\
INV-TTL & 3.3~V & Inverted version of TTL pulse \\
Blocking & 24~V & \\
\hline
\end{tabular}
\end{center}
\end{table}
All the control logic of the system is implemented in a Xilinx Spartan-6 FPGA. Apart from
pulse repetition, an I$^2$C to Wishbone bridge is also implemented. This module translates I$^2$C
accesses as presented in accesses to internal memory-mapped registers. The status of the various
components in the system can in this way be checked and controlled.
%CONV-TTL-BLO allows the user to set properties for the pulse replication
%and receive information above the latest events logged in the board.
\pagebreak
\section{Accessing internal registers}
\label{sec:internal-regs}
\subsection{ELMA crates}
CONV-TTL-BLO boards have been designed to operate in ELMA crates. These crates provide a
back plane with VME64x connectors which boards can be plugged into. A dedicated board inside the
ELMA crates called the SysMon (System Monitor) monitors overall system status and provides access
to boards plugged into the VME back plane.
The user can connect to SysMon boards either through a simple RS-232 interface, or through Telnet.
In order to send commands to a board plugged into an ELMA crate, the user would connect to the SysMon
over one of these two interfaces and send \verb=readreg= and \verb=writereg= commands to
board-specific registers, as exemplified in Section \ref{sec:getting-started} to control their functioning.
%Since it is the interface most experimented with up to the point of writing of this document,
%only the Telnet interface is used throughout this document.
\subsection{Board Addressing}
\label{sec:brd-addressing}
Communication with the CONV-TTL-BLO FPGA is done via I$^2$C interface through the SERA and SERB pins
in P1 VME64x connectors. In order to access a CONV-TTL-BLO board, it is necessary to send:
\begin{itemize}
\item The board's 7-bit I$^2$C address. Every CONV-TTL-BLO has an address that prepends two bits
of value \textit{10} to the Geographical Address of the slot according to VME64x specifications.
\item An internal CONV-TTL-BLO register address. It is a 16-bit integer in \textit{little endian} format
(most significant byte is sent first).
\end{itemize}
After this, four bytes of data are read/written from/to the internal CONV-TTL-BLO register. These
four bytes of data are written in \textit{big endian} format (least significant byte is sent first).
The addressing protocol is thoroughly described in \cite{sysmon-i2c}. The SysMon acts as a master on the
I$^2$C interface and has the protocol implemented as software on the on-board processor. The FPGAs on
CONV-TTL-BLO boards implement an I$^2$C slave and decode the data streams sent by the SysMon.
\subsection{CONV-TTL-BLO memory map}
\label{sec:memmap}
Table \ref{tbl:memmap} summarizes the registers mapping in the current version of the CONV-TTL-BLO firmware.
The first column represents the Wishbone address internal to the FPGA firmware and the second column represents
the ELMA register address (in \verb=readreg= and \verb=writereg= commands).
\begin{table}[!hbtp]
\caption{Memory map of the CONV-TTL-BLO design}
\label{tbl:memmap}
\centerline
{
\begin{tabular}{ r r l c p{.5\textwidth} }
\hline
\multicolumn{1}{c}{Address} & \multicolumn{1}{c}{ELMA} & \multicolumn{1}{c}{Name} & \multicolumn{1}{c}{Access} & \multicolumn{1}{c}{Description} \\
\hline
0x00 & 1 & STAT\_L & R & Lower 32 bits of system status register \\
0x04 & 2 & STAT\_H & R & Upper 32 bits of system status register \\
0x40 & 17 & I2C\_CTR0 & R & I$^2$C control register \\
0x44 & 18 & I2C\_LT & R & I$^2$C line timing register, provides the current I$^2$C line speed \\
0x48 & 19 & I2C\_DTX & R/W & Data to transmit through the I$^2$C interface \\
0x4C & 20 & I2C\_DRXA & R & Lower 32 bits of data received through the I$^2$C interface \\
0x50 & 21 & I2C\_DRXB & R & Upper 32 bits of data received through the I$^2$C interface \\
\hline
\end{tabular}
}
\end{table}
\subsection{Register description}
\begin{figure}[h]
\begin{center}
\includegraphics{Figures/pulse-def}
\caption{Pulse signal shape}
\label{fig:pulse-def}
\end{center}
\end{figure}
%\begin{table}[h]
%\caption{Pulse signal characteristics}
%\label{tbl:pulse-def}
%\centerline
%{
% \begin{tabular}{c c p{.5\textwidth}}
% \hline
% \textbf{Symbol} & \textbf{Value} & \multicolumn{1}{c}{\textbf{Description}} \\
% \hline
% $t_w$ & 1~$\mu$s & Pulse width \\
% $t_{p,min}$ & \textcolor{red}{\textbf{!!!}} & Minimum period of pulse signal \\
% \hline
% \end{tabular}
%}
%\end{table}
%======================================================================================
% SEC: Boards
%======================================================================================
\section{Converter Boards}
\label{sec:boards}
This section gives further information about the three boards which when coupled together
can be used to replicate blocking-level pulses.
\subsection{CONV-TTL-BLO}
\label{sec:conv-ttl-blo}
A picture of the CONV-TTL-BLO mainboard is presented in Fig.~\ref{fig:conv-ttl-blo}.
This board represents the main part of the converter system; all of the active circuitry
involved in pulse repetition is present on this board. The Spartan-6 FPGA is the core part
of the board, reacting to pulses at either the TTL inputs arriving on front panels, or
blocking pulses arriving on rear panels through the RTM system, and generating pulses for
the output channels, both blocking and TTL.
\textcolor{red}{\textbf{board picture}}
\subsubsection{TTL and INV-TTL inputs}
\label{sec:ttl-inp}
TTL and INV-TTL level pulses arrive through the LEMO connectors. The pulses are passed
through a Schmitt trigger buffer circuit to smooth out transitions and then passed to the FPGA.
The buffer circuit is shown in Fig.~\ref{fig:ttl-inp} and is common to the six TTL input channels
and the four INV-TTL input channels.
\begin{figure}[h]
\begin{center}
\includegraphics[width=.85\textwidth]{Figures/ttl-inp.png}
\caption{TTL and INV-TTL input circuit}
\label{fig:ttl-inp}
\end{center}
\end{figure}
\subsubsection{STAT\_L}
Since a signal at the input can be both TTL and INV-TTL, a switch (called the \textit{LEVEL} switch)
is provided on the board to select between the two. The switch (shown in Fig.~\ref{fig:level-switch})
is checked in the FPGA logic and the output pulse per each channel is adjusted according to its status.
\begin{table}[H]
%\caption{STAT\_L register}
%\label{tbl:reg-statl}
\centerline
{
\begin{tabular}{r c c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Reset} & \multicolumn{1}{c}{Description} \\
\hline
31..0 & IDENT\_L & 0x00000000 & Lower 32 bits of board identity, as provided by Maxim DS18B20U+ thermometer \\
\hline
\end{tabular}
}
\end{table}
As can be seen in Fig.~\ref{fig:level-switch}, when the switch is in the upper position, it indicates
that the signal on TTL and INV-TTL inputs is TTL level. When the switch is in the lower position,
this indicates an INV-TTL level at TTL and INV-TTL inputs.
\textcolor{red}{\textbf{LEVEL switch pic}}
A board can only have TTL \textit{or} INV-TTL inputs at one time on \textit{any} channel, not both.
The LEVEL switch indicates which of the two it is. Since there is only one LEVEL switch on CONV-TTL-BLO
boards, it is not possible to set the type of signal per each channel.
\subsubsection{STAT\_H}
\subsubsection{Blocking inputs}
\label{sec:blo-inp}
\begin{table}[H]
%\caption{STAT\_H register}
%\label{tbl:reg-stath}
\centerline
{
\begin{tabular}{r c c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Reset} & \multicolumn{1}{c}{Description} \\
\hline
15..0 & IDENT\_H & 0x0000 & Upper 32 bits of board identity, as provided by Maxim DS18B20U+ thermometer \\
18..16 & RTMM & "000" & Rear transition module mainboard (RTMM) identification \cite{rtm-ident} \\
21..19 & RTMP & "000" & Rear transition module piggyback (RTMP) identification \cite{rtm-ident} \\
31..22 & \textit{unimplemented} & -- & Unimplemented bits, read undefined, write as '0' \\
\hline
\end{tabular}
}
\end{table}
After their arrival in the rear panel through the RTMP LEMO connectors, blocking pulses pass through an
input circuit, shown in Fig.~\ref{fig:blo-inp}. This circuit's function is to adjust the voltage level
of the blocking pulse to a level more suitable for input to the FPGA. A transient voltage suppressing
diode at the input offers protection against any voltage spikes at the input, while the optocoupler
provides the voltage adjustment.
\begin{figure}[h]
\begin{center}
\includegraphics[width=\textwidth]{Figures/blo-inp.png}
\caption{Blocking input circuit}
\label{fig:blo-inp}
\end{center}
\end{figure}
\subsubsection{I2C\_CTR0}
\begin{table}[H]
%\caption{I2C\_CTR0 register}
%\label{tbl:reg-i2c-ctr0}
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
0 & I2C\_OP & '0' & I$^2$C operation, unused bit \\
7..1 & I2C\_ADDR & see Sec. \ref{sec:brd-addressing} & I$^2$C address of the CONV-TTL-BLO board \\
11..8 & BIA & 0x2 & Bytes of Indirect Addressing \\
19..12 & BRD & 0x4 & Bytes to be read from FPGA \\
27..20 & BWR & 0x4 & Bytes to be written to FPGA \\
31..28 & \textit{unimplemented} & -- & Unimplemented bits, read undefined, write as '0' \\
\hline
\end{tabular}
}
\end{table}
Signal levels expected at the input match those of the blocking standard definition \cite{StandardBlocking}.
\textcolor{red}{\textbf{The minimum signal level that the optocoupler is sensitive to is 5~V.}}
\subsubsection{I2C\_LT}
\begin{table}[H]
%\caption{I2C\_LT register}
%\label{tbl:reg-i2c-ctr0}
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
7..0 & WBCP & 20 & WishBone Clock Period, in ns \\
31..8 & SCLP & 0x000000 & SCL Period \\
\hline
\end{tabular}
}
\end{table}
The output of this circuit is further passed through a Schmitt-trigger buffer to smooth out transitions.
Since the buffer is the same inverting buffer present in the TTL input circuits, the inverted pulse signal
coming out of the circuit in Fig.~\ref{fig:blo-inp} is once again inverted, and the FPGA receives the
recovered pulse signal in normal polarity.
\subsubsection{I2C\_DTX}
\begin{table}[H]
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
31..0 & DTX & 0x00000000 & DTX register bits \\
\hline
\end{tabular}
}
\end{table}
\subsubsection{Blocking outputs}
\label{sec:blo-outp}
The blocking output circuit is shown in Fig.~\ref{fig:blo-outp}. The circuit is a typical flyback topology \cite{flyback},
with the Coilcraft inductor providing a galvanically isolated pulse at the output. Rise and fall times of
the pulse signals are controlled mainly by the resistors at the gate of the MOSFET transistor.
\subsubsection{I2C\_DRXA}
\textcolor{red}{\textbf{operation}}
\begin{table}[H]
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
31..0 & DRXA & 0x00000000 & DRXA register bits \\
\hline
\end{tabular}
}
\end{table}
\textcolor{red}{\textbf{snubber circuit design}}
\subsubsection{I2C\_DRXB}
\textcolor{red}{\textbf{max pulse length on the circuit}}
\begin{table}[H]
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
31..0 & DRXB & 0x00000000 & DRXB register bits \\
\hline
\end{tabular}
}
\end{table}
\begin{figure}[h]
\begin{center}
\includegraphics[width=\textwidth]{Figures/blo-outp.png}
\caption{Blocking output circuit}
\label{fig:blo-outp}
\end{center}
\end{figure}
%======================================================================================
% SEC: FPGA Logic
%======================================================================================
\section{FPGA Logic}
\label{sec:fpga-logic}
%======================================================================================
% SEC: Internal regs
%======================================================================================
%\pagebreak
%\section{Accessing internal registers}
%\label{sec:internal-regs}
%
%\subsection{ELMA crates}
%CONV-TTL-BLO boards have been designed to operate in ELMA crates. These crates provide a
%back plane with VME64x connectors which boards can be plugged into. A dedicated board inside the
%ELMA crates called the SysMon (System Monitor) monitors overall system status and provides access
%to boards plugged into the VME back plane.
%
%The user can connect to SysMon boards either through a simple RS-232 interface, or through Telnet.
%In order to send commands to a board plugged into an ELMA crate, the user would connect to the SysMon
%over one of these two interfaces and send \verb=readreg= and \verb=writereg= commands to
%board-specific registers, as exemplified in Section \ref{sec:getting-started} to control their functioning.
%
%%Since it is the interface most experimented with up to the point of writing of this document,
%%only the Telnet interface is used throughout this document.
%
%\subsection{Board Addressing}
%\label{sec:brd-addressing}
%
%Communication with the CONV-TTL-BLO FPGA is done via I$^2$C interface through the SERA and SERB pins
%in P1 VME64x connectors. In order to access a CONV-TTL-BLO board, it is necessary to send:
%
%\begin{itemize}
% \item The board's 7-bit I$^2$C address. Every CONV-TTL-BLO has an address that prepends two bits
% of value \textit{10} to the Geographical Address of the slot according to VME64x specifications.
% \item An internal CONV-TTL-BLO register address. It is a 16-bit integer in \textit{little endian} format
% (most significant byte is sent first).
%\end{itemize}
%
%After this, four bytes of data are read/written from/to the internal CONV-TTL-BLO register. These
%four bytes of data are written in \textit{big endian} format (least significant byte is sent first).
%
%The addressing protocol is thoroughly described in \cite{sysmon-i2c}. The SysMon acts as a master on the
%I$^2$C interface and has the protocol implemented as software on the on-board processor. The FPGAs on
%CONV-TTL-BLO boards implement an I$^2$C slave and decode the data streams sent by the SysMon.
%
%
%\subsection{CONV-TTL-BLO memory map}
%\label{sec:memmap}
%
%Table \ref{tbl:memmap} summarizes the registers mapping in the current version of the CONV-TTL-BLO firmware.
%The first column represents the Wishbone address internal to the FPGA firmware and the second column represents
%the ELMA register address (in \verb=readreg= and \verb=writereg= commands).
%
%\begin{table}[!hbtp]
%\caption{Memory map of the CONV-TTL-BLO design}
%\label{tbl:memmap}
%\centerline
%{
% \begin{tabular}{ r r l c p{.5\textwidth} }
% \hline
% \multicolumn{1}{c}{Address} & \multicolumn{1}{c}{ELMA} & \multicolumn{1}{c}{Name} & \multicolumn{1}{c}{Access} & \multicolumn{1}{c}{Description} \\
% \hline
% 0x00 & 1 & STAT\_L & R & Lower 32 bits of system status register \\
% 0x04 & 2 & STAT\_H & R & Upper 32 bits of system status register \\
% 0x40 & 17 & I2C\_CTR0 & R & I$^2$C control register \\
% 0x44 & 18 & I2C\_LT & R & I$^2$C line timing register, provides the current I$^2$C line speed \\
% 0x48 & 19 & I2C\_DTX & R/W & Data to transmit through the I$^2$C interface \\
% 0x4C & 20 & I2C\_DRXA & R & Lower 32 bits of data received through the I$^2$C interface \\
% 0x50 & 21 & I2C\_DRXB & R & Upper 32 bits of data received through the I$^2$C interface \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsection{Register description}
%
%
%\subsubsection{STAT\_L}
%
%\begin{table}[H]
%%\caption{STAT\_L register}
%%\label{tbl:reg-statl}
%\centerline
%{
% \begin{tabular}{r c c p{.6\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Reset} & \multicolumn{1}{c}{Description} \\
% \hline
% 31..0 & IDENT\_L & 0x00000000 & Lower 32 bits of board identity, as provided by Maxim DS18B20U+ thermometer \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%
%
%\subsubsection{STAT\_H}
%
%\begin{table}[H]
%%\caption{STAT\_H register}
%%\label{tbl:reg-stath}
%\centerline
%{
% \begin{tabular}{r c c p{.6\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Reset} & \multicolumn{1}{c}{Description} \\
% \hline
% 15..0 & IDENT\_H & 0x0000 & Upper 32 bits of board identity, as provided by Maxim DS18B20U+ thermometer \\
% 18..16 & RTMM & "000" & Rear transition module mainboard (RTMM) identification \cite{rtm-ident} \\
% 21..19 & RTMP & "000" & Rear transition module piggyback (RTMP) identification \cite{rtm-ident} \\
% 31..22 & \textit{unimplemented} & -- & Unimplemented bits, read undefined, write as '0' \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%
%\subsubsection{I2C\_CTR0}
%\begin{table}[H]
%%\caption{I2C\_CTR0 register}
%%\label{tbl:reg-i2c-ctr0}
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 0 & I2C\_OP & '0' & I$^2$C operation, unused bit \\
% 7..1 & I2C\_ADDR & see Sec. \ref{sec:brd-addressing} & I$^2$C address of the CONV-TTL-BLO board \\
% 11..8 & BIA & 0x2 & Bytes of Indirect Addressing \\
% 19..12 & BRD & 0x4 & Bytes to be read from FPGA \\
% 27..20 & BWR & 0x4 & Bytes to be written to FPGA \\
% 31..28 & \textit{unimplemented} & -- & Unimplemented bits, read undefined, write as '0' \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsubsection{I2C\_LT}
%\begin{table}[H]
%%\caption{I2C\_LT register}
%%\label{tbl:reg-i2c-ctr0}
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 7..0 & WBCP & 20 & WishBone Clock Period, in ns \\
% 31..8 & SCLP & 0x000000 & SCL Period \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsubsection{I2C\_DTX}
%\begin{table}[H]
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 31..0 & DTX & 0x00000000 & DTX register bits \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsubsection{I2C\_DRXA}
%
%\begin{table}[H]
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 31..0 & DRXA & 0x00000000 & DRXA register bits \\
% \hline
% \end{tabular}
%}
%\end{table}
%
%\subsubsection{I2C\_DRXB}
%
%\begin{table}[H]
%\centerline
%{
% \begin{tabular}{r c c p{.5\textwidth}}
% \hline
% \multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
% \hline
% 31..0 & DRXB & 0x00000000 & DRXB register bits \\
% \hline
% \end{tabular}
%}
%\end{table}
......
hdl/pulse_generator/rtl/pulse_generator.vhd
View file @ 222e55cc
......@@ -75,8 +75,9 @@ architecture behav of pulse_generator is
-- Pulse length counter
signal width_cnt : unsigned(f_log2_size(g_pulse_width)-1 downto 0);
-- Pulse and trigger
-- Pulse-specific signals
signal pulse : std_logic;
signal pulse_reject : std_logic;
-- Glitch filter
signal glitch_filt : std_logic_vector(g_glitch_filt_len downto 0);
......@@ -90,7 +91,8 @@ begin
--============================================================================
-- Output logic
--============================================================================
pulse_o <= pulse or trig_i;
pulse_o <= trig_i when (pulse_reject = '0') else
pulse;
--============================================================================
-- Glitch filtration logic
......@@ -131,7 +133,6 @@ begin
if (pulse = '1') then
width_cnt <= width_cnt + 1;
-- Reset pulse length counter and clear output pulse when reached max
-- length. The max length is given by the module input, minus the
-- glitch filter length (due to the flip-flops the pulse goes through).
......@@ -150,6 +151,32 @@ begin
end if;
end process p_gen_pulse;
-- This process is used to reject pulses longer than the pulse width defined
-- via the generic. This safeguards the blocking output transformers from
-- reaching saturation current when an INV-TTL signal is applied at the TTL
-- input without setting the LEVEL switch appropriately. It also guards the
-- transformers when no signal is present at the TTL input and the LEVEL switch
-- is set to INV-TTL.
--
-- When the pulse signal is set, the pulse_reject signal is also set. The
-- pulse_reject signal is cleared when the pulse input has settled back to '0'.
--
-- By using the pulse_reject signal as an enable for the output, the pulse output
-- width is cut to the desired size.
p_pulse_reject: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_reject <= '1';
elsif (pulse = '1') then
pulse_reject <= '1';
elsif (trig_i = '0') then
pulse_reject <= '0';
end if;
end if;
end process p_pulse_reject;
end architecture behav;
--==============================================================================
-- architecture end
......
hdl/pulse_generator/sim/testbench.vhd
View file @ 222e55cc
......@@ -150,8 +150,8 @@ begin
rst_n_i => rst_n,
pulse_o => trig
);
actual_trig <= trig; -- when lvl = '0' else not trig;
actual_pulse <= pulse; -- when lvl = '0' else not pulse;
actual_trig <= '1'; --trig;
actual_pulse <= pulse;
lvl_n <= not lvl;
......
hdl/pulse_generator/sim/transcript
View file @ 222e55cc
......@@ -65,15 +65,500 @@ do run.do
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# ** Error: (vish-4014) No objects found matching '/testbench/DUT/pulse_len_i'.
# Executing ONERROR command at macro ./wave.do line 10
# ** Error: (vish-4014) No objects found matching '/testbench/DUT/len_cnt'.
# Executing ONERROR command at macro ./wave.do line 11
# ** Error: (vish-4014) No objects found matching '/testbench/DUT/pulse_len'.
# Executing ONERROR command at macro ./wave.do line 12
# ** Error: (vish-4014) No objects found matching '/testbench/DUT/trig'.
# Executing ONERROR command at macro ./wave.do line 15
# ** Error: (vish-4014) No objects found matching '/testbench/DUT/level_i'.
# Executing ONERROR command at macro ./wave.do line 16
# 0 ps
# 105 us
add wave \
sim:/testbench/DUT/pulse_reject
restart; run 100 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
add wave \
sim:/testbench/DUT/pulse_reject
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/hdl/pulse_generator/sim/wave.do
restart; run 100 us
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.pulse_gen(behav)#1
# hexadecimal
# 0 ps
# 105 us
hdl/pulse_generator/sim/wave.do
View file @ 222e55cc
......@@ -5,15 +5,10 @@ add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/trig
add wave -noupdate /testbench/actual_trig
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/actual_pulse
add wave -noupdate -divider internal
add wave -noupdate /testbench/DUT/pulse_len_i
add wave -noupdate /testbench/DUT/len_cnt
add wave -noupdate /testbench/DUT/pulse_len
add wave -noupdate /testbench/DUT/pulse
add wave -noupdate /testbench/DUT/glitch_filt
add wave -noupdate /testbench/DUT/trig
add wave -noupdate /testbench/DUT/level_i
add wave -noupdate /testbench/DUT/pulse
add wave -noupdate /testbench/DUT/pulse_reject
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {12112676 ps} 0}
configure wave -namecolwidth 233
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 222e55cc
......@@ -104,11 +104,13 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362654810" xil_pn:in_ck="-4590833482063591864" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1362654798">
<transform xil_pn:end_ts="1362750559" xil_pn:in_ck="-4590833482063591864" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1362750547">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.lso"/>
......@@ -126,18 +128,20 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1362654831" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1362654825">
<transform xil_pn:end_ts="1362750565" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1362750559">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bld"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1362654860" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1362654831">
<transform xil_pn:end_ts="1362750592" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1362750565">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -150,9 +154,10 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1362654888" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1362654860">
<transform xil_pn:end_ts="1362750623" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1362750592">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ncd"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pad"/>
......@@ -164,9 +169,10 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1362654907" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1362654888">
<transform xil_pn:end_ts="1362750641" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1362750623">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bgn"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bit"/>
......@@ -175,15 +181,26 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1362654919" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1362654919">
<transform xil_pn:end_ts="1362751327" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-4173336264699367391" xil_pn:start_ts="1362751327">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1362654888" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1362654881">
<transform xil_pn:end_ts="1362750641" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1362750641">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/>
</transform>
<transform xil_pn:end_ts="1362750623" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1362750614">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twr"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twx"/>
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 222e55cc
......@@ -323,22 +323,9 @@ begin
);
end generate gen_ttl_pulse_generators;
cmp_tmp_pulse_gen: pulse_gen
generic map
(
g_pwidth => 125,
g_freq => 125*(10**6)
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
pulse_o => tmp_pulse
);
-- Pulse outputs assignment
FPGA_OUT_TTL <= pulse_outputs;
FPGA_TRIG_BLO <= (others => '0'); -- pulse_outputs;
FPGA_TRIG_BLO <= pulse_outputs;
-- Pulse status LEDs assignments
PULSE_FRONT_LED_N <= (not pulse_leds) when (ttl_oe = '1') else
......@@ -373,6 +360,19 @@ begin
-- Output assignment
INV_OUT <= not inv_outputs;
cmp_tmp_pulse_gen: pulse_gen
generic map
(
g_pwidth => 100,
g_freq => 125*(10**6)
)
port map
(
clk_i => clk_125,
rst_n_i => rst_n,
pulse_o => tmp_pulse
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
......
installation/V2/basic_trigger/project/basic_trigger_v2.gise
View file @ 222e55cc
......@@ -22,167 +22,9 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="basic_trigger_v2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="basic_trigger_v2_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="basic_trigger_v2_top.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="basic_trigger_v2_top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="basic_trigger_v2_top.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="basic_trigger_v2_top.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="basic_trigger_v2_top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="basic_trigger_v2_top.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="basic_trigger_v2_top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="basic_trigger_v2_top.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="basic_trigger_v2_top.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="basic_trigger_v2_top.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="basic_trigger_v2_top.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="basic_trigger_v2_top.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="basic_trigger_v2_top.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="basic_trigger_v2_top.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="basic_trigger_v2_top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="basic_trigger_v2_top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="basic_trigger_v2_top.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="basic_trigger_v2_top.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="basic_trigger_v2_top.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="basic_trigger_v2_top.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="basic_trigger_v2_top.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="basic_trigger_v2_top.xst"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="basic_trigger_v2_top_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="basic_trigger_v2_top_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="basic_trigger_v2_top_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="basic_trigger_v2_top_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="basic_trigger_v2_top_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="basic_trigger_v2_top_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="basic_trigger_v2_top_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="basic_trigger_v2_top_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="basic_trigger_v2_top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="basic_trigger_v2_top_par.xrpt"/>
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installation/V2/basic_trigger/project/basic_trigger_v2_top_guide.ncd
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installation/V2/basic_trigger/project/basic_trigger_v2_top_summary.html
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......@@ -2,436 +2,57 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>basic_trigger_v2_top Project Status (02/06/2013 - 18:11:23)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>basic_trigger_v2_top Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>basic_trigger_v2.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>basic_trigger_v2_top</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Programming File Generated</TD>
<TD>New (Stopped)</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/*.xmsgs?&DataKey=Warning'>616 Warnings (616 new, 0 filtered)</A></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.unroutes'>All Signals Completely Routed</A></TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top_envsettings.html'>
System Settings</A>
</TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>0 &nbsp;<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
<TD>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>283</TD>
<TD ALIGN=RIGHT>54,576</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>283</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>648</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT>2%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>625</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT>2%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>341</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>181</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>103</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>6,408</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Dual Port RAM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Single Port RAM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as Shift Register</TD>
<TD ALIGN=RIGHT>8</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>8</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>15</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>3</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
<TD ALIGN=RIGHT>12</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>220</TD>
<TD ALIGN=RIGHT>6,822</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Nummber of MUXCYs used</TD>
<TD ALIGN=RIGHT>416</TD>
<TD ALIGN=RIGHT>13,644</TD>
<TD ALIGN=RIGHT>3%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>678</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>402</TD>
<TD ALIGN=RIGHT>678</TD>
<TD ALIGN=RIGHT>59%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>30</TD>
<TD ALIGN=RIGHT>678</TD>
<TD ALIGN=RIGHT>4%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>246</TD>
<TD ALIGN=RIGHT>678</TD>
<TD ALIGN=RIGHT>36%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>19</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>29</TD>
<TD ALIGN=RIGHT>54,576</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>65</TD>
<TD ALIGN=RIGHT>296</TD>
<TD ALIGN=RIGHT>21%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>65</TD>
<TD ALIGN=RIGHT>65</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>116</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>232</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>25%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
<TD ALIGN=RIGHT>4</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
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<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>256</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>58</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of GTPA1_DUALs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCIE_A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>25%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>2.83</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0, Component Switching Limit: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
......@@ -439,20 +60,19 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Wed Feb 6 10:03:57 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/xst.xmsgs?&DataKey=Warning'>616 Warnings (616 new, 0 filtered)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/xst.xmsgs?&DataKey=Info'>22 Infos (22 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:10:09 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:10:34 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/map.xmsgs?&DataKey=Info'>6 Infos (0 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:10:58 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:11:05 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new, 0 filtered)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Wed Feb 6 18:11:22 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Feb 6 18:11:23 2013</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/06/2013 - 18:11:23</center>
<br><center><b>Date Generated:</b> 03/08/2013 - 15:04:10</center>
</BODY></HTML>
\ No newline at end of file
installation/V2/basic_trigger/project/iseconfig/basic_trigger_v2.projectmgr
View file @ 222e55cc
......@@ -30,13 +30,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a6000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
......@@ -77,7 +77,6 @@
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode>
......@@ -89,13 +88,13 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem>Configure Target Device</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a6000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000288000000010000000100000000000000000000000064ffffffff000000810000000000000001000002880000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>Configure Target Device</CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000018e0000011d01000000060100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
......
installation/V2/basic_trigger/project/iseconfig/basic_trigger_v2_top.xreport
View file @ 222e55cc
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2013-02-06T18:10:02</DateModified>
<DateModified>2013-03-08T15:04:10</DateModified>
<ModuleName>basic_trigger_v2_top</ModuleName>
<SummaryTimeStamp>2013-01-18T14:24:50</SummaryTimeStamp>
<SummaryTimeStamp>2013-03-08T15:04:04</SummaryTimeStamp>
<SavedFilePath>/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/basic_trigger_v2_top.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/</ImplementationReportsDirectory>
<DateInitialized>2013-01-16T17:50:04</DateInitialized>
......
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