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Commit 3f7fd876 authored by gilsoriano's avatar gilsoriano
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Stable version of the test of white rabbit. It works. Accessible via UART in extra header pins.

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hdl/wr_core_demo/Manifest.py deleted 100755 → 0
View file @ 428f322e
fetchto = "ip_cores"
modules = {"local" :
[ "platform",
"modules/fabric",
"modules/mini_bone",
"modules/wr_tbi_phy",
"modules/timing",
"modules/wr_mini_nic",
"modules/wr_softpll_ng",
"modules/wr_endpoint",
"modules/wr_pps_gen",
"modules/wrc_core" ],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master"
}
hdl/wr_core_demo/constraints/FPGAbank.ucf
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hdl/wr_core_demo/project/Manifest.py deleted 100755 → 0
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target = "xilinx"
action = "synthesis"
fetchto = "../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "wr_ep"
syn_project = "wr_ep.xise"
modules = { "local" : ["../rtl"]}
hdl/wr_core_demo/project/wr_ep.xise
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hdl/wr_core_demo/rtl/Manifest.py
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files = ["wr_ep.vhd", "wr_ep.ucf", "spec_serial_dac.vhd", "spec_serial_dac_arb.vhd", "wb_gpio_port_notristates.vhd"]
fetchto = "ip_cores"
fetchto = "../ip_cores"
modules = {
"local" : [".."]
}
modules = {"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git",
"git@ohwr.org:hdl-core-lib/wr-cores.git"]}
hdl/wr_core_demo/rtl/install 0 → 100755
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impact -batch install.cmd
hdl/wr_core_demo/rtl/install.cmd 0 → 100755
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setMode -bs
setCable -port auto
identify
assignFile -p 1 -file "/home/carlos/blo/hdl/wr_core_demo/rtl/syn/wr_ep.bit"
Program -p 1
quit
hdl/wr_core_demo/rtl/platform/Manifest.py 0 → 100755
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if target=="altera":
modules = {"local" : "altera"}
elif target=="xilinx":
modules = {"local" : "xilinx"}
\ No newline at end of file
hdl/wr_core_demo/rtl/platform/altera/Manifest.py 0 → 100755
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files = [ "altera_pkg.vhd", "flash_loader.vhd", "pow_reset.vhd" ]
modules = {"local":"wr_gxb_phy_arria2"}
\ No newline at end of file
hdl/wr_core_demo/rtl/platform/altera/altera_pkg.vhd 0 → 100755
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library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
package wr_altera_pkg is
component flash_loader
port (
noe_in : in std_logic
);
end component;
component pow_reset is
port (
clk : in std_logic; -- 125Mhz
nreset : buffer std_logic
);
end component;
component dmtd_clk_pll
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end component;
component sys_pll
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic;
c1 : out std_logic;
locked : out std_logic
);
end component;
component wr_gxb_phy_arriaii
generic (
g_simulation : integer;
g_force_disparity : integer);
port (
clk_reconf_i : in std_logic;
clk_ref_i : in std_logic;
tx_clk_o : out std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_k_i : in std_logic;
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0);
rx_k_o : out std_logic;
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(3 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic;
pad_txp_o : out std_logic;
pad_rxp_i : in std_logic := '0');
end component;
end wr_altera_pkg;
hdl/wr_core_demo/rtl/platform/altera/ddr3/Micron MT41J64M16LA-15E.xml 0 → 100755
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<?xml version="1.0" encoding="UTF-8"?>
<preset name="Micron MT41J64M16LA-15E">
<parameter name="mem_if_memtype" value="DDR3 SDRAM" />
<parameter name="vendor" value="Micron" />
<parameter name="chip_or_dimm" value="Discrete Device" />
<parameter name="mem_fmax" value="666.666" />
<parameter name="mem_if_coladdr_width" value="10" />
<parameter name="mem_if_rowaddr_width" value="13" />
<parameter name="mem_if_bankaddr_width" value="3" />
<parameter name="mem_if_clk_pair_count" value="1" />
<parameter name="mem_if_cs_per_dimm" value="1" />
<parameter name="mem_if_cs_per_rank" value="1" />
<parameter name="mem_if_cs_width" value="1" />
<parameter name="mirror_addressing" value="0" />
<parameter name="register_control_word_size" value="4" />
<parameter name="register_control_word_0" value="0000" />
<parameter name="register_control_word_1" value="0000" />
<parameter name="register_control_word_2" value="0000" />
<parameter name="register_control_word_3" value="0000" />
<parameter name="register_control_word_4" value="0000" />
<parameter name="register_control_word_5" value="0000" />
<parameter name="register_control_word_6" value="0000" />
<parameter name="register_control_word_7" value="0000" />
<parameter name="register_control_word_8" value="0000" />
<parameter name="register_control_word_9" value="0000" />
<parameter name="register_control_word_10" value="0000" />
<parameter name="register_control_word_11" value="0000" />
<parameter name="register_control_word_12" value="0000" />
<parameter name="register_control_word_13" value="0000" />
<parameter name="register_control_word_14" value="0000" />
<parameter name="register_control_word_15" value="0000" />
<parameter name="mem_if_dq_per_dqs" value="8" />
<parameter name="mem_if_dwidth" value="8" />
<parameter name="mem_if_dm_pins_en" value="Yes" />
<parameter name="mem_if_tinit_us" value="500.0" />
<parameter name="dss_tinit_rst_us" value="200.0" />
<parameter name="mem_if_tmrd_ns" value="6.0" />
<parameter name="mem_if_tras_ns" value="36.0" />
<parameter name="mem_if_trcd_ns" value="13.5" />
<parameter name="mem_if_trp_ns" value="13.5" />
<parameter name="mem_if_trefi_us" value="7.8" />
<parameter name="mem_if_trfc_ns" value="110.0" />
<parameter name="mem_if_twr_ns" value="15.0" />
<parameter name="mem_if_twtr_ck" value="4" />
<parameter name="mem_tdqsck_ps" value="255" />
<parameter name="mem_tdqsq_ps" value="125" />
<parameter name="mem_tdqss_ck" value="0.25" />
<parameter name="mem_tdha_ps" value="165" />
<parameter name="mem_tdsa_ps" value="180" />
<parameter name="mem_tdsh_ck" value="0.2" />
<parameter name="mem_tdss_ck" value="0.2" />
<parameter name="mem_tiha_ps" value="240" />
<parameter name="mem_tisa_ps" value="340" />
<parameter name="mem_tqh_ck" value="0.38" />
<parameter name="mem_tfaw_ns" value="30.0" />
<parameter name="mem_trrd_ns" value="6.0" />
<parameter name="mem_trtp_ns" value="7.5" />
<parameter name="mem_bl" value="On the fly" />
<parameter name="mem_btype" value="Sequential" />
<parameter name="mem_dll_pch" value="Fast exit" />
<parameter name="mem_dll_en" value="Yes" />
<parameter name="mem_rtt_nom" value="ODT Disabled" />
<parameter name="mem_rtt_wr" value="Dynamic ODT off" />
<parameter name="mem_drv_impedance" value="RZQ/7" />
<parameter name="mem_tcl" value="9.0" />
<parameter name="mem_atcl" value="Disabled" />
<parameter name="mem_wtcl" value="7.0" />
<parameter name="mem_pasr" value="Full Array" />
<parameter name="mem_asrm" value="Manual SR Reference (SRT)" />
<parameter name="mem_srtr" value="Normal" />
<parameter name="mem_tcl_50_fmax" value="333.333" />
<parameter name="mem_tcl_60_fmax" value="400.0" />
<parameter name="mem_tcl_70_fmax" value="533.333" />
<parameter name="mem_tcl_80_fmax" value="533.333" />
<parameter name="mem_tcl_90_fmax" value="666.666" />
<parameter name="mem_tcl_100_fmax" value="666.666" />
</preset>
hdl/wr_core_demo/rtl/platform/altera/ddr3/alt_mem_ddrx_buffer.v 0 → 100755
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module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
hdl/wr_core_demo/rtl/platform/altera/ddr3/alt_mem_ddrx_buffer_manager.v 0 → 100755
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module alt_mem_ddrx_buffer_manager
# (
parameter
CFG_BUFFER_ADDR_WIDTH = 6
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
writeif_ready,
writeif_valid,
writeif_address,
writeif_address_blocked,
// buffer write interface
buffwrite_valid,
buffwrite_address,
// read interface
readif_valid,
readif_address,
// buffer read interface
buffread_valid,
buffread_datavalid,
buffread_address
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_BUFFER_DEPTH = two_pow_N(CFG_BUFFER_ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
output writeif_ready;
input writeif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
input writeif_address_blocked;
// buffer write interface
output buffwrite_valid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
input readif_valid;
input [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
output buffread_valid;
output buffread_datavalid;
output [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
reg writeif_ready;
wire writeif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] writeif_address;
wire writeif_address_blocked;
// buffer write interface
wire buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffwrite_address;
// read data interface
wire readif_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] readif_address;
// buffer read interface
wire buffread_valid;
reg buffread_datavalid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] buffread_address;
// -----------------------------
// signal declaration
// -----------------------------
wire writeif_accepted;
reg [CTL_BUFFER_DEPTH-1:0] mux_writeif_ready;
reg [CTL_BUFFER_DEPTH-1:0] buffer_valid_array;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter;
reg err_buffer_valid_counter_overflow;
// -----------------------------
// module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
//
// assert
//
// - write & read to same location happen on same time
hdl/wr_core_demo/rtl/platform/altera/ddr3/alt_mem_ddrx_csr.v 0 → 100755
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hdl/wr_core_demo/rtl/platform/altera/ddr3/alt_mem_ddrx_define.iv 0 → 100755
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//--------------------------------------------------------------------------------------------------------
//
// [START] MMR - Memory Mapped Register Definition
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Generic Signals
//----------------------------------------------------------------------------------------------------
// cfg_type
`define MMR_TYPE_DDR1 3'b000
`define MMR_TYPE_DDR2 3'b001
`define MMR_TYPE_DDR3 3'b010
`define MMR_TYPE_LPDDR1 3'b011
`define MMR_TYPE_LPDDR2 3'b100
//----------------------------------------------------------------------------------------------------
// Address Mapping Signals
//----------------------------------------------------------------------------------------------------
// cfg_addr_order
`define MMR_ADDR_ORDER_CS_ROW_BA_COL 2'b00
`define MMR_ADDR_ORDER_CS_BA_ROW_COL 2'b01
`define MMR_ADDR_ORDER_ROW_CS_BA_COL 2'b10
//--------------------------------------------------------------------------------------------------------
//
// [END] MMR - Memory Mapped Register Definition
//
//--------------------------------------------------------------------------------------------------------
hdl/wr_core_demo/rtl/platform/altera/ddr3/alt_mem_ddrx_fifo.v 0 → 100755
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hdl/wr_core_demo/rtl/platform/altera/ddr3/alt_mem_ddrx_list.v 0 → 100755
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hdl/wr_core_demo/rtl/platform/altera/ddr3/alt_mem_ddrx_tbp.v 0 → 100755
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hdl/wr_core_demo/rtl/platform/altera/ddr3/ddr3_mem.html 0 → 100755
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN">
<HTML>
<HEAD>
<STYLE type="text/css">
A.h:hover { color: "#FF0000"; }
A.menu:link { text-decoration: none}
A.menu:visited{ text-decoration: none}
A.menu:hover {color: #EE9B06;}
A.submenu:link { text-decoration: none;}
A.submenu:visited { text-decoration: none}
A.submenu:hover {color: #EE9B06;}
div.category { border-bottom: 5px, solid, black; }
br.submenu { line-height: 1em;}
br.submenu { line-height: 7px;}
BODY, H1, H2, H3, H4, TD, TH, UL, OL, LI, P, DD, DT, DL, INPUT, SELECT, SPAN { font-family : SansSerif, Verdana, Helvetica, Arial, San-sarif; }
BODY { background-color : #e0e0e0; }
TD, UL, OL, LI, P, DD, DT, DL, SPAN { font-size: 11pt; color : black; }
BLOCKQUOTE { font-size: 10pt; color : #000099; }
TH { font-size : 11pt; font-weight : bold; font-style : normal; color : black; }
H1 { font-size : 18pt; color : black; }
H2 { font-size : 14pt; color : black; }
H3 { font-size : 12pt; color : black; }
H4 { font-size : 11pt; font-weight : bold; color : black; }
</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - DDR3 SDRAM Controller with ALTMEMPHY v11.1</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>ddr3_mem_controller_phy</TD></TR><TR><TD><B>Variation Name</B></TD><TD>ddr3_mem</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>VHDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>/home/stefan/quartus_projects/wr-hdl/platform/altera/ddr3</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>ddr3_mem.vhd</TD><TD>A MegaCore<small><sup>&reg</sup></small> function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>ddr3_mem.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>ddr3_mem.qip</TD><TD>Contains Quartus II project information for your MegaCore function variation.</TD></TR><TR><TD>ddr3_mem.html</TD><TD>The MegaCore function report file.</TD></TR><TR><TD>ddr3_mem_example_driver.vhdl</TD><TD>Example self-checking test generator that matches your variation.</TD></TR><TR><TD>ddr3_mem_example_top.vhdl</TD><TD>Example top level design file that you should set as your Quartus II project top level. Instantiates the example driver and the controller.</TD></TR><TR><TD>ddr3_mem_example_top.sdc</TD><TD>Example Synopsys Design Constraints file for paths in the example top level.</TD></TR><TR><TD>ddr3_mem_ex_lfsr8.vhdl</TD><TD>Example linear feedback shift register that is used to generate the pseudo-random test data for the example driver.</TD></TR><TR><TD>testbench | ddr3_mem_example_top_tb.vhdl</TD><TD>Example testbench that instantiates the example top level design file and the example memory model.</TD></TR><TR><TD>testbench | ddr3_mem_mem_model.vhdl</TD><TD>A simple example memory model that matches your variation.</TD></TR><TR><TD>testbench | ddr3_mem_full_mem_model.vhdl</TD><TD>Memory model that allocates memory for all available addresses.</TD></TR><TR><TD>ddr3_mem_pin_assignments.tcl</TD><TD>TCL script</TD></TR><TR><TD>ddr3_mem_advisor.ipa</TD><TD>IP Advisor file that matches your variation. Used by the IP Advisor feature in the Quartus II software.</TD></TR><TR><TD>ddr3_mem_phy.qip</TD><TD>Generated ALTMEMPHY QIP file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>local_address</TD><TD>INPUT</TD><TD>24</TD></TR><TR><TD>local_write_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_read_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_burstbegin</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_ready</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_rdata</TD><TD>OUTPUT</TD><TD>64</TD></TR><TR><TD>local_rdata_valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_wdata</TD><TD>INPUT</TD><TD>64</TD></TR><TR><TD>local_be</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>local_size</TD><TD>INPUT</TD><TD>3</TD></TR><TR><TD>local_refresh_ack</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_init_done</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>reset_phy_clk_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>dbg_addr</TD><TD>INPUT</TD><TD>13</TD></TR><TR><TD>dbg_wr</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_rd</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_cs</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_wr_data</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>dbg_rd_data</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>dbg_waitrequest</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>dll_reference_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>dqs_delay_ctrl_export</TD><TD>OUTPUT</TD><TD>6</TD></TR><TR><TD>mem_odt</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_clk</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_clk_n</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_cs_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cke</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_addr</TD><TD>OUTPUT</TD><TD>13</TD></TR><TR><TD>mem_ba</TD><TD>OUTPUT</TD><TD>3</TD></TR><TR><TD>mem_ras_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cas_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_we_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_dq</TD><TD>BIDIR</TD><TD>16</TD></TR><TR><TD>mem_dqs</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>mem_dqsn</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>mem_dm</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>mem_reset_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>global_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>pll_ref_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>phy_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>aux_full_rate_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>aux_half_rate_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>soft_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_request_n</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>
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set_false_path -from * -to [get_ports "pnf"]
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</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - ALTMEMPHY v11.1</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>ddr3_mem_phy_alt_mem_phy</TD></TR><TR><TD><B>Variation Name</B></TD><TD>ddr3_mem_phy</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>VHDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>/home/stefan/quartus_projects/wr-hdl/platform/altera/ddr3</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>ddr3_mem_phy.vhd</TD><TD>A MegaCore<small><sup>&reg</sup></small> function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>ddr3_mem_phy.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>ddr3_mem_phy.qip</TD><TD>Contains Quartus II project information for your MegaCore function variation.</TD></TR><TR><TD>ddr3_mem_phy.html</TD><TD>The MegaCore function report file.</TD></TR><TR><TD>ddr3_mem_phy_alt_mem_phy_seq_wrapper.v</TD><TD>A wrapper file that calls the sequencer file, this file is for compilation.</TD></TR><TR><TD>ddr3_mem_phy_alt_mem_phy_seq.vhd</TD><TD>Contains the sequencer used during calibration.</TD></TR><TR><TD>ddr3_mem_phy_alt_mem_phy_dq_dqs.vhd</TD><TD></TD></TR><TR><TD>ddr3_mem_phy_alt_mem_phy.v</TD><TD>Contains all modules of the ALTMEMPHY variation except for the sequencer.</TD></TR><TR><TD>ddr3_mem_phy_alt_mem_phy_pll.vhd</TD><TD>The PLL megafunction file for your ALTMEMPHY variation.</TD></TR><TR><TD>ddr3_mem_phy_pin_assignments.tcl</TD><TD>Contains I/O standard, drive strength, output enable grouping, and termination assignments for your ALTMEMPHY variation. If your top-level design pin names do not match the default pin names or a prefixed version, edit the assignments in this file.</TD></TR><TR><TD>ddr3_mem_phy_ddr_pins.tcl</TD><TD>Contains procedures used in the ddr3_mem_phy_report_timing.tcl file.</TD></TR><TR><TD>ddr3_mem_phy_report_timing.tcl</TD><TD>Script that reports timing for your ALTMEMPHY variation during compilation.</TD></TR><TR><TD>ddr3_mem_phy_report_timing_core.tcl</TD><TD>Contains procedures used in the ddr3_mem_phy_report_timing.tcl file.</TD></TR><TR><TD>ddr3_mem_phy_ddr_timing.tcl</TD><TD>Contains timing parameters for your ALTMEMPHY variation.</TD></TR><TR><TD>ddr3_mem_phy_ddr_timing.sdc</TD><TD>Contains timing constraints for your ALTMEMPHY variation.</TD></TR><TR><TD>ddr3_mem_phy_alt_mem_phy_pll.qip</TD><TD>Quartus II IP file for the ALTPLL variation, containing the files associated with the ALTPLL megafunction.</TD></TR><TR><TD>alt_mem_phy_defines.v</TD><TD>Contains constants used in the interface.</TD></TR><TR><TD>ddr3_mem_phy.ppf</TD><TD>Pin planner file for your ALTMEMPHY variation.</TD></TR><TR><TD>ddr3_mem_phy_alt_mem_phy_dq_dqs.vhd_clearbox.txt</TD><TD>Clearbox wysiwyg</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>pll_ref_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>global_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>soft_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_request_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_reset_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_dqs_burst</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>ctl_wdata_valid</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>ctl_wdata</TD><TD>INPUT</TD><TD>64</TD></TR><TR><TD>ctl_dm</TD><TD>INPUT</TD><TD>8</TD></TR><TR><TD>ctl_wlat</TD><TD>OUTPUT</TD><TD>5</TD></TR><TR><TD>ctl_addr</TD><TD>INPUT</TD><TD>26</TD></TR><TR><TD>ctl_ba</TD><TD>INPUT</TD><TD>6</TD></TR><TR><TD>ctl_cas_n</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_cke</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_cs_n</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_odt</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_ras_n</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_we_n</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_rst_n</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_mem_clk_disable</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_doing_rd</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>ctl_rdata</TD><TD>OUTPUT</TD><TD>64</TD></TR><TR><TD>ctl_rdata_valid</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>ctl_rlat</TD><TD>OUTPUT</TD><TD>5</TD></TR><TR><TD>ctl_cal_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_cal_byte_lane_sel_n</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_cal_success</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_cal_fail</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_cal_warning</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_addr</TD><TD>OUTPUT</TD><TD>13</TD></TR><TR><TD>mem_ba</TD><TD>OUTPUT</TD><TD>3</TD></TR><TR><TD>mem_cas_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cke</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cs_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_dm</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>mem_odt</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_ras_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_we_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_reset_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_clk</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_clk_n</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_dq</TD><TD>BIDIR</TD><TD>16</TD></TR><TR><TD>mem_dqs</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>mem_dqs_n</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>oct_ctl_rs_value</TD><TD>INPUT</TD><TD>14</TD></TR><TR><TD>oct_ctl_rt_value</TD><TD>INPUT</TD><TD>14</TD></TR><TR><TD>dqs_offset_delay_ctrl</TD><TD>INPUT</TD><TD>6</TD></TR><TR><TD>dqs_delay_ctrl_import</TD><TD>INPUT</TD><TD>6</TD></TR><TR><TD>dqs_delay_ctrl_export</TD><TD>OUTPUT</TD><TD>6</TD></TR><TR><TD>dll_reference_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>dbg_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_addr</TD><TD>INPUT</TD><TD>13</TD></TR><TR><TD>dbg_wr</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_rd</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_cs</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>dbg_wr_data</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>dbg_rd_data</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>dbg_waitrequest</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>aux_half_rate_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>aux_full_rate_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ddr3_mem_phy_alt_mem_phy_pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddr3_mem_phy_alt_mem_phy_pll.cmp"]
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