Serializer for SPI test. It helps the automatization of the test for the SPI core.

428f322e · gilsoriano · 44734571 · 428f322e · 428f322e
Commit 428f322e authored Aug 08, 2012 by gilsoriano
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serializer_sim.vhd hdl/m25p32/test/serializer_sim.vhd +123 -0

serializer_sim_pkg.vhd hdl/m25p32/test/serializer_sim_pkg.vhd +167 -0

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--- a/hdl/m25p32/test/serializer_sim.vhd
+++ b/hdl/m25p32/test/serializer_sim.vhd
+----------------------------------------------------------------------------------
+--
+-- Copyright CERN 2011.
+-- 
+-- This documentation describes Open Hardware and is licensed under the
+-- CERN OHL v. 1.1.
+--
+-- You may redistribute and modify this documentation under the terms of the CERN
+-- OHL v.1.1. (http://ohwr.org/cernohl).
+--
+-- This documentation is distributed WITHOUT
+-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
+-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
+-- applicable conditions.
+--
+----------------------------------------------------------------------------------
+--
+-- Company:        CERN, BE-CO-HT 
+-- Engineer:       Carlos Gil Soriano
+-- 
+-- Create Date:    17:09:09 08/08/2012
+-- Design Name:    Serializer
+-- Module Name:    serializer_sim.vhd 
+-- Project Name:   Serializer
+-- Target Devices: Spartan 6
+-- Tool versions:  Xilinx ISE 13.4
+-- Description:    Serializer to be gentlely used in simulation. No RTL model! 
+--                 This is a parametrizable serializer that improves the
+--                 readability of the test vectors in simulation and
+--                 verification.
+--
+-- Dependencies: 
+--
+-- Revision: 0.1
+--   0.01          + File Created
+--                 
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+library work;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.serializer_sim_pkg.ALL;
+
+entity serializer_sim is
+   generic(
+       g_SERIAL_LENGTH         : NATURAL := c_SERIAL_LENGTH;
+       g_PARALLEL_LENGTH       : NATURAL := c_PARALLEL_LENGTH;
+   ); port(
+       rst_i                : in  STD_LOGIC;
+       enable_i             : in  STD_LOGIC;
+       serial_data_i        : in  STD_LOGIC_VECTOR (c_SERIAL_LENGTH - 1   downto 0); 
+       serial_clock_i       : in  STD_LOGIC;
+
+       clk_i                : in  STD_LOGIC;
+       serial_frame_rcved_o : out STD_LOGIC;
+       parallel_frame_o     : out STD_LOGIC_VECTOR (8*c_PARALLEL_LENGTH - 1 downto 0)
+   );
+end serializer_sim;
+
+architecture Behavioral of serializer_sim is
+
+   signal s_inst    :     inst_parallel;
+   signal s_addr    :     addr_parallel;
+   signal s_data    :     data_parallel;
+
+   signal s_counter :   INTEGER;
+   signal reset_cnt :   STD_LOGIC;
+
+begin
+
+   parallel_frame_o(parallel_data_o'length - 1 downto parallel_data_o'length - 1
+                                           - inst_parallel'a_length) <= s_inst;
+   parallel_frame_o(parallel_data_o'length - parallel_inst'a_length - 1
+                                               downto parallel_data_o'length - 1
+                                           - inst_parallel'a_length
+                                           - addr_parallel'a_length) <= s_addr;
+   parallel_frame_o(data_parallel_o'length - 1 downto 0)             <= s_data;
+
+
+   p_serial_clock :process(serial_clock_i, reset_cnt)
+   begin
+      --! We attended the reset strobe from the fast clk domain and reset the
+      --! counter.
+      if reset_cnt = '1' then
+         s_inst        <= c_inst_paralell_default;
+         s_addr        <= c_addr_paralell_default;
+         s_data        <= c_data_paralell_default;
+         s_counter     <= 0;
+      end if;
+
+      if rising_edge(serial_clock_i) then
+         s_counter <= s_counter + 1;
+         --! We capture the signal at the sampling time
+         if s_counter < 8*c_SIZE_BLOCKS(0) then
+            s_inst.inst(8*c_s_counter)                            <= serial_data_i;
+         elsif   (s_counter <  8*(c_SIZE_BLOCKS(1)+c_SIZE_BLOCKS(0))
+            and  (s_counter >= 8* c_SIZE_BLOCKS(0))                  then
+            s_addr.inst(s_counter - 8* c_SIZE_BLOCKS(0))      <= serial_data_i;
+         else
+            s_data.inst(s_counter - 8*(c_SIZE_BLOCKS(1) + c_SIZE_BLOCKS(0)))
+                                                              <= serial_data_i;
+         end if;
+      else
+      end if;
+   end process;
+
+
+   --! This process only targets for placing a reset in the other domain.
+   --! It was thought in the synthesizable way (which means this is the
+   --! registered process and the combinatorial part is placed in the process
+   --! above).
+   p_clk :process(clk_i)
+   begin
+      if rising_edge(clk_i) then
+         reset_cnt  <= '0';
+         if rst_i = '1' then
+            reset_cnt <= '1';
+         end if;
+      end if;
+   end process;
+end Behavioral;
--- a/hdl/m25p32/test/serializer_sim_pkg.vhd
+++ b/hdl/m25p32/test/serializer_sim_pkg.vhd
+----------------------------------------------------------------------------------
+--
+-- Copyright CERN 2011.
+-- 
+-- This documentation describes Open Hardware and is licensed under the
+-- CERN OHL v. 1.1.
+--
+-- You may redistribute and modify this documentation under the terms of the CERN
+-- OHL v.1.1. (http://ohwr.org/cernohl).
+--
+-- This documentation is distributed WITHOUT
+-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
+-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
+-- applicable conditions.
+--
+----------------------------------------------------------------------------------
+--
+-- Company:        CERN, BE-CO-HT 
+-- Engineer:       Carlos Gil Soriano
+-- 
+-- Create Date:   17:09:09 08/08/2012                                          
+-- Design Name:   Serializer package for simulation
+-- Module Name:   serializer_sim_pkg.vhd  
+-- Project Name:  Serializer                                                   
+-- Target Devices:Spartan 6                                                    
+-- Tool versions: Xilinx ISE 13.4                                              
+-- Description:   This is a parametrizable serializer that improves the        
+--                readability of the test vectors in simulation and
+-- Dependencies:  verification.
+--
+-- Revision: 0.1
+--   0.01          + File Created
+--                 
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+library work;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.serializer_pkg_constraints.ALL
+
+package serializer_sim_pkg is
+
+   --! For the SPI translation there are only three different fields
+   constant c_SERIAL_BLOCKS : NATURAL := 3; 
+   
+   --! An array of naturals for storing the byte length of every field
+   type size_blocks is array (0 to c_SERIAL_BLOCKS - 1) of NATURAL;
+   
+   constant c_SIZE_BLOCKS   : size_blocks :=(0                   => 1,
+                                             1                   => 3,
+   --                                                            => ,
+                                             c_SERIAL_BLOCKS - 1 => 256);
+   
+   --! Here the parallel lenght to be sent out of the component                                          
+   function f_get_PARALLEL_LENGTH (constant serial_blocks : in NATURAL;
+                                   constant size_blocks   : in size_blocks)
+                                                                   return NATURAL;
+   
+   attribute  a_length : NATURAL;
+   
+   --! Record type for the parallelized instruction field                                                              
+   type inst_parallel is
+      record
+         inst: STD_LOGIC_VECTOR(8*(c_SIZE_BLOCKS(0) - 1)downto 0);
+      end record;
+   
+   attribute a_length of inst_parallel : type is (8*(c_SIZE_BLOCKS(0));
+   
+   
+   --! Record type for the parallelized address field                                                               
+   type addr_parallel is
+      record
+         addr: STD_LOGIC_VECTOR(8*(c_SIZE_BLOCKS(1) - 1)downto 0);
+      end record;
+   
+   attribute a_length of inst_parallel : type is (8*(c_SIZE_BLOCKS(1));
+   
+   --! Record type for the parallelized data field                                                          
+   type data_parallel is
+      record
+         data: STD_LOGIC_VECTOR(8*(c_SIZE_BLOCKS(2) - 1)downto 0);
+      end record;
+   
+   attribute a_length of inst_parallel : type is (8*(c_SIZE_BLOCKS(2));
+ 
+   --! Declaration of the default values
+   constant c_inst_paralell_default : inst_parallel := (inst => (others => '0'));
+   constant c_addr_paralell_default : addr_parallel := (addr => (others => '0'));
+   constant c_data_paralell_default : data_parallel := (data => (others => '0'));
+
+   function f_get_PARALLEL_LENGTH (constant individual_size   : in size_blocks)
+                                                             return NATURAL;
+   function f_INST_PARALLEL (STD_LOGIC_VECTOR(inst_parallel'a_length - 1
+                                              downto 0)) return inst_parallel;
+   function f_ADDR_PARALLEL (STD_LOGIC_VECTOR(addr_parallel'a_length - 1
+                                              downto 0)) return addr_parallel;
+   function f_DATA_PARALLEL (STD_LOGIC_VECTOR(data_parallel'a_length - 1
+                                              downto 0)) return data_parallel;
+   function f_SLV_TO_INST_PARALLEL (STD_LOGIC_VECTOR(8*c_PARALLEL_LENGTH - 1
+                                              downto 0)) return inst_parallel;
+   function f_SLV_TO_ADDR_PARALLEL (STD_LOGIC_VECTOR(8*c_PARALLEL_LENGTH - 1
+                                              downto 0)) return addr_parallel;
+   function f_SLV_TO_DATA_PARALLEL (STD_LOGIC_VECTOR(8*c_PARALLEL_LENGTH - 1
+                                              downto 0)) return data_parallel;
+
+package body serializer_sim_pkg is
+
+
+   function f_get_PARALLEL_LENGTH (constant individual_size   : in size_blocks)
+                                                             return NATURAL is
+      variable v_parallel_length  : NATURAL := 0;
+   begin
+      l_parallel_calc: for I in 0 to (c_SERIAL_BLOCKS - 1) loop
+         v_parallel_length := v_parallel_length + individual_size(I);
+      end loop;
+      return v_parallel_length;
+   end function;
+
+
+   function f_INST_PARALLEL (STD_LOGIC_VECTOR(8*c_PARALLEL_LENGTH - 1
+                                             downto 0))return inst_parallel is
+      variable v_inst_parallel : inst_parallel;
+   begin
+      v_inst_parallel.data <= inst_slv(8*c_PARALLEL_LENGTH - 1 
+                                             downto   8*c_PARALLEL_LENGTH
+                                                    - 8*c_SIZE_BLOCKS(0));
+   end f_INST_PARALLEL;
+
+
+   function f_ADDR_PARALLEL (addr_slv STD_LOGIC_VECTOR(8*c_PARALLEL_LENGTH - 1
+                                             downto 0)) return addr_parallel is
+      variable v_addr_parallel : addr_parallel;
+   begin
+      v_addr_parallel.data <= addr_slv(  8*c_PARALLEL_LENGTH
+                                       - 8*c_SIZE_BLOCKS(0) - 1 
+                                             downto   8*c_PARALLEL_LENGTH
+                                                    - 8*c_SIZE_BLOCKS(0)
+                                                    - 8*c_SIZE_BLOCKS(1));
+   end f_ADDR_PARALLEL;
+
+
+   function f_DATA_PARALLEL (STD_LOGIC_VECTOR(8*c_PARALLEL_LENGTH - 1
+                                             downto 0))return data_parallel is
+      variable v_data_parallel : data_parallel;
+   begin
+      v_data_parallel.data <= data_slv(8*c_SIZE_BLOCKS(2) - 1 downto 0);
+   end f_DATA_PARALLEL;
+
+
+   function f_STD_LOGIC_VECTOR (inst_part : inst_parallel)
+                                                     return STD_LOGIC_VECTOR is
+   begin
+   end f_STD_LOGIC_VECTOR;
+
+   function f_STD_LOGIC_VECTOR (addr_part : addr_parallel)
+                                                     return STD_LOGIC_VECTOR is
+   begin
+   end f_STD_LOGIC_VECTOR;
+
+   function f_STD_LOGIC_VECTOR (data_part : data_parallel)
+                                                     return STD_LOGIC_VECTOR is
+   begin
+   end f_STD_LOGIC_VECTOR;
+
+end serializer_sim_pkg;