Simulation. Test completion:

1.- Write into m25p32 SR works: we are able to protect SPI memory space. 2.- Starting to work in the Write Page test. Good synchronization between m25p32 controller, double buffer and SPI. Needs to load some data and check agains the serializer RX. 3.- Extra test: when an access over the SPI interface in being performed, the core doesn't allow to reconfigure the FMOH register, responsible of changing the fsm of the m25p32 controller. General: big cleanup of the code. Everything is commented. Code size smaller.

Simulation. Test completion:
1.- Write into m25p32 SR works: we are able to protect SPI memory space. 2.- Starting to work in the Write Page test. Good synchronization between m25p32 controller, double buffer and SPI. Needs to load some data and check agains the serializer RX. 3.- Extra test: when an access over the SPI interface in being performed, the core doesn't allow to reconfigure the FMOH register, responsible of changing the fsm of the m25p32 controller. General: big cleanup of the code. Everything is commented. Code size smaller.
44734571 · gilsoriano · 6c8c04da · 44734571 · 44734571 · 44734571
Commit 44734571 authored Aug 08, 2012 by gilsoriano
Showing with 214 additions and 146 deletions

m25p32_core.vhd hdl/m25p32/rtl/m25p32_core.vhd +176 -49

m25p32_core_pkg.vhd hdl/m25p32/rtl/m25p32_core_pkg.vhd +0 -81

m25p32_top_tb.vhd hdl/m25p32/test/m25p32_top_tb.vhd +38 -16

No files found.
--- a/hdl/m25p32/rtl/m25p32_core.vhd
+++ b/hdl/m25p32/rtl/m25p32_core.vhd
--- a/hdl/m25p32/rtl/m25p32_core_pkg.vhd
+++ b/hdl/m25p32/rtl/m25p32_core_pkg.vhd
@@ -210,88 +210,7 @@ package m25p32_core_pkg is
        spi_cs_n_o   : out STD_LOGIC);
   end component;

-   procedure proc_WRSR_fsm (signal s_CTR0     : inout r_CTR0;
-                            signal s_CTR1     : inout r_CTR1;
-                            signal s_SPI0     : inout r_SPI0;
-                            signal s_SPI1     : inout r_SPI1;
-                            signal s_SPI2     : in    r_SPI2;
-                            signal MEM_fsm    : inout t_m25p32_fsm; 
-                            signal MEM_fsm_d0 : inout t_m25p32_fsm);
-
 end m25p32_core_pkg;

-
 package body m25p32_core_pkg is
-
-
-   procedure proc_WRSR_fsm (signal s_CTR0     : inout r_CTR0;
-                            signal s_CTR1     : inout r_CTR1;
-                            signal s_SPI0     : inout r_SPI0;
-                            signal s_SPI1     : inout r_SPI1;
-                            signal s_SPI2     : in    r_SPI2;
-                            signal MEM_fsm    : inout t_m25p32_fsm; 
-                            signal MEM_fsm_d0 : inout t_m25p32_fsm)        is
-   begin
-      --! Creating one clock signal for r_FMOH.BOV bit
-      s_CTR1.BOV        <= '0';
-      --! Creating one clock signal for CTR1 push bits
-      s_CTR1.PUSH_I     <= '0';
-      s_CTR1.PUSH_A     <= '0';
-      s_CTR1.PUSH_D     <= '0';
-      --! Creating one clock signal for SPI1 push bits
-      s_SPI1.PUSH_INST  <= '0'; 
-      s_SPI1.PUSH_ADDR  <= '0'; 
-      s_SPI1.PUSH_DATA  <= '0'; 
-      case MEM_fsm is
-         when S0_IDLE              =>
-            if s_CTR0.OPF = '0' then
-               s_CTR0.OPA        <= '1';
-               MEM_fsm           <= S1_WREN;
-               s_SPI0            <= c_SPI0_WREN;
-               s_SPI1            <= c_SPI1_WREN;
-                --! We push directly the instruction from m25p32_core
-               s_CTR1.BOV        <= '1';
-           else
-               s_CTR0            <= c_CTR0_default;
-               s_SPI0            <= c_SPI0_default;
-               s_SPI1            <= c_SPI1_default;
-            end if;
-         when S1_WREN              =>
-            if s_SPI2.SENT_OP = '1' then
-               MEM_fsm           <= S2A_SPI_OP_LD_DBUF;
-               s_CTR1.PUSH_I     <= c_SPI1_WRSR.PUSH_INST; 
-               s_CTR1.PUSH_A     <= c_SPI1_WRSR.PUSH_ADDR; 
-               s_CTR1.PUSH_D     <= c_SPI1_WRSR.PUSH_DATA; 
-            end if;
-         when S2A_SPI_OP_LD_DBUF   =>
-               --! As it only takes only cycle to load the buffer, we just
-               --! pass to the next state
-               MEM_fsm           <= S2B_SPI_OP_LD_SPIBUF;
-               --! We push the contents into the double buffer by writing
-               --! into s_CTR1 register.
-               s_SPI0            <= c_SPI0_WRSR;
-               s_SPI1            <= c_SPI1_WRSR;
-         when S2B_SPI_OP_LD_SPIBUF =>
-            if s_SPI2.SENT_OP = '1' then
-               MEM_fsm           <= S4_WRDI;
-               s_SPI0            <= c_SPI0_WRDI;
-               s_SPI1            <= c_SPI1_WRDI;
-               --! We push directly the instruction from m25p32_core
-               s_CTR1.BOV        <= '1';
-            end if;
-         when S4_WRDI              =>
-            if s_SPI2.SENT_OP = '1' then
-               MEM_fsm           <= S0_IDLE;
-               s_SPI1            <= c_SPI1_IDLE;
-               s_CTR0.OPF        <= '1';
-            end if;
-         when Q0_ERROR             =>
-            s_SPI1               <= c_SPI1_IDLE;
-            MEM_fsm              <= S4_WRDI;
-         when others               =>
-            s_SPI1               <= c_SPI1_IDLE;
-      end case;
-   end procedure;
-
-
 end m25p32_core_pkg;
--- a/hdl/m25p32/test/m25p32_top_tb.vhd
+++ b/hdl/m25p32/test/m25p32_top_tb.vhd
@@ -157,9 +157,8 @@ begin
            when WRP         =>
               s_FMOH.PG   <= v_page; 
               s_FMOH.SCT  <= v_sector;
--            when RDSR     =>
--            when WRSR     =>
-            when others   =>
+            when others      =>
+               null;
         end case;
      end procedure;

@@ -226,27 +225,50 @@ begin
      wb_rst_i  <= '0';
        wait for c_WISHBONE_PERIOD*10;

-      --! Test schema:
-      --! 1.- 
+      --! Test schema WRSR:
+      --!                                          [wishbone addr]
+      --! 1.- Write SR to be passed to m25p32        c_SR_m25p32_addr
+      --! 2.- Place a WRSR order through FMOH        c_FMOH_addr

-        s_SR_m25p32 <= (WIP  => '0', 
-                        WEL  => '0', 
-                        BP0  => '1', 
-                        BP1  => '1', 
-                        BP2  => '1', 
-                        x    => (others => '0'), 
-                        SRWD => '0');
+      s_SR_m25p32 <= (WIP  => '0', 
+                      WEL  => '0', 
+                      BP0  => '1', 
+                      BP1  => '1', 
+                      BP2  => '1', 
+                      x    => (others => '0'), 
+                      SRWD => '0');

-           wait until rising_edge(wb_clk);
-        wishbone_write_SR(s_SR_m25p32);
+         wait until rising_edge(wb_clk);
+      wishbone_write_SR(s_SR_m25p32);

      set_FMOH(WRSR,
               0,
               0);
-        send_instruction;
+      send_instruction;

-      wait;

+      --! Test schema WRSR:
+      --!                                          [wishbone addr]
+      --! 1.- 
+      --! 2.- Place a WRP order through FMOH         c_FMOH_addr
+
+      set_FMOH(WRP,
+               1,
+               1);
+
+      wait for 10*c_WISHBONE_PERIOD;
+
+         --! Overwrite test
+         --! Why try to perform a write into FMOH when a operation is being
+         --! performed.
+         --! It should not rewrite the FMOH value.
+         send_instruction;
+
+      --! Know it should accept the instruction
+      wait for 200*c_WISHBONE_PERIOD;
+      send_instruction;
+
+      wait;

   end process m25p32_access;