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Conv TTL Blocking
Commit 456634b1 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Updated documentation file, set pulse status LED lighting length to 125 ms.

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\bibstyle{unsrt}
\bibdata{userGuide}
\bibcite{StandardBlocking}{1}
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@misc{StandardBlocking,
author= "C. Gil Soriano",
title= {{Standard Blocking Output Signal Definition for CTDAH board}},
month= sep,
year= 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
@TECHREPORT{UG380,
institution= "Xilinx Inc.",
title= {{Spartan-6 FPGA Configuration User Guide}},
month= jul,
year= 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
\ No newline at end of file
doc/HDL/usersGuide/userGuide.tex deleted 100755 → 0
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%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{draftwatermark}
\SetWatermarkLightness{0.90}
\SetWatermarkScale{5}
\begin{document}
\title{\textbf{CONV-TTL-BLO \\ User Guide}}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{Figures/CERN-Logo.png}
\end{center}
\end{figure}
\begin{abstract}
This document describes the CONV-TTL-BLO board, a Blocking pulse repetitor
board in double height VME format. It replaces all the following boards:
\begin{itemize}
\item 8 channel repeater
\item 16 channel repeater
\item CTDAC
\item LA-BLO-TTL
\item LAF-BLO-TTL
\item LASB-TTL-BLO
\item LA-GATE
\item LA-TTL-BLO
\item LAPF-TTL-BLO\footnote{For replacing this board a pulse width of 4us
must be set.}
\end{itemize}
\end{abstract}
\maketitle{}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
\pagebreak
\listoffigures
\listoftables
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\pagebreak
\section{Introduction}
CONV-TTL-BLO is a board intended for replicating Blocking Pulses, offering six
totally independent replication channels. The shape of the pulses is defined in
\cite{StandardBlocking}. CONV-TTL-BLO works together with two more boards:
CONV-TTL-RTM and CONV-TTL-RTM-BLO.\\
CONV-TTL-BLO holds all the active circuitry
and it is connected as a Front Module to a VME64 backplane. The ports offered
in the Front Panel are explained in the next section.\\
\begin{figure}[!htdp]
\begin{center}
\includegraphics[scale=0.55, keepaspectratio]{Figures/BLOschema.png}
\caption{Pulse Repetition system}
\label{prs}
\end{center}
\end{figure}
CONV-TTL-RTM and CONV-TTL-RTM-BLO are both connected to the rear part of the
crate and provide, in the rear panel, the connectivity of the I/O Blocking
lines.
Every channel offers, in the Rear Panel, three Blocking Pulse outputs and one
Blocking Pulse input.\\
CONV-TTL-RTM is a motherboard attached to the Rear Transition Module of the P2
VME64 connector. It connects CONV-TTL-BLO to CONV-TTL-RTM-BLO and
provides overvoltage protection for all the I/Os of all the channels.\\
CONV-TTL-RTM-BLO is a piggyback board mounted on CONV-TTL-RTM. It holds all the
LEMO 00 connectors and channel LEDs that are offered in the Rear Panel.
\begin{table}[htdp]
\begin{center}
%\begin{turn}{90}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Board} & \textbf{Connection}& \textbf{Ports}\\
\hline
\hline
\textit{CONV-TTL-BLO} & Front & SFP\\
& & TTL Blocking triggers\\
& & TTL Blocking output replica\\
& & inverters \\
\hline
\textit{CONV-TTL-RTM} & Back & - \\
\hline
\textit{CONV-TTL-RTM-BLO} & Back & Blocking Pulse input\\
&& Blocking Pulse outputs\\
\hline
\end{tabular}
\caption{Boards for Blocking repetition}
\label{boards}
%\end{turn}
\end{center}
\end{table}
\pagebreak
\section{Board Ports}
CONV-TTL-BLO consist of several ports, divided in three sections (from top to
bottom as shown in Figure~\ref{fp}):
\begin{itemize}
\item SFP connector: \textbf{[A]}.
\item Blocking connectors: \textbf{[B]} and \textbf{[C]}.
\item General Purpose connectors: \textbf{[D]} and \textbf{[E]}.
\end{itemize}
\subsection{TTL-triggers}
They correspond to the block \textbf{[B]} in Figure~\ref{fp}. The connectors are
LEMO 00.
By connecting an external trigger source to one of the connectors a pulse can be
replicated, either in a Blocking Pulse level in the Rear Panel or in a TTL panel
in the Front Panel.
\begin{table}[htdp]
\begin{center}
\begin{tabular}{|l|l|l|c|c|}
\hline
\textbf{Name} & \textbf{Type} & \textbf{Level} & \textbf{Internal} &
\textbf{Location}\\
&&&\textbf{Termination} &\\
\hline
\hline
CH1 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B] \\
\hline
CH2 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
CH3 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
CH4 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
CH5 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
CH6 IN & Pulsed & TTL or $\overline{TTL}$ & 50$\Omega$ Parallel & [B]\\
\hline
\end{tabular}
\caption{TTL-triggers Front Panel inputs}
\label{trigFP}
\end{center}
\end{table}
\subsection{TTL-level Blocking pulses replica}
They correspond to the block \textbf{[C]} in Figure~\ref{fp}. The connectors are
LEMO 00.
From these connectors a TTL-level Blocking Pulse replica of the Rear Panel
outputs if offered to the Front Panel. The pulse width of this output is
similar to the pulse outputted in the Rear Panel; however, the rise time and top
pulse level are obviously different from the Blocking output.\\
Once pulse is outputted, the LED of the corresponding channel blinks for 500
ms.\\
A summary of all the connector of this kind is found in Figure~\ref{replicaFP}.
\begin{table}[htdp]
\begin{center}
\begin{tabular}{|l|l|l|c|c|}
\hline
\textbf{Name} & \textbf{Type} & \textbf{Level} & \textbf{Internal} &
\textbf{Location}\\
&&&\textbf{Termination} &\\
\hline
\hline
CH1 OUT & Pulsed & TTL & No & [C]\\
\hline
CH2 OUT & Pulsed & TTL & No & [C]\\
\hline
CH3 OUT & Pulsed & TTL & No & [C]\\
\hline
CH4 OUT & Pulsed & TTL & No & [C]\\
\hline
CH5 OUT & Pulsed & TTL & No & [C]\\
\hline
CH6 OUT & Pulsed & TTL & No & [C]\\
\hline
\end{tabular}
\caption{TTL-level Blocking pulses Front Panel output}
\label{replicaFP}
\end{center}
\end{table}
\subsection{SFP connector}
It is marked in Figure~\ref{fp} as \textbf{[A]}. If the cable is plugged-in the
socket, \textit{White Rabbit} precise time-stamping can be obtained in
CONV-TTL-BLO. Three LEDs above the connector show the status of the
\textit{White Rabbit} link.
\subsection{General pupose}
In the lower part of the Front Panel (\textbf{[D]} and \textbf{[E]} in
Figure~\ref{fp}) can be found four dedicated inverters. The output is a TTL inverted version of
the TTL input.
\begin{table}[htdp]
\begin{center}
\begin{tabular}{|l|l|l|c|c|}
\hline
\textbf{Name} & \textbf{Type} & \textbf{Level} & \textbf{Internal} &
\textbf{Location}\\
&&&\textbf{Termination} &\\
\hline
\hline
\multicolumn{5}{|c|}{\textbf{General Purpose Inputs}}\\
\hline
INV A IN & Pulsed & TTL or $\overline{TTL}$ & No & [D]\\
\hline
INV B IN & Pulsed & TTL or $\overline{TTL}$ & No & [D]\\
\hline
INV C IN & Pulsed & TTL or $\overline{TTL}$ & No & [D]\\
\hline
INV D IN & Pulsed & TTL or $\overline{TTL}$ & No & [D]\\
\hline
\hline
\multicolumn{5}{|c|}{\textbf{General Purpose Inverted Outputs}}\\
\hline
INV A OUT & Pulsed & $\overline{TTL}$ or TTL & No & [E]\\
\hline
INV B OUT & Pulsed & $\overline{TTL}$ or TTL & No & [E]\\
\hline
INV C OUT & Pulsed & $\overline{TTL}$ or TTL & No & [E]\\
\hline
INV D OUT & Pulsed & $\overline{TTL}$ or TTL & No & [E]\\
\hline
\end{tabular}
\caption{General pupose Front Panel IOs}
\label{gpFP}
\end{center}
\end{table}
\pagebreak
\subsection{Front Panel}
\begin{figure}[!htdp]
\begin{center}
\includegraphics[scale=0.75, keepaspectratio]{Figures/FrontPanel.png}
\caption{CONV-TTL-BLO Front Panel}
\label{fp}
\end{center}
\end{figure}
\pagebreak
\section{Board Addressing}
Communication with the FPGA is done via I2C interface through SERA and SERB pins
in P1 VME64x connectors. In order to access one card inside a certain crate, it
is necessary to set:
\begin{itemize}
\item An \textbf{I2C address}. Every CONV-TTL-BLO has an I2C address that
equals the Geographical Address of the slot according to VME64x specifications. It is
7 bits width.
\item An \textbf{internal CONV-TTL-BLO address}. It is a short integer (16
bits) in big endian format.
\end{itemize}
%\subsection{Write command}
%\begin{table}[htdp]
%\begin{tabular}{|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|}
%\hline
%7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
%\hline
%\multicolumn{7}{|c|}{I2C ADDRESS} & RD\textbackslash\\
%\multicolumn{7}{|c|}{} & WRN\\
%\hline
%\end{tabular}
%\vspace{12pt}
%\begin{tabular}{|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|}
%\hline
%7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
%\hline
%\multicolumn{7}{|c|}{I2C ADDRESS} & RD\textbackslash\\
%\multicolumn{7}{|c|}{} & WRN\\
%\hline
%\end{tabular}
%\vspace{12pt}
%\begin{tabular}{|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|p{1cm}|}
%\hline
%7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
%\hline
%\multicolumn{7}{|c|}{I2C ADDRESS} & RD\textbackslash\\
%\multicolumn{7}{|c|}{} & WRN\\
%\hline
%\end{tabular}
%\caption{General pupose Front Panel IOs}
%\label{gpFP}
%\end{table}
\pagebreak
\section{Functional Description}
The task of CONV-TTL-BLO is to output a Blocking Pulse upon a reception of a
trigger is received.
As stated before, CONV-TTL-BLO works together with
CONV-TTL-RTM and CONV-TTL-RTM-BLO which are both in the rear part of the crate.
The system formed by this three boards offers three independent channels for
outputting Blocking Pulses. Refer to Figure~\ref{prs} for a visual,
whole-system, description.
CONV-TTL-BLO allows the user to set propierties for the pulse replication
and receive information above the latest events logged in the board.
\subsection{Trigger sources}
There are two sources for triggering in every channel: one coming from the
Front Panel (CONV-TTL-BLO) and other coming from the Rear Panel
(CONV-TTL-RTM through CONV-TTL-RTM-BLO).
The trigger policy is that \emph{a Blocking pulse will be outputted whenever
either a trigger in the Front Panel or the Rear Panel is detected}:\\
\begin{table}[htdp]
\begin{center}
\begin{tabular}{|c|c|c|}
\hline
\textbf{Trigger} & \textbf{Board} & \textbf{Connection}\\
\hline
\hline
TTL & CONV-TTL-BLO & Front Panel\\
\hline
Blocking & CONV-TTL-RTM-BLO & Rear Panel\\
\hline
\end{tabular}
\vspace{0.5cm}
\begin{tabular}{|c|}
\hline
\textbf{Global trigger is OR function of the two sources above}\\
\hline
\end{tabular}
\caption{Trigger sources}
\label{ts}
\end{center}
\end{table}
\pagebreak
\section{Memory Map}
\begin{table}[!htpd]
\begin{center}
\begin{turn}{90}
\begin{tabular}{|p{2cm}|p{2cm}|p{2cm}|p{3cm}|p{6cm}|}
\hline
\textbf{Channel} & \textbf{Address} & \textbf{Data type} & \textbf{Name} &
\textbf{Comment}\\
\hline
\hline
\multirow{2}{*}{Access} & 0x0101 & Bit pattern & CTR0\_ACCESS & Control device
access 0\\\cline{2-5}
&0x0102 & Bit pattern & ACTR1 & Control device access 1 \\
\hline
\hline
\multirow{2}{*}{I2C} & 0x0202 & Bit pattern & CTR0\_I2C & I2C control
0\\\cline{2-5} & 0x0203 & Bit pattern & I2C\_CTR1 & I2C control 1\\
\hline
\hline
\multirow{5}{*}{Ch 1} & 0x0301 & Bit pattern & CTR0\_CH1 & Channel 1
control\\\cline{2-5}
& 0x0302 & Integers & CTR1\_CH1 & Channel 1 min/max Pulse
length\\\cline{2-5}
& 0x0305 & Bit pattern & RAM0\_CH1 & RAM control Channel 1\\\cline{2-5}
& 0x0306 & Bit pattern & RAM1\_CH1 & Current read/write Address
pointers\\\cline{2-5}
& 0x0307 & Bit pattern & RAM2\_CH1 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Ch 2} & 0x0401 & Bit pattern & CTR0\_CH2 & Channel
control\\\cline{2-5}
& 0x0402 & Integers & CTR1\_CH2 & Channel 2 min/max Pulse
length\\\cline{2-5}
& 0x0405 & Bit pattern & RAM0\_CH2 & RAM control Channel 2\\\cline{2-5}
& 0x0406 & Bit pattern & RAM1\_CH2 & Current read/write Address
pointers\\\cline{2-5}
& 0x0407 & Bit pattern & RAM2\_CH2 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Ch 3} & 0x0501 & Bit pattern & CTR0\_CH3 & Channel 3
control\\\cline{2-5}
& 0x0502 & Integers & CTR1\_CH3 & Channel 3 min/max Pulse
length\\\cline{2-5}
& 0x0505 & Bit pattern & RAM0\_CH3 & RAM control Channel 3\\\cline{2-5}
& 0x0506 & Bit pattern & RAM1\_CH3 & Current read/write Address
pointers\\\cline{2-5}
& 0x0507 & Bit pattern & RAM2\_CH3 & Start/end read address\\
\hline
\end{tabular}
\end{turn}
\end{center}
\caption{CONV-TTL-BLO Memory map I/II}
\label{mmap1}
\end{table}
\begin{table}[!htpd]
\begin{center}
\begin{turn}{-90}
\begin{tabular}{|p{2.25cm}|p{2cm}|p{2cm}|p{3cm}|p{6cm}|}
\hline
\textbf{Channel} & \textbf{Address} & \textbf{Data type} & \textbf{Name} &
\textbf{Comment}\\
\hline
\hline
\multirow{5}{*}{Ch 4} & 0x0601 & Bit pattern & CTR0\_CH4 & Channel 4
control\\\cline{2-5}
& 0x0602 & Integers & CTR1\_CH4 & Channel 4 min/max Pulse
length\\\cline{2-5}
& 0x0605 & Bit pattern & RAM0\_CH4 & RAM control Channel 4\\\cline{2-5}
& 0x0606 & Bit pattern & RAM1\_CH4 & Current read/write Address
pointers\\\cline{2-5}
& 0x0607 & Bit pattern & RAM2\_CH4 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Ch 5} & 0x0701 & Bit pattern & CTR0\_CH5 & Channel 5
control\\\cline{2-5}
& 0x0702 & Integers & CTR1\_CH5 & Channel 5 min/max Pulse
length\\\cline{2-5}
& 0x0705 & Bit pattern & RAM0\_CH5 & RAM control Channel 5\\\cline{2-5}
& 0x0706 & Bit pattern & RAM1\_CH5 & Current read/write Address
pointers\\\cline{2-5}
& 0x0707 & Bit pattern & RAM2\_CH5 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Ch 6} & 0x0801 & Bit pattern & CTR0\_CH6 & Channel 6
control\\\cline{2-5}
& 0x0802 & Integers & CTR1\_CH6 & Channel 6 min/max Pulse
length\\\cline{2-5}
& 0x0805 & Bit pattern & RAM0\_CH6 & RAM control Channel 6\\\cline{2-5}
& 0x0806 & Bit pattern & RAM1\_CH6 & Current read/write Address
pointers\\\cline{2-5}
& 0x0807 & Bit pattern & RAM2\_CH6 & Start/end read address\\
\hline
\hline
\multirow{5}{*}{Multiboot} & 0x0901 & Bit pattern & CTRL0 & Multiboot operation
control\\\cline{2-5}
& 0x0904 & Integer & GENERAL1 & Lower bits 1$^{st}$ bitstream
address\\\cline{2-5} & 0x0905 & Bit pattern & GENERAL2 & Lower bits 1$^{st}$
bitstream address\\\cline{2-5}
& 0x0906 & Integer & GENERAL3 & Higher bits 2$^{nd}$ bitstream
address\\\cline{2-5}
& 0x0907 & Bit pattern & GENERAL4 & Higher bits 2$^{nd}$ bitstream
address\\\cline{2-5}
\hline
\hline
\multirow{2}{*}{EEPROM} &&&&\\\cline{2-5}
&&&&\\
\hline
\multirow{2}{*}{White Rabbit} &&&&\\\cline{2-5}
&&&&\\
\hline
\end{tabular}
\end{turn}
\end{center}
\caption{CONV-TTL-BLO Memory map II/II}
\label{mmap2}
\end{table}
\pagebreak
\section{Register Description}
\subsection{Access Registers}
\subsubsection{CTR0\_ACCESS}
The \textit{CTR0} register is a read-write register that enable and disable
access to Wishbone devices in the memory map.\\
\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | l |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR0\_ACCESS}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN0 & ENable access to device 0 in memory map\\
\hline
1 & EN1 & ENable access to device 1 in memory map\\
\hline
2 & EN2 & ENable access to device 2 in memory map\\
\hline
3 & EN3 & ENable access to device 3 in memory map\\
\hline
4 & EN4 & ENable access to device 4 in memory map\\
\hline
5 & EN5 & ENable access to device 5 in memory map\\
\hline
6 & EN6 & ENable access to device 6 in memory map\\
\hline
7 & EN7 & ENable access to device 7 in memory map\\
\hline
8 & EN8 & ENable access to device 8 in memory map\\
\hline
9 & EN9 & ENable access to device 9 in memory map\\
\hline
10 & EN10 & ENable access to device 10 in memory map\\
\hline
11 & EN11 & ENable access to device 11 in memory map\\
\hline
31-13 & x & Reserved \\
\hline
\end{tabular}\\
\caption{CTR0\_ACCESS Register}
\label{ctr0access}
\end{center}
\end{table}
\subsubsection{CTR1\_ACCESS}
The \textit{CTR1} register is a read-write register that enable and disable
read and write permissions to Wishbone devices in the memory map.\\
\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | l |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR1\_ACCESS}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & GWR & General write permissions\\
\hline
1 & GRD & General read permissions\\
\hline
2 & WR0 & WRite permissions in memory map 0\\
\hline
3 & RD0 & ReaD permissions in memory map 0\\
\hline
4 & WR1 & WRite permissions in memory map 1\\
\hline
5 & RD1 & ReaD permissions in memory map 1\\
\hline
6 & WR2 & WRite permissions in memory map 2\\
\hline
7 & RD2 & ReaD permissions in memory map 2\\
\hline
8 & WR3 & WRite permissions in memory map 3\\
\hline
9 & RD3 & ReaD permissions in memory map 3\\
\hline
10 & WR4 & WRite permissions in memory map 4\\
\hline
11 & RD4 & ReaD permissions in memory map 4\\
\hline
12 & WR5 & WRite permissions in memory map 5\\
\hline
13 & RD5 & ReaD permissions in memory map 5\\
\hline
14 & WR6 & WRite permissions in memory map 6\\
\hline
15 & RD6 & ReaD permissions in memory map 6\\
\hline
16 & WR7 & WRite permissions in memory map 7\\
\hline
17 & RD7 & ReaD permissions in memory map 7\\
\hline
18 & WR8 & WRite permissions in memory map 8\\
\hline
19 & RD8 & ReaD permissions in memory map 8\\
\hline
20 & WR9 & WRite permissions in memory map 9\\
\hline
21 & RD9 & ReaD permissions in memory map 9\\
\hline
22 & WR10 & WRite permissions in memory map 10\\
\hline
23 & RD10 & ReaD permissions in memory map 10\\
\hline
24 & WR11 & WRite permissions in memory map 11\\
\hline
25 & RD11 & ReaD permissions in memory map 11\\
\hline
31-26 & x & Reserved\\
\hline
\end{tabular}
\caption{CTR1\_ACCESS Register}
\label{ctr1access}
\end{center}
\end{table}
\pagebreak
\subsection{I2C Registers}
\subsubsection{CTR0\_I2C}
The CTR0 register is a write-read register. It controls the indirect addres
and holds the I2C address (which in the case of \textit{CONV-TTL-BLO} will be
connected to VME64x geographical address pins).\\
\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR0\_I2C}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & general ENable\\
\hline
1 & RST & general ReSeT\\
\hline
2 & PEN & Prescaler ENable\\
\hline
5-3 & x & Reserved\\
\hline
7-6 & BIA & Bytes Indirect Addressing\\
\hline
14-8 & A[6:0] & I2C address\\
\hline
15 & x & Reserved\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}
\caption{CTR0\_I2C Register}
\label{ctr0I2C}
\end{center}
\end{table}
\subsubsection{CTR1\_I2C}
The CTR1 register is a write-read register. It shows the fsm of the separate
\textit{read} and \textit{write} fsms.\\
\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR1\_I2C}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
7-0 & RDS & fsm status: ReaD Status\\
\hline
15-8 & WDS & fsm status: WRite Status\\
\hline
31-16 & - & Not used\\
\hline
\end{tabular}
\caption{CTR1\_I2C Register}
\label{ctr1I2C}
\end{center}
\end{table}
\pagebreak
\subsection{Channel Registers}
\subsubsection{CTR0\_CH[x]}
The CTR0\_CH[x] register is a read-write register. It allows setting up the
basic configuration of the trigger HDL core, its RAM blocks and both the deglitching
mask and output pulse length to be used.\\
\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR0\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN & General ENable\\
\hline
1 & CLR & General CLeaR\\
\hline
3-2 & x & Reserved\\
\hline
4 & EN\_TT & Enable Time-Tagging\\
\hline
5 & CLR\_TT & Clear Time-Tagging\\
\hline
7-6 & RDM & time-tagging ReaD Mode\\
\hline
15-8 & CGM & Current Glitch Mask\\
\hline
31-16 & CPL & Current Pulse Length\\
\hline
\end{tabular}
\caption{CTR0\_CH[x] Register}
\label{ctr0ch}
\end{center}
\end{table}
\subsubsection{CTR1\_CH[x]}
The CTR1\_CH[x] register is a read-write register. It allows setting up the
boundaries that override invalid values of CPL field in CTR0.\\
\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{CTR1\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & MinPL & Minimum Pulse Length\\
\hline
31-16 & MaxPL & Maximum Pulse Length\\
\hline
\end{tabular}
\caption{CTR1\_CH[x] Register}
\label{ctr1ch}
\end{center}
\end{table}
\subsubsection{RAM0\_CH[x]}
The RAM0 register is a read-write register. It allows setting up the RAM
and the read request to it.\\
\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{RAM0\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
0 & EN\_TT & Enable Time-Tagging \\
\hline
1 & CLR\_TT & Clear Time-Tagging \\
\hline
3-2 & RDM & time-tagging ReaD mode\\
\hline
4 & EMPTY & RAM empty\\
\hline
5 & FULL & RAM full\\
\hline
6 & WA & RAM Wrapped Around\\
\hline
7 & RQT & ReQuesT read\\
\hline
31-8 & x & Reserved\\
\hline
\end{tabular}
\caption{RAM0\_CH[x] Register}
\label{ram0ch}
\end{center}
\end{table}
\subsubsection{RAM1\_CH[x]}
The RAM1 register is a read-only register. It shows the current read and write
address configured to be accessed.\\
\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{RAM1\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & CRA & Current Read Address\\
\hline
31-16& CWA & Current Write Address\\
\hline
\end{tabular}
\caption{RAM1\_CH[x] Register}
\label{ram1ch}
\end{center}
\end{table}
\subsubsection{RAM2\_CH[x]}
The RAM2 register is a read-write register. It allows setting up the RAM adress
range to be read.\\
\begin{table}[!htpd]
\begin{center}
\begin{tabular}{| l | c | c |}
\hline
\multicolumn{3}{|c|}{\textbf{RAM2\_CH[x]}}\\
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning}\\
\hline
\hline
15-0 & SA & Starting read Address\\
\hline
31-16 & EA & Ending read Address\\
\hline
\end{tabular}
\caption{RAM2\_CH[x] Register}
\label{ram2ch}
\end{center}
\end{table}
\subsection{Multiboot Registers}
\subsection{White Rabbit Registers}
\pagebreak
\section{Installation}
\bibliographystyle{unsrt}
\bibliography{userGuide}
\end{document}
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id="image8503"
x="310.48663"
y="31.21929" />
</g>
</svg>
doc/ug/Makefile 0 → 100644
View file @ 456634b1
FILE=ug-conv-ttl-blo
all:
pdflatex -synctex=1 -interaction=nonstopmode *.tex
bibtex *.aux
pdflatex -synctex=1 -interaction=nonstopmode *.tex
pdflatex -synctex=1 -interaction=nonstopmode *.tex
evince $(FILE).pdf &
clean:
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
doc/ug/ug-conv-ttl-blo.bib 0 → 100755
View file @ 456634b1
@misc{StandardBlocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = "{\url{http://www.ohwr.org/documents/109}}"
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
@TECHREPORT{UG380,
institution = "Xilinx Inc.",
title = {{Spartan-6 FPGA Configuration User Guide}},
month = jul,
year = 2011,
number = "UG380 v2.3",
note = "{\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}"
}
@misc{rtm-ident,
title = {{RTM detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
doc/ug/ug-conv-ttl-blo.tex 0 → 100755
View file @ 456634b1
%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{hyperref}
\usepackage{rotating}
\usepackage{multirow}
% \usepackage{draftwatermark}
% \SetWatermarkLightness{0.90}
% \SetWatermarkScale{5}
\usepackage{float}
\restylefloat{table}
\begin{document}
\title{\textbf{CONV-TTL-BLO \\ User Guide}}
\author{Theodor-Adrian Stana\\
% \href{mailto:t.stana@cern.ch}{\textbf{\textit{t.stana@cern.ch}}}\\
Carlos Gil Soriano\\
% \href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}
BE-CO-HT\\
}
\date{\today}
\maketitle
\thispagestyle{empty}
\begin{figure}[htb]
\begin{center}
\includegraphics[scale=0.25, keepaspectratio]{Figures/CERN-Logo.png}
\end{center}
\end{figure}
\begin{abstract}
This document describes the CONV-TTL-BLO board, a Blocking pulse repeater
board in double height VME format. It replaces all the following boards:
\begin{itemize}
\item 8 channel repeater
\item 16 channel repeater
\item CTDAC
\item LA-BLO-TTL
\item LAF-BLO-TTL
\item LASB-TTL-BLO
\item LA-GATE
\item LA-TTL-BLO
\item LAPF-TTL-BLO\footnote{For replacing this board a pulse width of 4us
must be set.}
\end{itemize}
\end{abstract}
\maketitle{}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
\pagebreak
\listoffigures
\listoftables
\pagebreak
\section*{List of abbreviations}
\begin{itemize}
\item RTM -- Rear Transition Module
\item RTMM -- RTM Motherboard
\item RTMP -- RTM Piggiback
\end{itemize}
\pagenumbering{arabic}
\setcounter{page}{1}
\pagebreak
\section{Introduction}
\label{sec:intro}
CONV-TTL-BLO is a board intended for replicating Blocking Pulses, offering six
totally independent replication channels. The shape of the pulses is defined in
\cite{StandardBlocking}. CONV-TTL-BLO works together with two more boards:
CONV-TTL-RTM and CONV-TTL-RTM-BLO.\\
\begin{figure}[!htdp]
\begin{center}
\includegraphics[scale=0.55, keepaspectratio]{Figures/BLOschema.png}
\caption{Pulse Repetition system}
\label{prs}
\end{center}
\end{figure}
CONV-TTL-BLO contains all the active circuitry and it is connected as a Front Module
to a VME64 backplane. CONV-TTL-RTM and CONV-TTL-RTM-BLO are both connected to the rear
part of the crate and provide, in the rear panel, the connectivity of the I/O Blocking
lines. Every channel offers, in the rear panel, three Blocking Pulse outputs and one
Blocking Pulse input.
CONV-TTL-RTM is a motherboard attached to the Rear Transition Module (RTM) of the P2
VME64 connector. It connects CONV-TTL-BLO to CONV-TTL-RTM-BLO and
provides overvoltage protection for all the I/Os of all the channels.\\
CONV-TTL-RTM-BLO is a piggyback board mounted on CONV-TTL-RTM. It contains all the
LEMO 00 connectors and channel LEDs that are offered in the rear panel.
\begin{table}[htdp]
\caption{Boards for Blocking repetition}
\label{boards}
\centerline
{
%\begin{turn}{90}
\begin{tabular}{l l l}
\hline
\multicolumn{1}{c}{\textbf{Board}} & \multicolumn{1}{c}{\textbf{Connection}} & \multicolumn{1}{c}{\textbf{Ports}} \\
\hline
\textit{CONV-TTL-BLO} & Front & SFP \\
& & TTL Blocking triggers \\
& & TTL Blocking output replica \\
& & inverters \\
\textit{CONV-TTL-RTM} & Back & - \\
\textit{CONV-TTL-RTM-BLO} & Back & Blocking Pulse input \\
&& Blocking Pulse outputs\\
\hline
\end{tabular}
}
%\end{turn}
\end{table}
\pagebreak
\section{Main Board Front Panel}
\label{sec:mainboard-front-panel}
The front panel of CONV-TTL-BLO boards is shown in Figure~\ref{fp}. It consists
of status LEDs and several ports, divided in three sections from top to bottom:
\begin{itemize}
\item SFP connector: \textbf{[A]}.
\item Blocking connectors: \textbf{[B]} and \textbf{[C]}.
\item General Purpose connectors: \textbf{[D]} and \textbf{[E]}.
\end{itemize}
\begin{figure}[!htdp]
\begin{center}
\includegraphics[scale=.5, keepaspectratio]{Figures/FrontPanel.png}
\caption{CONV-TTL-BLO Front Panel}
\label{fp}
\end{center}
\end{figure}
\subsection{Status LEDs}
In the current version of the CONV-TTL-BLO boards, only several of the status LEDs
present on the board are used, due to limited firmware support in the FPGA.
The implemented status LEDs are presented in Table \ref{tbl:status-leds}. Unimplemented
status LEDs are off by default.
\begin{table}
\caption{Status LEDs on CONV-TTL-BLO front panels}
\label{tbl:status-leds}
\centerline
{
\begin{tabular}{l p{.75\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{LED}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{PW} & Power LED. Lights \textit{green} when a valid CONV-TTL-BLO firmware is loaded
to the FPGA. \\
\textit{ERR} & Error LED. Lights \textit{red} when no rear transition module board is present. \\
\textit{TTL\_N} & Negated-TTL status LED. Lights \textit{green} when negated TTL logic is selected
via the 8$^{th}$ position of the on-board selection switch. \\
\textit{I2C} & I$^2$C status LED. Lights \textit{red} until an I$^2$C transfer has taken place. Once
either a read or a write is successfully completed, the I$^2$C status LED lights \textit{green}
to signal the communication is up. \\
\hline
\end{tabular}
}
\end{table}
\subsection{SFP connector}
This connector is used to add White Rabbit support to the CONV-TTL-BLO boards.
If an optic fibre cable is connected to this socket, White Rabbit precise
time-stamping can be added to CONV-TTL-BLO. Three LEDs above the connector are provisioned to
show the status of the White Rabbit link.
White Rabbit is currently not supported in the CONV-TTL-BLO firmware.
\subsection{TTL triggers}
The TTL triggers correspond to block \textbf{[B]} in Figure~\ref{fp}. The connectors are
LEMO 00 (type EPY). By connecting an external trigger source to one of the connectors a pulse
is replicated in a Blocking Pulse level in the Rear Panel and in a TTL panel
in the Front Panel. All input channels are 50$\Omega$-terminated.
\subsection{Repeated TTL pulses}
These correspond to block \textbf{[C]} in Figure~\ref{fp}. The connectors are
LEMO 00 (type EPA). From these connectors a TTL level Blocking Pulse replica of the Rear Panel
outputs if offered to the Front Panel. The pulse width of this output is
similar to the pulse outputted in the Rear Panel; the rise time and top
pulse level are however different from the Blocking output.
When the pulse is output, the LED of the corresponding channel blinks for 125 ms.
The TTL output lines are not internally terminated.
\subsection{General pupose}
Four dedicated inverters can be found in the lower part of the Front Panel (\textbf{[D]} and \textbf{[E]} in
Figure~\ref{fp}). The output is a TTL inverted version of the TTL input. The inverted-TTL outputs are not internally
terminated.
\pagebreak
\section{Getting Started}
\label{sec:getting-started}
This section provides a reference to testing the CONV-TTL-BLO boards for basic functionality. The steps
listed below were run on a Linux Ubuntu 12.04 unit connected to the wired Ethernet interface on the
CERN network. The steps to follow should be similar on any Linux or Windows machine; some details
such as ELMA crate IP or TELNET client escape characters may differ in the reader's case.
The following steps should be performed for testing board functionality:
\begin{enumerate}
\item Plug in a front module card to the ELMA crate. Turn on power to the crate and program
the Spartan-6 FPGA.
\item Check that the \textit{PW} LED lights \textit{green} and the \textit{ERR} and \textit{I2C} LEDs light \textit{red}.
The \textit{TTL\_N} LED may also be lit. If it is and the LED is \textit{green}, this is not an issue.
\item Connect to an ELMA crate via TELNET, using the following command on the command line:
\begin{verbatim}
$ telnet 137.138.192.90
Trying 137.138.192.90...
Connected to 137.138.192.90.
Escape character is '^]'.
login:user
password USER
%>
\end{verbatim}
\item If the TELNET access is successful, the user should now be presented with a command line
to the SysMon board. To test basic SysMon functionality, run a \verb=voltage= command on the
SysMon, which should output the following:
\begin{verbatim}
%>voltage
----------------------------Sensor List---------------------------
--no--Name-------------Type----Value--Unit---State------------------
* 2 +3.3V Thr 3.31 V Ok
* 3 +5V Thr 5.01 V Ok
* 4 +12V Thr 12.09 V Ok
* 5 -12V Thr -12.38 V Ok
\end{verbatim}
\item It can now be proceeded to reading a register from the CONV-TTL-BLO boards. The \verb=readreg=
command can be used for this purpose. Assuming a CONV-TTL-BLO board in VME slot 1, reading register
I2C\_CTR0 at address 0x40 (see Sec. \ref{sec:internal-regs}) is done as follows:
\begin{verbatim}
%>readreg 1 17
Read Data: 004042BC
\end{verbatim}
\item The output of the command should be as above, yielding the default value of the I2C\_CTR0 register.
The \textit{I2C} LED on the front panel should also be lit \textit{green} now. It can now be proceeded to checking
the pulse repetition mechanisms.
\item First, connect one end of a cable with LEMO 00 connectors at both ends to the front module front panel
TTL input ports.
\item Configure a pulse generator to output TTL level pulses (\textit{max. 5V}) at a frequency of about 3~Hz
with a pulse length of $\geq$1~$\mu$s.
\item Connect the other end of the cable to the pulse generator. The LED of the corresponding channel should
light for 125~ms when a pulse arrives.
\item Connect the corresponding channel output port to an oscilloscope and measure the signal level of the pulse
and that the pulse width is 1~${\mu}$s long.
\item Repeat the operation with the other front channels.
\item Connect a rear transition module (RTM) board to the back-plane of the ELMA, on the same VME slot as the front module.
The \textit{ERR} LED should turn off.
\item Connect the LEMO cable to each channel on the front module front panel in turn to each of the channels.
As with the front module front panel, the LED corresponding to the connected channel on the rear transition module piggyback
(RTMP) front panel should be lit for about 125~ms when a pulse arrives. Measure that the output pulse on the blocking
channels is 1~${\mu}$s long and 24~V in amplitude.
\item Disconnect the LEMO cable from the front module front panel and configure the pulse generator for 15~V pulse amplitude.
\item Connect the LEMO cable to channel 1 the front panel of the RTMP board. Measure the output pulse on the corresponding channel of the
RTMP front panel; it should be 1~${\mu}$s long and 24~V in amplitude.
\item Finally, measure on the front panel of the front module that on channel 1 the output pulse is 1~${\mu}$s long and 3.3~V.
\item Repeat for all other channels.
\end{enumerate}
\pagebreak
\section{Functional Description}
The task of CONV-TTL-BLO is to output a Blocking Pulse upon a reception of a
trigger is received. As stated before, CONV-TTL-BLO works together with
CONV-TTL-RTM and CONV-TTL-RTM-BLO in the rear part of the crate.
The system formed by these three boards offers three independent channels for
outputting Blocking Pulses. Refer to Figure~\ref{prs} for a visual,
whole-system, description.
There are two sources for triggering in every channel: one coming from the
Front Panel (CONV-TTL-BLO) and other coming from the Rear Panel
(CONV-TTL-RTM through CONV-TTL-RTM-BLO).
The trigger policy is that a Blocking pulse will be outputted whenever
either a trigger in the Front Panel or the Rear Panel is detected.
\begin{table}[htdp]
\caption{Trigger sources}
\begin{center}
\begin{tabular}{c c c}
\hline
\textbf{Trigger} & \textbf{Board} & \textbf{Connection} \\
\hline
TTL & CONV-TTL-BLO & Front Panel\\
Blocking & CONV-TTL-RTM-BLO & Rear Panel\\
\hline
\end{tabular}
\vspace{0.5cm}
\begin{tabular}{|c|}
\hline
\textbf{Global trigger is OR function of the two sources above} \\
\hline
\end{tabular}
\end{center}
\end{table}
All the control logic of the system is implemented in a Xilinx Spartan-6 FPGA. Apart from
pulse repetition, an I$^2$C to Wishbone bridge is also implemented. This module translates I$^2$C
accesses as presented in accesses to internal memory-mapped registers. The status of the various
components in the system can in this way be checked and controlled.
%CONV-TTL-BLO allows the user to set properties for the pulse replication
%and receive information above the latest events logged in the board.
\pagebreak
\section{Accessing internal registers}
\label{sec:internal-regs}
\subsection{ELMA crates}
CONV-TTL-BLO boards have been designed to operate in ELMA crates. These crates provide a
back plane with VME64x connectors which boards can be plugged into. A dedicated board inside the
ELMA crates called the SysMon (System Monitor) monitors overall system status and provides access
to boards plugged into the VME back plane.
The user can connect to SysMon boards either through a simple RS-232 interface, or through Telnet.
In order to send commands to a board plugged into an ELMA crate, the user would connect to the SysMon
over one of these two interfaces and send \verb=readreg= and \verb=writereg= commands to
board-specific registers, as exemplified in Section \ref{sec:getting-started} to control their functioning.
%Since it is the interface most experimented with up to the point of writing of this document,
%only the Telnet interface is used throughout this document.
\subsection{Board Addressing}
\label{sec:brd-addressing}
Communication with the CONV-TTL-BLO FPGA is done via I$^2$C interface through the SERA and SERB pins
in P1 VME64x connectors. In order to access a CONV-TTL-BLO board, it is necessary to send:
\begin{itemize}
\item The board's 7-bit I$^2$C address. Every CONV-TTL-BLO has an address that prepends two bits
of value \textit{10} to the Geographical Address of the slot according to VME64x specifications.
\item An internal CONV-TTL-BLO register address. It is a 16-bit integer in \textit{little endian} format
(most significant byte is sent first).
\end{itemize}
After this, four bytes of data are read/written from/to the internal CONV-TTL-BLO register. These
four bytes of data are written in \textit{big endian} format (least significant byte is sent first).
The addressing protocol is thoroughly described in \cite{sysmon-i2c}. The SysMon acts as a master on the
I$^2$C interface and has the protocol implemented as software on the on-board processor. The FPGAs on
CONV-TTL-BLO boards implement an I$^2$C slave and decode the data streams sent by the SysMon.
\subsection{CONV-TTL-BLO memory map}
\label{sec:memmap}
Table \ref{tbl:memmap} summarizes the registers mapping in the current version of the CONV-TTL-BLO firmware.
The first column represents the Wishbone address internal to the FPGA firmware and the second column represents
the ELMA register address (in \verb=readreg= and \verb=writereg= commands).
\begin{table}[!hbtp]
\caption{Memory map of the CONV-TTL-BLO design}
\label{tbl:memmap}
\centerline
{
\begin{tabular}{ r r l c p{.5\textwidth} }
\hline
\multicolumn{1}{c}{Address} & \multicolumn{1}{c}{ELMA} & \multicolumn{1}{c}{Name} & \multicolumn{1}{c}{Access} & \multicolumn{1}{c}{Description} \\
\hline
0x00 & 1 & STAT\_L & R & Lower 32 bits of system status register \\
0x04 & 2 & STAT\_H & R & Upper 32 bits of system status register \\
0x40 & 17 & I2C\_CTR0 & R & I$^2$C control register \\
0x44 & 18 & I2C\_LT & R & I$^2$C line timing register, provides the current I$^2$C line speed \\
0x48 & 19 & I2C\_DTX & R/W & Data to transmit through the I$^2$C interface \\
0x4C & 20 & I2C\_DRXA & R & Lower 32 bits of data received through the I$^2$C interface \\
0x50 & 21 & I2C\_DRXB & R & Upper 32 bits of data received through the I$^2$C interface \\
\hline
\end{tabular}
}
\end{table}
\subsection{Register description}
\subsubsection{STAT\_L}
\begin{table}[H]
%\caption{STAT\_L register}
%\label{tbl:reg-statl}
\centerline
{
\begin{tabular}{r c c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Reset} & \multicolumn{1}{c}{Description} \\
\hline
31..0 & IDENT\_L & 0x00000000 & Lower 32 bits of board identity, as provided by Maxim DS18B20U+ thermometer \\
\hline
\end{tabular}
}
\end{table}
\subsubsection{STAT\_H}
\begin{table}[H]
%\caption{STAT\_H register}
%\label{tbl:reg-stath}
\centerline
{
\begin{tabular}{r c c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Reset} & \multicolumn{1}{c}{Description} \\
\hline
15..0 & IDENT\_H & 0x0000 & Upper 32 bits of board identity, as provided by Maxim DS18B20U+ thermometer \\
18..16 & RTMM & "000" & Rear transition module mainboard (RTMM) identification \cite{rtm-ident} \\
21..19 & RTMP & "000" & Rear transition module piggyback (RTMP) identification \cite{rtm-ident} \\
31..22 & \textit{unimplemented} & -- & Unimplemented bits, read undefined, write as '0' \\
\hline
\end{tabular}
}
\end{table}
\subsubsection{I2C\_CTR0}
\begin{table}[H]
%\caption{I2C\_CTR0 register}
%\label{tbl:reg-i2c-ctr0}
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
0 & I2C\_OP & '0' & I$^2$C operation, unused bit \\
7..1 & I2C\_ADDR & see Sec. \ref{sec:brd-addressing} & I$^2$C address of the CONV-TTL-BLO board \\
11..8 & BIA & 0x2 & Bytes of Indirect Addressing \\
19..12 & BRD & 0x4 & Bytes to be read from FPGA \\
27..20 & BWR & 0x4 & Bytes to be written to FPGA \\
31..28 & \textit{unimplemented} & -- & Unimplemented bits, read undefined, write as '0' \\
\hline
\end{tabular}
}
\end{table}
\subsubsection{I2C\_LT}
\begin{table}[H]
%\caption{I2C\_LT register}
%\label{tbl:reg-i2c-ctr0}
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
7..0 & WBCP & 20 & WishBone Clock Period, in ns \\
31..8 & SCLP & 0x000000 & SCL Period \\
\hline
\end{tabular}
}
\end{table}
\subsubsection{I2C\_DTX}
\begin{table}[H]
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
31..0 & DTX & 0x00000000 & DTX register bits \\
\hline
\end{tabular}
}
\end{table}
\subsubsection{I2C\_DRXA}
\begin{table}[H]
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
31..0 & DRXA & 0x00000000 & DRXA register bits \\
\hline
\end{tabular}
}
\end{table}
\subsubsection{I2C\_DRXB}
\begin{table}[H]
\centerline
{
\begin{tabular}{r c c p{.5\textwidth}}
\hline
\multicolumn{1}{c}{Bit} & \multicolumn{1}{c}{Field} & \multicolumn{1}{c}{Default} & \multicolumn{1}{c}{Description} \\
\hline
31..0 & DRXB & 0x00000000 & DRXB register bits \\
\hline
\end{tabular}
}
\end{table}
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{ug-conv-ttl-blo}
\end{document}
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 456634b1
......@@ -413,9 +413,9 @@ begin
generic map
(
g_number_of_channels => g_number_of_channels,
g_clk_period => c_CLKB_PERIOD,
g_pulse_length => c_OUTPUT_PULSE_LENGTH,
g_led_blinking_length => c_LED_BLINKING_LENGTH
g_clk_period => 5 ns,
g_pulse_length => 1000 ns,
g_led_blinking_length => (10**6)*125 ns
)
port map
(
......
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