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706c104c
Commit
706c104c
authored
May 16, 2013
by
Theodor-Adrian Stana
Browse files
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Add flash_load block
parent
cdc38585
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9 changed files
with
737 additions
and
0 deletions
+737
-0
Makefile
hdl/flash_load/syn/Makefile
+63
-0
Manifest.py
hdl/flash_load/syn/Manifest.py
+13
-0
flash_load.bit
hdl/flash_load/syn/flash_load.bit
+0
-0
flash_load.gise
hdl/flash_load/syn/flash_load.gise
+180
-0
flash_load.xise
hdl/flash_load/syn/flash_load.xise
+348
-0
run.tcl
hdl/flash_load/syn/run.tcl
+2
-0
Manifest.py
hdl/flash_load/top/Manifest.py
+4
-0
flash_load.ucf
hdl/flash_load/top/flash_load.ucf
+4
-0
flash_load.v
hdl/flash_load/top/flash_load.v
+123
-0
No files found.
hdl/flash_load/syn/Makefile
0 → 100644
View file @
706c104c
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT
:=
flash_load.xise
ISE_CRAP
:=
*
.b flash_load_summary.html
*
.tcl flash_load.bld flash_load.cmd_log
*
.drc flash_load.lso
*
.ncd flash_load.ngc flash_load.ngd flash_load.ngr flash_load.pad flash_load.par flash_load.pcf flash_load.prj flash_load.ptwx flash_load.stx flash_load.syr flash_load.twr flash_load.twx flash_load.gise flash_load.unroutes flash_load.ut flash_load.xpi flash_load.xst flash_load_bitgen.xwbt flash_load_envsettings.html flash_load_guide.ncd flash_load_map.map flash_load_map.mrp flash_load_map.ncd flash_load_map.ngm flash_load_map.xrpt flash_load_ngdbuild.xrpt flash_load_pad.csv flash_load_pad.txt flash_load_par.xrpt flash_load_summary.xml flash_load_usage.xml flash_load_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local
:
echo
"project open
$(PROJECT)
"
>
run.tcl
echo
"process run {Generate Programming File} -force rerun_all"
>>
run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean
:
rm
-f
$(ISE_CRAP)
rm
-rf
xst xlnx_auto_
*
_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper
:
rm
-f
*
.bit
*
.bin
*
.mcs
USER
:=
$(HDLMAKE_USER)
#take the value from the environment
SERVER
:=
$(HDLMAKE_SERVER)
#take the value from the environment
R_NAME
:=
flash_load
__test_for_remote_synthesis_variables
:
ifeq
(x$(USER),x)
@echo
"Remote synthesis user is not set. You can set it by editing variable USER in the makefile."
&&
false
endif
ifeq
(x$(SERVER),x)
@echo
"Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile."
&&
false
endif
CWD
:=
$(
shell
pwd
)
FILES
:=
../top/flash_load.v
\
../top/flash_load.ucf
\
run.tcl
\
flash_load.xise
#target for running simulation in the remote location
remote
:
__test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back
:
__do_synthesis
__do_synthesis
:
__send
__send
:
__test_for_remote_synthesis_variables
__send
:
ssh
$(USER)
@
$(SERVER)
'mkdir -p
$(R_NAME)
'
rsync
-Rav
$
(
foreach file,
$(FILES)
,
$(
shell
readlink
-f
$(file))
)
$(USER)
@
$(SERVER)
:
$(R_NAME)
__do_synthesis
:
ssh
$(USER)
@
$(SERVER)
'cd
$(R_NAME)$(CWD)
&& xtclsh run.tcl'
__send_back
:
cd
..
&&
rsync
-av
$(USER)
@
$(SERVER)
:
$(R_NAME)$(CWD)
.
&&
cd
$(CWD)
#target for removing stuff from the remote location
cleanremote
:
ssh
$(USER)
@
$(SERVER)
'rm -rf
$(R_NAME)
'
hdl/flash_load/syn/Manifest.py
0 → 100644
View file @
706c104c
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"flash_load"
syn_project
=
"flash_load.xise"
modules
=
{
"local"
:
[
"../top"
]
}
hdl/flash_load/syn/flash_load.bit
0 → 100644
View file @
706c104c
File added
hdl/flash_load/syn/flash_load.gise
0 → 100644
View file @
706c104c
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project
xmlns=
"http://www.xilinx.com/XMLSchema"
xmlns:xil_pn=
"http://www.xilinx.com/XMLSchema"
>
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version
xmlns=
"http://www.xilinx.com/XMLSchema"
>
11.1
</version>
<sourceproject
xmlns=
"http://www.xilinx.com/XMLSchema"
xil_pn:fileType=
"FILE_XISE"
xil_pn:name=
"flash_load.xise"
/>
<files
xmlns=
"http://www.xilinx.com/XMLSchema"
>
<file
xil_pn:fileType=
"FILE_DIRECTORY"
xil_pn:name=
"_ngo"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/bitgen.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/map.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/ngdbuild.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/par.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/trce.xmsgs"
/>
<file
xil_pn:fileType=
"FILE_XMSGS"
xil_pn:name=
"_xmsgs/xst.xmsgs"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_BITGEN_REPORT"
xil_pn:name=
"flash_load.bgn"
xil_pn:subbranch=
"FPGAConfiguration"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_BIT"
xil_pn:name=
"flash_load.bit"
xil_pn:subbranch=
"FPGAConfiguration"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGDBUILD_LOG"
xil_pn:name=
"flash_load.bld"
/>
<file
xil_pn:fileType=
"FILE_CMD_LOG"
xil_pn:name=
"flash_load.cmd_log"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_BITGEN_DRC"
xil_pn:name=
"flash_load.drc"
xil_pn:subbranch=
"FPGAConfiguration"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_LSO"
xil_pn:name=
"flash_load.lso"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NCD"
xil_pn:name=
"flash_load.ncd"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGC"
xil_pn:name=
"flash_load.ngc"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGD"
xil_pn:name=
"flash_load.ngd"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGR"
xil_pn:name=
"flash_load.ngr"
/>
<file
xil_pn:fileType=
"FILE_PAD_MISC"
xil_pn:name=
"flash_load.pad"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_PAR_REPORT"
xil_pn:name=
"flash_load.par"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_PCF"
xil_pn:name=
"flash_load.pcf"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_XST_PROJECT"
xil_pn:name=
"flash_load.prj"
/>
<file
xil_pn:fileType=
"FILE_TRCE_MISC"
xil_pn:name=
"flash_load.ptwx"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_XST_STX"
xil_pn:name=
"flash_load.stx"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_XST_REPORT"
xil_pn:name=
"flash_load.syr"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_TIMING_TXT_REPORT"
xil_pn:name=
"flash_load.twr"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_TIMING_XML_REPORT"
xil_pn:name=
"flash_load.twx"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_UNROUTES"
xil_pn:name=
"flash_load.unroutes"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_BITGEN_REPORT"
xil_pn:name=
"flash_load.ut"
xil_pn:subbranch=
"FPGAConfiguration"
/>
<file
xil_pn:fileType=
"FILE_XPI"
xil_pn:name=
"flash_load.xpi"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_XST"
xil_pn:name=
"flash_load.xst"
/>
<file
xil_pn:fileType=
"FILE_NCD"
xil_pn:name=
"flash_load_guide.ncd"
xil_pn:origination=
"imported"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_MAP_REPORT"
xil_pn:name=
"flash_load_map.map"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_MAP_REPORT"
xil_pn:name=
"flash_load_map.mrp"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NCD"
xil_pn:name=
"flash_load_map.ncd"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_NGM"
xil_pn:name=
"flash_load_map.ngm"
xil_pn:subbranch=
"Map"
/>
<file
xil_pn:fileType=
"FILE_XRPT"
xil_pn:name=
"flash_load_map.xrpt"
/>
<file
xil_pn:fileType=
"FILE_XRPT"
xil_pn:name=
"flash_load_ngdbuild.xrpt"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_PAD_EXCEL_REPORT"
xil_pn:name=
"flash_load_pad.csv"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:branch=
"Implementation"
xil_pn:fileType=
"FILE_PAD_TXT_REPORT"
xil_pn:name=
"flash_load_pad.txt"
xil_pn:subbranch=
"Par"
/>
<file
xil_pn:fileType=
"FILE_XRPT"
xil_pn:name=
"flash_load_par.xrpt"
/>
<file
xil_pn:fileType=
"FILE_FITTER_REPORT"
xil_pn:name=
"flash_load_summary.xml"
/>
<file
xil_pn:fileType=
"FILE_WEBTALK"
xil_pn:name=
"flash_load_usage.xml"
/>
<file
xil_pn:fileType=
"FILE_XRPT"
xil_pn:name=
"flash_load_xst.xrpt"
/>
<file
xil_pn:fileType=
"FILE_LOG"
xil_pn:name=
"webtalk.log"
/>
<file
xil_pn:fileType=
"FILE_FITTER_REPORT"
xil_pn:name=
"webtalk_pn.xml"
/>
<file
xil_pn:fileType=
"FILE_DIRECTORY"
xil_pn:name=
"xlnx_auto_0_xdb"
/>
<file
xil_pn:fileType=
"FILE_DIRECTORY"
xil_pn:name=
"xst"
/>
</files>
<transforms
xmlns=
"http://www.xilinx.com/XMLSchema"
>
<transform
xil_pn:end_ts=
"1368621130"
xil_pn:name=
"TRAN_copyInitialToXSTAbstractSynthesis"
xil_pn:start_ts=
"1368621130"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621130"
xil_pn:name=
"TRAN_schematicsToHdl"
xil_pn:prop_ck=
"6934415616083766239"
xil_pn:start_ts=
"1368621130"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621130"
xil_pn:name=
"TRAN_regenerateCores"
xil_pn:prop_ck=
"-1721405900475599742"
xil_pn:start_ts=
"1368621130"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621130"
xil_pn:name=
"TRAN_SubProjectAbstractToPreProxy"
xil_pn:start_ts=
"1368621130"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621130"
xil_pn:name=
"TRAN_xawsTohdl"
xil_pn:prop_ck=
"5900686104834338785"
xil_pn:start_ts=
"1368621130"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621130"
xil_pn:name=
"TRAN_SubProjectPreToStructuralProxy"
xil_pn:prop_ck=
"-3972139311098429560"
xil_pn:start_ts=
"1368621130"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621130"
xil_pn:name=
"TRAN_platgen"
xil_pn:prop_ck=
"8407149860075101388"
xil_pn:start_ts=
"1368621130"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621141"
xil_pn:in_ck=
"-217834592883323394"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"139858878510116945"
xil_pn:start_ts=
"1368621130"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"_xmsgs/xst.xmsgs"
/>
<outfile
xil_pn:name=
"flash_load.lso"
/>
<outfile
xil_pn:name=
"flash_load.ngc"
/>
<outfile
xil_pn:name=
"flash_load.ngr"
/>
<outfile
xil_pn:name=
"flash_load.prj"
/>
<outfile
xil_pn:name=
"flash_load.stx"
/>
<outfile
xil_pn:name=
"flash_load.syr"
/>
<outfile
xil_pn:name=
"flash_load.xst"
/>
<outfile
xil_pn:name=
"flash_load_xst.xrpt"
/>
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
<outfile
xil_pn:name=
"xst"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621141"
xil_pn:in_ck=
"2585801308284997222"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"-8134291796269689588"
xil_pn:start_ts=
"1368621141"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621149"
xil_pn:in_ck=
"-4949290262918435527"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"5928870684827519715"
xil_pn:start_ts=
"1368621141"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_ngo"
/>
<outfile
xil_pn:name=
"_xmsgs/ngdbuild.xmsgs"
/>
<outfile
xil_pn:name=
"flash_load.bld"
/>
<outfile
xil_pn:name=
"flash_load.ngd"
/>
<outfile
xil_pn:name=
"flash_load_ngdbuild.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621172"
xil_pn:in_ck=
"-4949290262918435526"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1368621149"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/map.xmsgs"
/>
<outfile
xil_pn:name=
"flash_load.pcf"
/>
<outfile
xil_pn:name=
"flash_load_map.map"
/>
<outfile
xil_pn:name=
"flash_load_map.mrp"
/>
<outfile
xil_pn:name=
"flash_load_map.ncd"
/>
<outfile
xil_pn:name=
"flash_load_map.ngm"
/>
<outfile
xil_pn:name=
"flash_load_map.xrpt"
/>
<outfile
xil_pn:name=
"flash_load_summary.xml"
/>
<outfile
xil_pn:name=
"flash_load_usage.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621205"
xil_pn:in_ck=
"-8441539207212611245"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1368621172"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/par.xmsgs"
/>
<outfile
xil_pn:name=
"flash_load.ncd"
/>
<outfile
xil_pn:name=
"flash_load.pad"
/>
<outfile
xil_pn:name=
"flash_load.par"
/>
<outfile
xil_pn:name=
"flash_load.ptwx"
/>
<outfile
xil_pn:name=
"flash_load.unroutes"
/>
<outfile
xil_pn:name=
"flash_load.xpi"
/>
<outfile
xil_pn:name=
"flash_load_pad.csv"
/>
<outfile
xil_pn:name=
"flash_load_pad.txt"
/>
<outfile
xil_pn:name=
"flash_load_par.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"1368621225"
xil_pn:in_ck=
"7054216870265283536"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"396117104113915555"
xil_pn:start_ts=
"1368621205"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
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<outfile
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<outfile
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<outfile
xil_pn:name=
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<outfile
xil_pn:name=
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</transform>
<transform
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xil_pn:in_ck=
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</transforms>
</generated_project>
hdl/flash_load/syn/flash_load.xise
0 → 100644
View file @
706c104c
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project
xmlns=
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xmlns:xil_pn=
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<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
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<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
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xil_pn:name=
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<property
xil_pn:name=
"Maximum Number of Lines in Report"
xil_pn:value=
"1000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Maximum Signal Name Length"
xil_pn:value=
"20"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Move First Flip-Flop Stage"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Move Last Flip-Flop Stage"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Insert IPROG CMD in the Bitfile spartan6"
xil_pn:value=
"Enable"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Next Configuration Mode spartan6"
xil_pn:value=
"001"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Starting Address for Golden Configuration spartan6"
xil_pn:value=
"0x00000000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Starting Address for Next Configuration spartan6"
xil_pn:value=
"0x00000000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Use New Mode for Next Configuration spartan6"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: User-Defined Register for Failsafe Scheme spartan6"
xil_pn:value=
"0x0000"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Netlist Hierarchy"
xil_pn:value=
"As Optimized"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Netlist Translation Type"
xil_pn:value=
"Timestamp"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Clock Buffers"
xil_pn:value=
"16"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report Post Trace"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimization Effort spartan6"
xil_pn:value=
"Normal"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimization Goal"
xil_pn:value=
"Speed"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimize Instantiated Primitives"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options spartan6"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Par"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compxlib Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Map Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other NETGEN Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Ngdbuild Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Place & Route Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Simulator Commands Behavioral"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Simulator Commands Post-Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Simulator Commands Post-Route"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Simulator Commands Post-Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other XPWR Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other XST Command Line Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Output Extended Identifiers"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Output File Name"
xil_pn:value=
"flash_load"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Overwrite Compiled Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers into IOBs"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Package"
xil_pn:value=
"fgg484"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Timing-Driven Packing and Placement"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place & Route Effort Level (Overall)"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place And Route Mode"
xil_pn:value=
"Normal Place and Route"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Place MultiBoot Settings into Bitstream spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Placer Effort Level Map"
xil_pn:value=
"High"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Placer Extra Effort Map"
xil_pn:value=
"None"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Port to be used"
xil_pn:value=
"Auto - default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Map Simulation Model Name"
xil_pn:value=
"flash_load_map.v"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Place & Route Simulation Model Name"
xil_pn:value=
"flash_load_timesim.v"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Synthesis Simulation Model Name"
xil_pn:value=
"flash_load_synthesis.v"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Post Translate Simulation Model Name"
xil_pn:value=
"flash_load_translate.v"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Map spartan6"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Xst"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Produce Verbose Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Property Specification in Project File"
xil_pn:value=
"Store all values"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"ROM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"ROM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Read Cores"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Reduce Control Sets"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Regenerate Core"
xil_pn:value=
"Under Current Project Setting"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Balancing"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Duplication Map"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Duplication Xst"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Register Ordering spartan6"
xil_pn:value=
"4"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Release Write Enable (Output Events)"
xil_pn:value=
"Default (6)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Design Instance in Testbench File to"
xil_pn:value=
"UUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Architecture To"
xil_pn:value=
"Structure"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Entity to"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Rename Top Level Module To"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Fastest Path(s) in Each Constraint"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Fastest Path(s) in Each Constraint Post Trace"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Paths by Endpoint"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Paths by Endpoint Post Trace"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Type"
xil_pn:value=
"Verbose Report"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Type Post Trace"
xil_pn:value=
"Verbose Report"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Unconstrained Paths"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Report Unconstrained Paths Post Trace"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Reset On Configuration Pulse Width"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Resource Sharing"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Retain Hierarchy"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Retry Configuration if CRC Error Occurs spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run Design Rules Checker (DRC)"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time Map"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time Par"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Run for Specified Time Translate"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Safe Implementation"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Security"
xil_pn:value=
"Enable Readback and Reconfiguration"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Route"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Source Node"
xil_pn:value=
"UUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Set SPI Configuration Bus Width spartan6"
xil_pn:value=
"1"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Setup External Master Clock Division spartan6"
xil_pn:value=
"1"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Shift Register Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Shift Register Minimum Size spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Show All Models"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Model Target"
xil_pn:value=
"Verilog"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time ISim"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Map"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Par"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Translate"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulator"
xil_pn:value=
"ISim (VHDL/Verilog)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Slice Utilization Ratio"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify 'define Macro Name and Value"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Map"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Route"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Translate"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Speed Grade"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Starting Placer Cost Table (1-100) Map spartan6"
xil_pn:value=
"1"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Synthesis Tool"
xil_pn:value=
"XST (VHDL/Verilog)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Target Simulator"
xil_pn:value=
"Please Specify"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Timing Mode Map"
xil_pn:value=
"Performance Evaluation"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Timing Mode Par"
xil_pn:value=
"Performance Evaluation"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Top-Level Module Name in Output Netlist"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Top-Level Source Type"
xil_pn:value=
"HDL"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Trim Unconnected Signals"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Tristate On Configuration Pulse Width"
xil_pn:value=
"0"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Unused IOB Pins"
xil_pn:value=
"Pull Down"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use 64-bit PlanAhead on 64-bit Systems"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Clock Enable"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Behavioral"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Post-Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Post-Route"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Project File Post-Translate"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Simulation Command File Behavioral"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Simulation Command File Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Simulation Command File Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Simulation Command File Translate"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Waveform Configuration File Behav"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Waveform Configuration File Map"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Waveform Configuration File Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Custom Waveform Configuration File Translate"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use DSP Block spartan6"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use LOC Constraints"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use RLOC Constraints"
xil_pn:value=
"Yes"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Smart Guide"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synchronous Reset"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synchronous Set"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synthesis Constraints File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"UserID Code (8 Digit Hexadecimal)"
xil_pn:value=
"0xFFFFFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VCCAUX Voltage Level spartan6"
xil_pn:value=
"2.5V"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VHDL Source Analysis Standard"
xil_pn:value=
"VHDL-93"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Value Range Check"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Verilog Macros"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wait for DCM and PLL Lock (Output Events) spartan6"
xil_pn:value=
"Default (NoWait)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wakeup Clock spartan6"
xil_pn:value=
"Startup Clock"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Watchdog Timer Value spartan6"
xil_pn:value=
"0xFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Working Directory"
xil_pn:value=
"."
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Write Timing Constraints"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property
xil_pn:name=
"PROP_BehavioralSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_DesignName"
xil_pn:value=
"flash_load"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_DevFamilyPMName"
xil_pn:value=
"spartan6"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_FPGAConfiguration"
xil_pn:value=
"FPGAConfiguration"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PostMapSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PostParSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PostSynthSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PostXlateSimTop"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_PreSynthesis"
xil_pn:value=
"PreSynthesis"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_intProjectCreationTimestamp"
xil_pn:value=
"2013-05-15T14:32:09"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWbtProjectID"
xil_pn:value=
"17441D530B2D0CF759769C6CA437BBB8"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWorkingDirLocWRTProjDir"
xil_pn:value=
"Same"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_intWorkingDirUsed"
xil_pn:value=
"No"
xil_pn:valueState=
"non-default"
/>
</properties>
<libraries/>
<files>
<file
xil_pn:name=
"../top/flash_load.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1"
/>
</file>
<file
xil_pn:name=
"../top/flash_load.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2"
/>
</file>
</files>
<bindings/>
<version
xil_pn:ise_version=
"14.2"
xil_pn:schema_version=
"2"
/>
</project>
hdl/flash_load/syn/run.tcl
0 → 100644
View file @
706c104c
project open flash_load.xise
process run
{
Generate Programming File
}
-force rerun_all
hdl/flash_load/top/Manifest.py
0 → 100644
View file @
706c104c
files
=
[
"flash_load.v"
,
"flash_load.ucf"
]
hdl/flash_load/top/flash_load.ucf
0 → 100644
View file @
706c104c
net "MOSI" LOC = "AB20";
net "MISO" LOC = "AA20";
net "DRCK1" LOC = "Y20";
net "CSB" LOC = "AA3";
hdl/flash_load/top/flash_load.v
0 → 100644
View file @
706c104c
module
flash_load
(
output
wire
MOSI
,
output
wire
CSB
,
output
wire
DRCK1
,
input
MISO
)
;
wire
CAPTURE
;
wire
UPDATE
;
wire
TDI
;
reg
TDO1
;
reg
[
47
:
0
]
header
;
reg
[
15
:
0
]
len
;
reg
have_header
=
0
;
assign
MOSI
=
TDI
;
wire
SEL1
;
wire
SHIFT
;
wire
RESET
;
reg
CS_GO
=
0
;
reg
CS_GO_PREP
=
0
;
reg
CS_STOP
=
0
;
reg
CS_STOP_PREP
=
0
;
reg
[
13
:
0
]
RAM_RADDR
;
reg
[
13
:
0
]
RAM_WADDR
;
wire
DRCK1_INV
=
!
DRCK1
;
wire
RAM_DO
;
wire
RAM_DI
;
reg
RAM_WE
=
0
;
RAMB16_S1_S1
RAMB16_S1_S1_inst
(
.
DOA
(
RAM_DO
)
,
.
DOB
()
,
.
ADDRA
(
RAM_RADDR
)
,
.
ADDRB
(
RAM_WADDR
)
,
.
CLKA
(
DRCK1_INV
)
,
.
CLKB
(
DRCK1
)
,
.
DIA
(
1'b0
)
,
.
DIB
(
RAM_DI
)
,
.
ENA
(
1'b1
)
,
.
ENB
(
1'b1
)
,
.
SSRA
(
1'b0
)
,
.
SSRB
(
1'b0
)
,
.
WEA
(
1'b0
)
,
.
WEB
(
RAM_WE
)
)
;
BSCAN_SPARTAN6
BSCAN_SPARTAN6_inst
(
.
CAPTURE
(
CAPTURE
)
,
.
DRCK
(
DRCK1
)
,
.
RESET
(
RESET
)
,
.
RUNTEST
()
,
.
SEL
(
SEL1
)
,
.
SHIFT
(
SHIFT
)
,
.
TCK
()
,
.
TDI
(
TDI
)
,
.
TMS
()
,
.
UPDATE
(
UPDATE
)
,
.
TDO
(
TDO1
)
)
;
assign
CSB
=
!
(
CS_GO
&&
!
CS_STOP
)
;
assign
RAM_DI
=
MISO
;
always
@
(
posedge
DRCK1
)
TDO1
<=
RAM_DO
;
wire
rst
=
CAPTURE
||
RESET
||
UPDATE
||
!
SEL1
;
always
@
(
negedge
DRCK1
or
posedge
rst
)
if
(
rst
)
begin
have_header
<=
0
;
CS_GO_PREP
<=
0
;
CS_STOP
<=
0
;
end
else
begin
CS_STOP
<=
CS_STOP_PREP
;
if
(
!
have_header
)
begin
if
(
header
[
46
:
15
]
==
32'h59a659a6
)
begin
len
<=
{
header
[
14
:
0
]
,
1'b0
};
have_header
<=
1
;
if
(
{
header
[
14
:
0
]
,
1'b0
}
!=
0
)
begin
CS_GO_PREP
<=
1
;
end
end
end
else
if
(
len
!=
0
)
begin
len
<=
len
-
1
;
end
// if (!have_header)
end
// else: !if(CAPTRE || RESET || UPDATE || !SEL1)
always
@
(
posedge
DRCK1
or
posedge
rst
)
if
(
rst
)
begin
CS_GO
<=
0
;
CS_STOP_PREP
<=
0
;
RAM_WADDR
<=
0
;
RAM_RADDR
<=
0
;
RAM_WE
<=
0
;
end
else
begin
RAM_RADDR
<=
RAM_RADDR
+
1
;
RAM_WE
<=
!
CSB
;
if
(
RAM_WE
)
RAM_WADDR
<=
RAM_WADDR
+
1
;
header
<=
{
header
[
46
:
0
]
,
TDI
};
CS_GO
<=
CS_GO_PREP
;
if
(
CS_GO
&&
(
len
==
0
))
CS_STOP_PREP
<=
1
;
end
// else: !if(CAPTURE || RESET || UPDATE || !SEL1)
endmodule
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