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Conv TTL Blocking
Commit cdc38585 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Fix grab holes in RTM Interface Tester board

parent c4f77a46
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hdl/pts/rtl/pts_regs.vhd
View file @ cdc38585
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pts_regs.vhd
-- Author : auto-generated by wbgen2 from pts_regs.wb
-- Created : Tue Apr 30 11:25:57 2013
-- Created : Fri May 3 17:05:11 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pts_regs.wb
......@@ -31,6 +31,8 @@ entity pts_regs is
pts_csr_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for BIT field: 'reset' in reg: 'control and status register'
pts_csr_rst_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'control and status register'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'control and status register'
pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID'
......@@ -92,7 +94,8 @@ begin
end if;
rddata_reg(3 downto 0) <= pts_csr_crrt_test_int;
rddata_reg(15) <= pts_csr_rst_int;
rddata_reg(21 downto 16) <= pts_csr_rtm_i;
rddata_reg(23 downto 16) <= pts_csr_switch_i;
rddata_reg(29 downto 24) <= pts_csr_rtm_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
......@@ -104,14 +107,6 @@ begin
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
......@@ -140,6 +135,7 @@ begin
pts_csr_crrt_test_o <= pts_csr_crrt_test_int;
-- reset
pts_csr_rst_o <= pts_csr_rst_int;
-- switches
-- RTM
-- bits
pts_id_bits_o <= pts_id_bits_int;
......
hdl/pts/rtl/pts_regs.wb
View file @ cdc38585
......@@ -23,11 +23,20 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "switches";
prefix = "switch";
type = SLV;
align = 16;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RTM";
prefix = "rtm";
type = SLV;
align = 16;
align = 24;
size = 6;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......
hdl/pts/syn/conv_ttl_blo_v2.gise 0 → 100644
View file @ cdc38585
This diff is collapsed.
hdl/pts/syn/conv_ttl_blo_v2.mcs
View file @ cdc38585
This diff is collapsed.
hdl/pts/syn/conv_ttl_blo_v2.prm
View file @ cdc38585
......@@ -3,7 +3,7 @@ Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
promgen -spi -w -u 0 conv_ttl_blo_v2.bit
PROM conv_ttl_blo_v2.prm map: Wed Mar 27 16:36:24 2013
PROM conv_ttl_blo_v2.prm map: Fri May 3 15:37:57 2013
Format Mcs86 (32-bit)
Size 2048K
......@@ -11,4 +11,4 @@ PROM start 0000:0000
PROM end 001f:ffff
Addr1 Addr2 Date File(s)
0000:0000 0016:a673 Mar 27 14:19:40 2013 conv_ttl_blo_v2.bit
0000:0000 0016:a78b May 3 15:20:29 2013 conv_ttl_blo_v2.bit
hdl/pts/syn/conv_ttl_blo_v2.xise
View file @ cdc38585
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/pts/syn/run.tcl 0 → 100644
View file @ cdc38585
project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
hdl/pts/top/conv_ttl_blo_v2.ucf
View file @ cdc38585
......@@ -339,26 +339,26 @@ NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
###-------------------
###-- Configuration Switches
###
###-- Schematics name EXTRA_SWITCH_*
###---- renamed to extra_switch_n_i[*]
###-------------------
#NET "extra_switch_n_i[1]" LOC = F22;
#NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33";
## NET "extra_switch_n_i[2]" LOC = G22;
## NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33";
## NET "extra_switch_n_i[3]" LOC = H21;
## NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33";
## NET "extra_switch_n_i[4]" LOC = H22;
## NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33";
## NET "extra_switch_n_i[5]" LOC = J22;
## NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33";
## NET "extra_switch_n_i[6]" LOC = K21;
## NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33";
## NET "extra_switch_n_i[7]" LOC = K22;
## NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
##-------------------
##-- Configuration Switches
##
##-- Schematics name EXTRA_SWITCH_*
##---- renamed to extra_switch_n_i[*]
##-------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-------------------
......
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @ cdc38585
......@@ -122,7 +122,7 @@ entity conv_ttl_blo_v2 is
-- TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
-- extra_switch_n_i : in std_logic_vector(7 downto 1);
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- It allows power sequencing of the
-- 24V rail after a security given delay
......@@ -354,6 +354,8 @@ architecture behav of conv_ttl_blo_v2 is
pts_csr_crrt_test_o : out std_logic_vector(3 downto 0);
-- Port for BIT field: 'reset' in reg: 'control and status register'
pts_csr_rst_o : out std_logic;
-- Port for std_logic_vector field: 'switches' in reg: 'control and status register'
pts_csr_switch_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM' in reg: 'control and status register'
pts_csr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID'
......@@ -677,6 +679,7 @@ architecture behav of conv_ttl_blo_v2 is
signal cnt_blo_out : t_blo_pulse_counter;
signal rtm_lines : std_logic_vector(5 downto 0);
signal switches : std_logic_vector(7 downto 0);
signal dumled : std_logic_vector(6 downto 1);
......@@ -856,8 +859,9 @@ begin
--============================================================================
-- PTS registers
--============================================================================
-- Assign the RTM detection lines signal
rtm_lines <= fpga_rtmp_n_i & fpga_rtmm_n_i;
-- Assign the RTM detection lines and switches signals
rtm_lines <= fpga_rtmp_n_i & fpga_rtmm_n_i;
switches <= ttl_switch_n_i & extra_switch_n_i;
-- Regs to test I2C operation
cmp_pts_regs: pts_regs
......@@ -878,13 +882,14 @@ begin
-- PTS control register
pts_csr_crrt_test_o => pts_crrt_test_slv,
pts_csr_rst_o => rst_fr_reg,
pts_csr_switch_i => switches,
pts_csr_rtm_i => rtm_lines,
-- PTS ID register
pts_id_bits_o => open
);
-- Assign the unsigned )current test signal
-- Assign the unsigned current test signal
pts_crrt_test <= unsigned(pts_crrt_test_slv);
--============================================================================
......
pcb/PTS_P2_Board/PTS_P2_Board.OutJob deleted 100644 → 0
View file @ c4f77a46
[OutputJobFile]
Version=1.0
[OutputGroup1]
Name=
Description=
TargetOutputMedium=PDF
VariantName=[No Variations]
VariantScope=0
CurrentConfigurationName=
TargetPrinter=\\CERNPRINTHP\864-1A17-HPCOL
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputMedium1=Print Job
OutputMedium1_Type=Printer
OutputMedium1_Printer=
OutputMedium1_PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputMedium2=PDF
OutputMedium2_Type=Publish
OutputMedium3=Folder Structure
OutputMedium3_Type=GeneratedFiles
OutputMedium4=Video
OutputMedium4_Type=Multimedia
OutputType1=Schematic Print
OutputName1=Schematic Prints of PTS_P2_Board.SchDoc
OutputCategory1=Documentation
OutputDocumentPath1=PTS_P2_Board.SchDoc
OutputVariantName1=
OutputEnabled1=1
OutputEnabled1_OutputMedium1=0
OutputEnabled1_OutputMedium2=1
OutputEnabled1_OutputMedium3=0
OutputEnabled1_OutputMedium4=0
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=0.71|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
Configuration1_Name1=OutputConfigurationParameter1
Configuration1_Item1=Record=SchPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False|PrintArea=0|PrintAreaRect.X1=0|PrintAreaRect.Y1=0|PrintAreaRect.X2=0|PrintAreaRect.Y2=0
[PublishSettings]
OutputFilePath2=\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\PTS_P2_Board.pdf
ReleaseManaged2=0
OutputBasePath2=\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\
OutputPathMedia2=
OutputPathOutputer2=[Output Type]
OutputFileName2=PTS_P2_Board.pdf
OpenOutput2=1
PromptOverwrite2=1
PublishMethod2=0
ZoomLevel2=50
FitSCHPrintSizeToDoc2=0
FitPCBPrintSizeToDoc2=0
GenerateNetsInfo2=1
MarkPins2=1
MarkNetLabels2=1
MarkPortsId2=1
GenerateTOC=1
OutputFilePath3=\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\Project Outputs for PTS_P2_Board\
ReleaseManaged3=1
OutputBasePath3=Project Outputs for PTS_P2_Board
OutputPathMedia3=
OutputPathOutputer3=[Output Type]
OutputFileName3=
OpenOutput3=1
OutputFilePath4=\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\Project Outputs for PTS_P2_Board\
ReleaseManaged4=1
OutputBasePath4=Project Outputs for PTS_P2_Board
OutputPathMedia4=
OutputPathOutputer4=[Output Type]
OutputFileName4=
OpenOutput4=1
PromptOverwrite4=1
PublishMethod4=5
ZoomLevel4=50
FitSCHPrintSizeToDoc4=1
FitPCBPrintSizeToDoc4=1
GenerateNetsInfo4=1
MarkPins4=1
MarkNetLabels4=1
MarkPortsId4=1
MediaFormat4=Windows Media file (*.wmv,*.wma,*.asf)
FixedDimensions4=1
Width4=352
Height4=288
MultiFile4=0
FramesPerSecond4=25
FramesPerSecondDenom4=1
AviPixelFormat4=7
AviCompression4=MP42 MS-MPEG4 V2
AviQuality4=100
FFmpegVideoCodecId4=13
FFmpegPixelFormat4=0
FFmpegQuality4=80
WmvVideoCodecName4=Windows Media Video V7
WmvQuality4=80
[GeneratedFilesSettings]
RelativeOutputPath2=\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\PTS_P2_Board.pdf
OpenOutputs2=1
RelativeOutputPath3=\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\Project Outputs for PTS_P2_Board\
OpenOutputs3=1
AddToProject3=1
TimestampFolder3=0
UseOutputName3=0
OpenODBOutput3=0
OpenGerberOutput3=0
OpenNCDrillOutput3=0
OpenIPCOutput3=0
EnableReload3=0
RelativeOutputPath4=\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\Project Outputs for PTS_P2_Board\
OpenOutputs4=1
pcb/PTS_P2_Board/PTS_P2_Board.PrjPCBStructure deleted 100644 → 0
View file @ c4f77a46
Record=TopLevelDocument|FileName=PTS_P2_Board.SchDoc
pcb/PTS_P2_Board/Project Logs for PTS_P2_Board/PTS_P2_Board PCB ECO 4-25-2013 11-18-35 AM.LOG deleted 100644 → 0
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Added Component: Designator=D1(DIOM5336X265N)
Added Component: Designator=D2(DIOM5336X265N)
Added Component: Designator=D3(DIOM5336X265N)
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Added Component: Designator=D5(DIOM5336X265N)
Added Component: Designator=D6(DIOM5336X265N)
Added Component: Designator=P2(HARTING_02 01 160 2101)
Added Component: Designator=R1(RESC3216X65N)
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Added Component: Designator=R10(RESC3216X65N)
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Added Component: Designator=R14(RESC3216X65N)
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Added Component: Designator=R16(RESC3216X65N)
Added Component: Designator=R17(RESC3216X65N)
Added Component: Designator=R18(RESC3216X65N)
Added Pin To Net: NetName=BLO_C_1_N Pin=D1-2
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Added Pin To Net: NetName=BLO_C_1_N Pin=P2-d14
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Added Pin To Net: NetName=BLO_C_1_N Pin=P2-d23
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Added Pin To Net: NetName=BLO_C_1_N Pin=P2-MTG2
Added Pin To Net: NetName=BLO_C_1_N Pin=P2-z2
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Added Pin To Net: NetName=BLO_C_1_N Pin=P2-z16
Added Pin To Net: NetName=BLO_C_1_N Pin=P2-z18
Added Pin To Net: NetName=BLO_C_1_N Pin=P2-z20
Added Pin To Net: NetName=BLO_C_1_N Pin=P2-z22
Added Pin To Net: NetName=BLO_C_1_N Pin=P2-z24
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Added Pin To Net: NetName=BLO_C_1_N Pin=P2-z28
Added Pin To Net: NetName=BLO_C_1_N Pin=P2-z30
Added Pin To Net: NetName=BLO_C_1_N Pin=P2-z32
Added Net: Name=BLO_C_1_N
Added Pin To Net: NetName=BLO_C_1_P Pin=D2-1
Added Pin To Net: NetName=BLO_C_1_P Pin=P2-c3
Added Pin To Net: NetName=BLO_C_1_P Pin=P2-c9
Added Pin To Net: NetName=BLO_C_1_P Pin=P2-c27
Added Pin To Net: NetName=BLO_C_1_P Pin=R4-1
Added Net: Name=BLO_C_1_P
Added Pin To Net: NetName=BLO_C_2_P Pin=D3-1
Added Pin To Net: NetName=BLO_C_2_P Pin=P2-c2
Added Pin To Net: NetName=BLO_C_2_P Pin=P2-c8
Added Pin To Net: NetName=BLO_C_2_P Pin=P2-c14
Added Pin To Net: NetName=BLO_C_2_P Pin=R7-1
Added Net: Name=BLO_C_2_P
Added Pin To Net: NetName=BLO_C_3_P Pin=D4-1
Added Pin To Net: NetName=BLO_C_3_P Pin=P2-c7
Added Pin To Net: NetName=BLO_C_3_P Pin=P2-c13
Added Pin To Net: NetName=BLO_C_3_P Pin=P2-c19
Added Pin To Net: NetName=BLO_C_3_P Pin=R10-1
Added Net: Name=BLO_C_3_P
Added Pin To Net: NetName=BLO_C_4_P Pin=D5-1
Added Pin To Net: NetName=BLO_C_4_P Pin=P2-c12
Added Pin To Net: NetName=BLO_C_4_P Pin=P2-c18
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Added Net: Name=BLO_C_4_P
Added Pin To Net: NetName=BLO_C_5_P Pin=D6-1
Added Pin To Net: NetName=BLO_C_5_P Pin=P2-c17
Added Pin To Net: NetName=BLO_C_5_P Pin=P2-c23
Added Pin To Net: NetName=BLO_C_5_P Pin=P2-c29
Added Pin To Net: NetName=BLO_C_5_P Pin=R16-1
Added Net: Name=BLO_C_5_P
Added Pin To Net: NetName=BLO_C_6_P Pin=D1-1
Added Pin To Net: NetName=BLO_C_6_P Pin=P2-c4
Added Pin To Net: NetName=BLO_C_6_P Pin=P2-c22
Added Pin To Net: NetName=BLO_C_6_P Pin=P2-c28
Added Pin To Net: NetName=BLO_C_6_P Pin=R1-1
Added Net: Name=BLO_C_6_P
Added Pin To Net: NetName=BLO_IN_1_P Pin=P2-a5
Added Pin To Net: NetName=BLO_IN_1_P Pin=R3-2
Added Net: Name=BLO_IN_1_P
Added Pin To Net: NetName=BLO_IN_2_P Pin=P2-a10
Added Pin To Net: NetName=BLO_IN_2_P Pin=R6-2
Added Net: Name=BLO_IN_2_P
Added Pin To Net: NetName=BLO_IN_3_P Pin=P2-a15
Added Pin To Net: NetName=BLO_IN_3_P Pin=R9-2
Added Net: Name=BLO_IN_3_P
Added Pin To Net: NetName=BLO_IN_4_P Pin=P2-a20
Added Pin To Net: NetName=BLO_IN_4_P Pin=R12-2
Added Net: Name=BLO_IN_4_P
Added Pin To Net: NetName=BLO_IN_5_P Pin=P2-a25
Added Pin To Net: NetName=BLO_IN_5_P Pin=R15-2
Added Net: Name=BLO_IN_5_P
Added Pin To Net: NetName=BLO_IN_6_P Pin=P2-a30
Added Pin To Net: NetName=BLO_IN_6_P Pin=R18-2
Added Net: Name=BLO_IN_6_P
Added Pin To Net: NetName=NetR1_2 Pin=R1-2
Added Pin To Net: NetName=NetR1_2 Pin=R2-1
Added Net: Name=NetR1_2
Added Pin To Net: NetName=NetR2_2 Pin=R2-2
Added Pin To Net: NetName=NetR2_2 Pin=R3-1
Added Net: Name=NetR2_2
Added Pin To Net: NetName=NetR4_2 Pin=R4-2
Added Pin To Net: NetName=NetR4_2 Pin=R5-1
Added Net: Name=NetR4_2
Added Pin To Net: NetName=NetR5_2 Pin=R5-2
Added Pin To Net: NetName=NetR5_2 Pin=R6-1
Added Net: Name=NetR5_2
Added Pin To Net: NetName=NetR7_2 Pin=R7-2
Added Pin To Net: NetName=NetR7_2 Pin=R8-1
Added Net: Name=NetR7_2
Added Pin To Net: NetName=NetR8_2 Pin=R8-2
Added Pin To Net: NetName=NetR8_2 Pin=R9-1
Added Net: Name=NetR8_2
Added Pin To Net: NetName=NetR10_2 Pin=R10-2
Added Pin To Net: NetName=NetR10_2 Pin=R11-1
Added Net: Name=NetR10_2
Added Pin To Net: NetName=NetR11_2 Pin=R11-2
Added Pin To Net: NetName=NetR11_2 Pin=R12-1
Added Net: Name=NetR11_2
Added Pin To Net: NetName=NetR13_2 Pin=R13-2
Added Pin To Net: NetName=NetR13_2 Pin=R14-1
Added Net: Name=NetR13_2
Added Pin To Net: NetName=NetR14_2 Pin=R14-2
Added Pin To Net: NetName=NetR14_2 Pin=R15-1
Added Net: Name=NetR14_2
Added Pin To Net: NetName=NetR16_2 Pin=R16-2
Added Pin To Net: NetName=NetR16_2 Pin=R17-1
Added Net: Name=NetR16_2
Added Pin To Net: NetName=NetR17_2 Pin=R17-2
Added Pin To Net: NetName=NetR17_2 Pin=R18-1
Added Net: Name=NetR17_2
Added Pin To Net: NetName=RTMM0_LED1 Pin=P2-z1
Added Pin To Net: NetName=RTMM0_LED1 Pin=P2-z3
Added Net: Name=RTMM0_LED1
Added Pin To Net: NetName=RTMM1_LED2 Pin=P2-a1
Added Pin To Net: NetName=RTMM1_LED2 Pin=P2-z9
Added Net: Name=RTMM1_LED2
Added Pin To Net: NetName=RTMM2_LED3 Pin=P2-a2
Added Pin To Net: NetName=RTMM2_LED3 Pin=P2-z13
Added Net: Name=RTMM2_LED3
Added Pin To Net: NetName=RTMP0_LED4 Pin=P2-z19
Added Pin To Net: NetName=RTMP0_LED4 Pin=P2-z25
Added Net: Name=RTMP0_LED4
Added Pin To Net: NetName=RTMP1_LED5 Pin=P2-z23
Added Pin To Net: NetName=RTMP1_LED5 Pin=P2-z27
Added Net: Name=RTMP1_LED5
Added Pin To Net: NetName=RTMP2_LED6 Pin=P2-z29
Added Pin To Net: NetName=RTMP2_LED6 Pin=P2-z31
Added Net: Name=RTMP2_LED6
Added Class: Name=PTS_P2_Board
Added Room: Name=PTS_P2_Board
pcb/PTS_P2_Board/Project Logs for PTS_P2_Board/PTS_P2_Board PCB ECO 4-26-2013 10-21-53 AM.LOG deleted 100644 → 0
View file @ c4f77a46
Change Component DesignItemId : Designator=P2 Old DesignItemId=HARTING_02 01 160 2101 New DesignItemId=HARTING_02 04 160 1101
Change Component Footprint: Designator=P2 Old Footprint=HARTING_02 01 160 2101 New Footprint=HARTING_02 04 160 1101
Added Member To Class: ClassName=PTS_P2_Board Member=Component D1 SMBJ30CA
Added Member To Class: ClassName=PTS_P2_Board Member=Component D2 SMBJ30CA
Added Member To Class: ClassName=PTS_P2_Board Member=Component D3 SMBJ30CA
Added Member To Class: ClassName=PTS_P2_Board Member=Component P2 HAR-BUS 64
Added Member To Class: ClassName=PTS_P2_Board Member=Component R1 51
Added Member To Class: ClassName=PTS_P2_Board Member=Component R2 51
Added Member To Class: ClassName=PTS_P2_Board Member=Component R3 51
Added Member To Class: ClassName=PTS_P2_Board Member=Component R4 51
Added Member To Class: ClassName=PTS_P2_Board Member=Component R5 51
Added Member To Class: ClassName=PTS_P2_Board Member=Component R6 51
Added Member To Class: ClassName=PTS_P2_Board Member=Component R7 51
Added Member To Class: ClassName=PTS_P2_Board Member=Component R8 51
Added Member To Class: ClassName=PTS_P2_Board Member=Component R9 51
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.DRL deleted 100644 → 0
View file @ c4f77a46
TT#v 2 s k #v 2 sk #v 2 sk #v 2 sk # 7 8 7 8 7 7 7 8 7 7 7 7 8 7 # 7 8 7 7 7 7  7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7  7 7  7 7 7 7  7 7 7 7  8 8 8  8 7 7 7 8  7 7 8 7 7 8 7 7 7  8 8  8 7 7 8  7 8 7 8 7 7 8 8  8 7  7 7  7 8  7  7 7  8 7 7  7 8 7  7 7  7 8 8  8 7 7 7 7 7 7 8  7 7 7 7 7 8 7 7 7 7 7 8 7 7 7 7 7 7 7 8 7 8  7 8 7 7 7 7  7 7 7 7 7 7 8  7 7 7 7 7 7  7 7 8 7 7  7 7 7 7 7 7 8 7 7 7 7 7 7  7 7 7 8 8  8 7 8  8 8 # 7 8 7 # 7 8 7 7 T
\ No newline at end of file
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.TXT deleted 100644 → 0
View file @ c4f77a46
M48
;Layer_Color=9474304
;FILE_FORMAT=4:2
METRIC,LZ
;TYPE=PLATED
T1F00S00C0.50
T2F00S00C1.00
T3F00S00C2.80
T4F00S00C3.00
%
T01
X0018Y00289
X003Y0029
X0044
X0056
X00398Y0017
X00272
X00653
X00791
X0082Y0029
X0069
T02
X005888Y000277
X006142
X006396
X00665
X006904
X007158
X007412
X007666
X00792
X008174
X008428
X008682
X008936
X005634
X00538
X005126
X004872
X004618
X004364
X00411
X003856
X003602
X003348
X003094
X00284
X002586
X002332
X002078
X001824
X00157
X001316
X001062
Y000531
Y000785
Y001039
Y001293
X001316
X00157
X001824
Y001039
X00157
X001316
Y000785
X00157
X001824
Y000531
X00157
X001316
X002078
Y000785
Y001039
Y001293
X002332
X002586
Y001039
X002332
Y000785
X002586
Y000531
X002332
X00284
Y000785
Y001039
Y001293
X003094
X003348
X003602
X003856
Y001039
X003602
X003348
X003094
Y000785
X003348
X003602
X003856
Y000531
X003602
X003348
X003094
X00411
Y000785
Y001039
Y001293
X004364
X004618
X004872
X005126
X00538
X005634
Y001039
X00538
X005126
X004872
X004618
X004364
Y000785
X004618
X004872
X005126
X00538
X005634
Y000531
X00538
X005126
X004872
X004618
X004364
X005888
X006142
Y000785
X005888
Y001039
X006142
Y001293
X005888
X006396
X00665
X006904
X007158
X007412
X007666
X00792
X008174
X008428
Y001039
X008174
X00792
X007666
X007412
X007158
X006904
X00665
X006396
Y000785
X00665
X006904
X007158
X007412
X007666
X00792
X008174
X008428
Y000531
X008174
X00792
X007666
X007412
X007158
X006904
X00665
X006396
X008682
Y000785
Y001039
Y001293
X008936
Y001039
Y000785
Y000531
T03
X009444Y000277
X000554
T04
X0003Y004
X005
X0097
M30
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/Status Report.Txt deleted 100644 → 0
View file @ c4f77a46
Output: Bill of Materials
Type : BOM
From : Variant [[No Variations]] of Project [PTS_P2_Board.PrjPCB]
Files Generated : 0
Documents Printed : 0
Finished Output Generation At 11:21:07 AM On 5/3/2013
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/Design Rule Check - PTS_P2_Board.html → pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/Design Rule Check - RTM_Interface_Tester.html
View file @ cdc38585
......@@ -230,22 +230,22 @@
<tr class="front_matter">
<td class="front_matter_column1">Date</td>
<td class="front_matter_column2">:</td>
<td class="front_matter_column3">29/04/2013</td>
<td class="front_matter_column3">5/14/2013</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time</td>
<td class="front_matter_column2">:</td>
<td class="front_matter_column3">15:20:47</td>
<td class="front_matter_column3">12:37:34 PM</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time</td>
<td class="front_matter_column2">:</td>
<td class="front_matter_column3">00:00:01</td>
<td class="front_matter_column3">00:00:00</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Filename</td>
<td class="front_matter_column2">:</td>
<td class="front_matter_column3"><a href="file:///\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\PTS_P2_Board.PcbDoc" class="file"><acronym title="\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\PTS_P2_Board.PcbDoc">\\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\PTS_P2_Board.PcbDoc</acronym></a></td>
<td class="front_matter_column3"><a href="file:///\\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc" class="file"><acronym title="\\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc">\\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc</acronym></a></td>
</tr>
</table>
</td>
......@@ -262,7 +262,7 @@
</table>
</td>
</table>
<hr><a name="IDASA4LC"><h2>Summary</h2></a><table>
<hr><a name="IDASA0TC"><h2>Summary</h2></a><table>
<tr>
<th class="column1">Warnings</th>
<th class="column2">Count</th>
......@@ -277,55 +277,55 @@
<th class="column2">Count</th>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAEB4LC">Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=1mm) (InNet('BLO_C_1_N'))</a></td>
<td class="column1"><a href="#IDAEB0TC">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDAKB4LC">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column1"><a href="#IDAKB0TC">Clearance Constraint (Gap=0.17mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAQB4LC">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column1"><a href="#IDAQB0TC">Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDAWB4LC">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
<td class="column1"><a href="#IDAWB0TC">Net Antennae (Tolerance=0mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDA2B4LC">Hole Size Constraint (Min=0.025mm) (Max=3mm) (All)</a></td>
<td class="column1"><a href="#IDA2B0TC">Silk to Silk (Clearance=0.254mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDACC4LC">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
<td class="column1"><a href="#IDACC0TC">Silkscreen Over Component Pads (Clearance=0.1mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAIC4LC">Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)</a></td>
<td class="column1"><a href="#IDAIC0TC">Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDAOC4LC">Silkscreen Over Component Pads (Clearance=0.1mm) (All),(All)</a></td>
<td class="column1"><a href="#IDAOC0TC">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAUC4LC">Silk to Silk (Clearance=0.254mm) (All),(All)</a></td>
<td class="column1"><a href="#IDAUC0TC">Hole Size Constraint (Min=0.025mm) (Max=3mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDA0C4LC">Net Antennae (Tolerance=0mm) (All)</a></td>
<td class="column1"><a href="#IDA0C0TC">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAAD4LC">Width Constraint (Min=0.2mm) (Max=1mm) (Preferred=0.254mm) (All)</a></td>
<td class="column1"><a href="#IDAAD0TC">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDAGD4LC">Clearance Constraint (Gap=0.17mm) (All),(All)</a></td>
<td class="column1"><a href="#IDAGD0TC">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAMD4LC">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
<td class="column1"><a href="#IDAMD0TC">Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=1mm) (InNet('BLO_C_1_N'))</a></td>
<td class="column2">0</td>
</tr>
<tr>
......
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.DRL 0 → 100644
View file @ cdc38585
TT#v 2 s k #v 2 sk #v 2 sk #v 2 sk # 7 8 7 8 7 7 7 8 7 7 7 7 8 7 # 7 8 7 7 7 7  7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7  7 7 7 7 7 7 7 7 7 7 8 8 8  8 7 7 7 8  7 7 8 7 7 8 7 7 7 8 8  8 7 7 8  7 8 7 8 7 7 8 8  8 7 7 7  7 8  7  7 7 8 7 7  7 8 7  7 7 7 8 8  8 7 7 7 7 7 7 8  7 7 7 7 7 8 7 7 7 7 7 8 7 7 7 7 7 7 7 8 7 8  7 8 7 7 7 7  7 7 7 7 7 7 8  7 7 7 7 7 7  7 7 8 7 7  7 7 7 7 7 7 8 7 7 7 7 7 7  7 7 7 8 8  8 7 8  8 8 # 7 8 7 # 7 8 7 7 T
\ No newline at end of file
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.DRR → pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.DRR
View file @ cdc38585
---------------------------------------------------------------------------
NCDrill File Report For: PTS_P2_Board.PcbDoc 29/04/2013 15:21:44
NCDrill File Report For: RTM_Interface_Tester.PcbDoc 5/14/2013 12:53:44 PM
---------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
ASCII RoundHoles File : PTS_P2_Board.TXT
EIA File : PTS_P2_Board.DRL
ASCII RoundHoles File : RTM_Interface_Tester.TXT
EIA File : RTM_Interface_Tester.DRL
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 0.5mm (19.685mil) Round 10 148.01 mm (5.83 Inch)
T2 1mm (39.37mil) Round 160 485.14 mm (19.10 Inch)
T3 2.8mm (110.236mil) Round 2 88.90 mm (3.50 Inch)
T4 3mm (118.11mil) Round 3 94.00 mm (3.70 Inch)
T4 3mm (118.11mil) Round 3 90.00 mm (3.54 Inch)
---------------------------------------------------------------------------
Totals 175 816.05 mm (32.13 Inch)
Totals 175 812.05 mm (31.97 Inch)
Total Processing Time (hh:mm:ss) : 00:00:00
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.EXTREP → pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.EXTREP
View file @ cdc38585
------------------------------------------------------------------------------------------
Gerber File Extension Report For: PTS_P2_Board.GBR 29/04/2013 15:21:22
Gerber File Extension Report For: RTM_Interface_Tester.GBR 5/14/2013 12:53:31 PM
------------------------------------------------------------------------------------------
......
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.GBS → pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.GBS
View file @ cdc38585
......@@ -23,357 +23,357 @@ G04 Layer_Color=16711935*
%ADD26C,1.20*%
%ADD27C,5.30*%
D23*
X5000Y4000D02*
X4800Y3900D02*
D03*
X9700D02*
X9300D02*
D03*
X300D02*
D03*
D24*
X7158Y1293D02*
X6958Y1293D02*
D03*
X7412D02*
X7212D02*
D03*
X7666D02*
X7466D02*
D03*
X7920D02*
X7720D02*
D03*
X8174D02*
X7974D02*
D03*
X8428D02*
X8228D02*
D03*
X8682D02*
X8482D02*
D03*
X8936D02*
X8736D02*
D03*
X5126D02*
X4926D02*
D03*
X5380D02*
X5180D02*
D03*
X5634D02*
X5434D02*
D03*
X5888D02*
X5688D02*
D03*
X6142D02*
X5942D02*
D03*
X6396D02*
X6196D02*
D03*
X6650D02*
X6450D02*
D03*
X6904D02*
X6704D02*
D03*
X3094D02*
X2894D02*
D03*
X3348D02*
X3148D02*
D03*
X3602D02*
X3402D02*
D03*
X3856D02*
X3656D02*
D03*
X4110D02*
X3910D02*
D03*
X4364D02*
X4164D02*
D03*
X4618D02*
X4418D02*
D03*
X4872D02*
X4672D02*
D03*
X2840D02*
X2640D02*
D03*
X2586D02*
X2386D02*
D03*
X2332D02*
X2132D02*
D03*
X2078D02*
X1878D02*
D03*
X1824D02*
X1624D02*
D03*
X1570D02*
X1370D02*
D03*
X1316D02*
X1116D02*
D03*
X1062D02*
X862D02*
D03*
X7158Y277D02*
X6958Y277D02*
D03*
X7412D02*
X7212D02*
D03*
X7666D02*
X7466D02*
D03*
X7920D02*
X7720D02*
D03*
X8174D02*
X7974D02*
D03*
X8428D02*
X8228D02*
D03*
X8682D02*
X8482D02*
D03*
X8936D02*
X8736D02*
D03*
X5126D02*
X4926D02*
D03*
X5380D02*
X5180D02*
D03*
X5634D02*
X5434D02*
D03*
X5888D02*
X5688D02*
D03*
X6142D02*
X5942D02*
D03*
X6396D02*
X6196D02*
D03*
X6650D02*
X6450D02*
D03*
X6904D02*
X6704D02*
D03*
X3094D02*
X2894D02*
D03*
X3348D02*
X3148D02*
D03*
X3602D02*
X3402D02*
D03*
X3856D02*
X3656D02*
D03*
X4110D02*
X3910D02*
D03*
X4364D02*
X4164D02*
D03*
X4618D02*
X4418D02*
D03*
X4872D02*
X4672D02*
D03*
X2840D02*
X2640D02*
D03*
X2586D02*
X2386D02*
D03*
X2332D02*
X2132D02*
D03*
X2078D02*
X1878D02*
D03*
X1824D02*
X1624D02*
D03*
X1570D02*
X1370D02*
D03*
X1316D02*
X1116D02*
D03*
X1062D02*
X862D02*
D03*
Y1039D02*
D03*
X1316D02*
X1116D02*
D03*
X1570D02*
X1370D02*
D03*
X1824D02*
X1624D02*
D03*
X2078D02*
X1878D02*
D03*
X2332D02*
X2132D02*
D03*
X2586D02*
X2386D02*
D03*
X2840D02*
X2640D02*
D03*
X4872D02*
X4672D02*
D03*
X4618D02*
X4418D02*
D03*
X4364D02*
X4164D02*
D03*
X4110D02*
X3910D02*
D03*
X3856D02*
X3656D02*
D03*
X3602D02*
X3402D02*
D03*
X3348D02*
X3148D02*
D03*
X3094D02*
X2894D02*
D03*
X6904D02*
X6704D02*
D03*
X6650D02*
X6450D02*
D03*
X6396D02*
X6196D02*
D03*
X6142D02*
X5942D02*
D03*
X5888D02*
X5688D02*
D03*
X5634D02*
X5434D02*
D03*
X5380D02*
X5180D02*
D03*
X5126D02*
X4926D02*
D03*
X8936D02*
X8736D02*
D03*
X8682D02*
X8482D02*
D03*
X8428D02*
X8228D02*
D03*
X8174D02*
X7974D02*
D03*
X7920D02*
X7720D02*
D03*
X7666D02*
X7466D02*
D03*
X7412D02*
X7212D02*
D03*
X7158D02*
X6958D02*
D03*
X1062Y785D02*
X862Y785D02*
D03*
X1316D02*
X1116D02*
D03*
X1570D02*
X1370D02*
D03*
X1824D02*
X1624D02*
D03*
X2078D02*
X1878D02*
D03*
X2332D02*
X2132D02*
D03*
X2586D02*
X2386D02*
D03*
X2840D02*
X2640D02*
D03*
X4872D02*
X4672D02*
D03*
X4618D02*
X4418D02*
D03*
X4364D02*
X4164D02*
D03*
X4110D02*
X3910D02*
D03*
X3856D02*
X3656D02*
D03*
X3602D02*
X3402D02*
D03*
X3348D02*
X3148D02*
D03*
X3094D02*
X2894D02*
D03*
X6904D02*
X6704D02*
D03*
X6650D02*
X6450D02*
D03*
X6396D02*
X6196D02*
D03*
X6142D02*
X5942D02*
D03*
X5888D02*
X5688D02*
D03*
X5634D02*
X5434D02*
D03*
X5380D02*
X5180D02*
D03*
X5126D02*
X4926D02*
D03*
X8936D02*
X8736D02*
D03*
X8682D02*
X8482D02*
D03*
X8428D02*
X8228D02*
D03*
X8174D02*
X7974D02*
D03*
X7920D02*
X7720D02*
D03*
X7666D02*
X7466D02*
D03*
X7412D02*
X7212D02*
D03*
X7158D02*
X6958D02*
D03*
Y531D02*
D03*
X7412D02*
X7212D02*
D03*
X7666D02*
X7466D02*
D03*
X7920D02*
X7720D02*
D03*
X8174D02*
X7974D02*
D03*
X8428D02*
X8228D02*
D03*
X8682D02*
X8482D02*
D03*
X8936D02*
X8736D02*
D03*
X5126D02*
X4926D02*
D03*
X5380D02*
X5180D02*
D03*
X5634D02*
X5434D02*
D03*
X5888D02*
X5688D02*
D03*
X6142D02*
X5942D02*
D03*
X6396D02*
X6196D02*
D03*
X6650D02*
X6450D02*
D03*
X6904D02*
X6704D02*
D03*
X3094D02*
X2894D02*
D03*
X3348D02*
X3148D02*
D03*
X3602D02*
X3402D02*
D03*
X3856D02*
X3656D02*
D03*
X4110D02*
X3910D02*
D03*
X4364D02*
X4164D02*
D03*
X4618D02*
X4418D02*
D03*
X4872D02*
X4672D02*
D03*
X2840D02*
X2640D02*
D03*
X2586D02*
X2386D02*
D03*
X2332D02*
X2132D02*
D03*
X2078D02*
X1878D02*
D03*
X1824D02*
X1624D02*
D03*
X1570D02*
X1370D02*
D03*
X1316D02*
X1116D02*
D03*
X1062D02*
X862D02*
D03*
D26*
X6530Y1700D02*
X6330Y1700D02*
D03*
X7910D02*
X7710D02*
D03*
X3980D02*
X3780D02*
D03*
X2720D02*
X2520D02*
D03*
X8200Y2900D02*
X8000Y2900D02*
D03*
X6900D02*
X6700D02*
D03*
X5600D02*
X5400D02*
D03*
X4400D02*
X4200D02*
D03*
X3000D02*
X2800D02*
D03*
X1800Y2890D02*
X1600Y2890D02*
D03*
D27*
X9444Y277D02*
X9244Y277D02*
D03*
X554D02*
X354D02*
D03*
M02*
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.GM1 → pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.GM1
View file @ cdc38585
......@@ -24,11 +24,11 @@ G04 Layer_Color=16711935*
%ADD27C,5.30*%
%ADD28C,0.10*%
D28*
X-0Y0D02*
Y2000D01*
X0Y0D02*
Y1800D01*
Y4250D01*
X10000D01*
X-0Y0D02*
X10000D01*
X9600D01*
X0Y0D02*
X9600D01*
Y4250D01*
M02*
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.GTS → pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.GTS
View file @ cdc38585
......@@ -22,455 +22,455 @@ G04 Layer_Color=8388736*
%ADD25C,3.70*%
%ADD26C,1.20*%
D21*
X8200Y1985D02*
X8000Y1985D02*
D03*
Y2415D02*
D03*
X6900Y1985D02*
X6700Y1985D02*
D03*
Y2415D02*
D03*
X5600Y1985D02*
X5400Y1985D02*
D03*
Y2415D02*
D03*
X4400D02*
X4200D02*
D03*
Y1985D02*
D03*
X3000Y2415D02*
X2800Y2415D02*
D03*
Y1985D02*
D03*
X1800Y2415D02*
X1600Y2415D02*
D03*
Y1985D02*
D03*
D22*
X2300Y3055D02*
X2100Y3055D02*
D03*
Y3345D02*
D03*
X3500Y3055D02*
X3300Y3055D02*
D03*
Y3345D02*
D03*
X4900Y3055D02*
X4700Y3055D02*
D03*
Y3345D02*
D03*
X6100D02*
X5900D02*
D03*
Y3055D02*
D03*
X7400Y3345D02*
X7200Y3345D02*
D03*
Y3055D02*
D03*
X8700Y3345D02*
X8500Y3345D02*
D03*
Y3055D02*
D03*
X2300Y2455D02*
X2100Y2455D02*
D03*
Y2745D02*
D03*
X3500Y2455D02*
X3300Y2455D02*
D03*
Y2745D02*
D03*
X4900Y2455D02*
X4700Y2455D02*
D03*
Y2745D02*
D03*
X6100D02*
X5900D02*
D03*
Y2455D02*
D03*
X7400Y2745D02*
X7200Y2745D02*
D03*
Y2455D02*
D03*
X8700Y2745D02*
X8500Y2745D02*
D03*
Y2455D02*
D03*
X2300Y1855D02*
X2100Y1855D02*
D03*
Y2145D02*
D03*
X3500Y1855D02*
X3300Y1855D02*
D03*
Y2145D02*
D03*
X4900Y1855D02*
X4700Y1855D02*
D03*
Y2145D02*
D03*
X6100D02*
X5900D02*
D03*
Y1855D02*
D03*
X7400Y2145D02*
X7200Y2145D02*
D03*
Y1855D02*
D03*
X8700Y2145D02*
X8500Y2145D02*
D03*
Y1855D02*
D03*
D23*
X5000Y4000D02*
X4800Y3900D02*
D03*
X9700D02*
X9300D02*
D03*
X300D02*
D03*
D24*
X7158Y1293D02*
X6958Y1293D02*
D03*
X7412D02*
X7212D02*
D03*
X7666D02*
X7466D02*
D03*
X7920D02*
X7720D02*
D03*
X8174D02*
X7974D02*
D03*
X8428D02*
X8228D02*
D03*
X8682D02*
X8482D02*
D03*
X8936D02*
X8736D02*
D03*
X5126D02*
X4926D02*
D03*
X5380D02*
X5180D02*
D03*
X5634D02*
X5434D02*
D03*
X5888D02*
X5688D02*
D03*
X6142D02*
X5942D02*
D03*
X6396D02*
X6196D02*
D03*
X6650D02*
X6450D02*
D03*
X6904D02*
X6704D02*
D03*
X3094D02*
X2894D02*
D03*
X3348D02*
X3148D02*
D03*
X3602D02*
X3402D02*
D03*
X3856D02*
X3656D02*
D03*
X4110D02*
X3910D02*
D03*
X4364D02*
X4164D02*
D03*
X4618D02*
X4418D02*
D03*
X4872D02*
X4672D02*
D03*
X2840D02*
X2640D02*
D03*
X2586D02*
X2386D02*
D03*
X2332D02*
X2132D02*
D03*
X2078D02*
X1878D02*
D03*
X1824D02*
X1624D02*
D03*
X1570D02*
X1370D02*
D03*
X1316D02*
X1116D02*
D03*
X1062D02*
X862D02*
D03*
X7158Y277D02*
X6958Y277D02*
D03*
X7412D02*
X7212D02*
D03*
X7666D02*
X7466D02*
D03*
X7920D02*
X7720D02*
D03*
X8174D02*
X7974D02*
D03*
X8428D02*
X8228D02*
D03*
X8682D02*
X8482D02*
D03*
X8936D02*
X8736D02*
D03*
X5126D02*
X4926D02*
D03*
X5380D02*
X5180D02*
D03*
X5634D02*
X5434D02*
D03*
X5888D02*
X5688D02*
D03*
X6142D02*
X5942D02*
D03*
X6396D02*
X6196D02*
D03*
X6650D02*
X6450D02*
D03*
X6904D02*
X6704D02*
D03*
X3094D02*
X2894D02*
D03*
X3348D02*
X3148D02*
D03*
X3602D02*
X3402D02*
D03*
X3856D02*
X3656D02*
D03*
X4110D02*
X3910D02*
D03*
X4364D02*
X4164D02*
D03*
X4618D02*
X4418D02*
D03*
X4872D02*
X4672D02*
D03*
X2840D02*
X2640D02*
D03*
X2586D02*
X2386D02*
D03*
X2332D02*
X2132D02*
D03*
X2078D02*
X1878D02*
D03*
X1824D02*
X1624D02*
D03*
X1570D02*
X1370D02*
D03*
X1316D02*
X1116D02*
D03*
X1062D02*
X862D02*
D03*
Y1039D02*
D03*
X1316D02*
X1116D02*
D03*
X1570D02*
X1370D02*
D03*
X1824D02*
X1624D02*
D03*
X2078D02*
X1878D02*
D03*
X2332D02*
X2132D02*
D03*
X2586D02*
X2386D02*
D03*
X2840D02*
X2640D02*
D03*
X4872D02*
X4672D02*
D03*
X4618D02*
X4418D02*
D03*
X4364D02*
X4164D02*
D03*
X4110D02*
X3910D02*
D03*
X3856D02*
X3656D02*
D03*
X3602D02*
X3402D02*
D03*
X3348D02*
X3148D02*
D03*
X3094D02*
X2894D02*
D03*
X6904D02*
X6704D02*
D03*
X6650D02*
X6450D02*
D03*
X6396D02*
X6196D02*
D03*
X6142D02*
X5942D02*
D03*
X5888D02*
X5688D02*
D03*
X5634D02*
X5434D02*
D03*
X5380D02*
X5180D02*
D03*
X5126D02*
X4926D02*
D03*
X8936D02*
X8736D02*
D03*
X8682D02*
X8482D02*
D03*
X8428D02*
X8228D02*
D03*
X8174D02*
X7974D02*
D03*
X7920D02*
X7720D02*
D03*
X7666D02*
X7466D02*
D03*
X7412D02*
X7212D02*
D03*
X7158D02*
X6958D02*
D03*
X1062Y785D02*
X862Y785D02*
D03*
X1316D02*
X1116D02*
D03*
X1570D02*
X1370D02*
D03*
X1824D02*
X1624D02*
D03*
X2078D02*
X1878D02*
D03*
X2332D02*
X2132D02*
D03*
X2586D02*
X2386D02*
D03*
X2840D02*
X2640D02*
D03*
X4872D02*
X4672D02*
D03*
X4618D02*
X4418D02*
D03*
X4364D02*
X4164D02*
D03*
X4110D02*
X3910D02*
D03*
X3856D02*
X3656D02*
D03*
X3602D02*
X3402D02*
D03*
X3348D02*
X3148D02*
D03*
X3094D02*
X2894D02*
D03*
X6904D02*
X6704D02*
D03*
X6650D02*
X6450D02*
D03*
X6396D02*
X6196D02*
D03*
X6142D02*
X5942D02*
D03*
X5888D02*
X5688D02*
D03*
X5634D02*
X5434D02*
D03*
X5380D02*
X5180D02*
D03*
X5126D02*
X4926D02*
D03*
X8936D02*
X8736D02*
D03*
X8682D02*
X8482D02*
D03*
X8428D02*
X8228D02*
D03*
X8174D02*
X7974D02*
D03*
X7920D02*
X7720D02*
D03*
X7666D02*
X7466D02*
D03*
X7412D02*
X7212D02*
D03*
X7158D02*
X6958D02*
D03*
Y531D02*
D03*
X7412D02*
X7212D02*
D03*
X7666D02*
X7466D02*
D03*
X7920D02*
X7720D02*
D03*
X8174D02*
X7974D02*
D03*
X8428D02*
X8228D02*
D03*
X8682D02*
X8482D02*
D03*
X8936D02*
X8736D02*
D03*
X5126D02*
X4926D02*
D03*
X5380D02*
X5180D02*
D03*
X5634D02*
X5434D02*
D03*
X5888D02*
X5688D02*
D03*
X6142D02*
X5942D02*
D03*
X6396D02*
X6196D02*
D03*
X6650D02*
X6450D02*
D03*
X6904D02*
X6704D02*
D03*
X3094D02*
X2894D02*
D03*
X3348D02*
X3148D02*
D03*
X3602D02*
X3402D02*
D03*
X3856D02*
X3656D02*
D03*
X4110D02*
X3910D02*
D03*
X4364D02*
X4164D02*
D03*
X4618D02*
X4418D02*
D03*
X4872D02*
X4672D02*
D03*
X2840D02*
X2640D02*
D03*
X2586D02*
X2386D02*
D03*
X2332D02*
X2132D02*
D03*
X2078D02*
X1878D02*
D03*
X1824D02*
X1624D02*
D03*
X1570D02*
X1370D02*
D03*
X1316D02*
X1116D02*
D03*
X1062D02*
X862D02*
D03*
D25*
X9444Y277D02*
X9244Y277D02*
D03*
X554D02*
X354D02*
D03*
D26*
X6530Y1700D02*
X6330Y1700D02*
D03*
X7910D02*
X7710D02*
D03*
X3980D02*
X3780D02*
D03*
X2720D02*
X2520D02*
D03*
X8200Y2900D02*
X8000Y2900D02*
D03*
X6900D02*
X6700D02*
D03*
X5600D02*
X5400D02*
D03*
X4400D02*
X4200D02*
D03*
X3000D02*
X2800D02*
D03*
X1800Y2890D02*
X1600Y2890D02*
D03*
M02*
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.LDP → pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.LDP
View file @ cdc38585
Layer Pairs Export File for PCB: \\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\PTS_P2_Board.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=pts_p2_board.txt|LayerPairs=gtl,gbl
Layer Pairs Export File for PCB: \\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=rtm_interface_tester.txt|LayerPairs=gtl,gbl
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.REP → pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.REP
View file @ cdc38585
*************************************************************
FileName = PTS_P2_Board.GBR
FileName = RTM_Interface_Tester.GBR
AutoAperture = True
*************************************************************
Generating : Top Layer
File : PTS_P2_Board.GTL
File : RTM_Interface_Tester.GTL
Adding Layer : Top Layer
......@@ -23,7 +23,7 @@ Used DCodes :
*************************************************************
Generating : Bottom Layer
File : PTS_P2_Board.GBL
File : RTM_Interface_Tester.GBL
Adding Layer : Bottom Layer
......@@ -41,7 +41,7 @@ Used DCodes :
*************************************************************
Generating : Top Overlay
File : PTS_P2_Board.GTO
File : RTM_Interface_Tester.GTO
Adding Layer : Top Overlay
......@@ -54,7 +54,7 @@ Used DCodes :
*************************************************************
Generating : Top Solder
File : PTS_P2_Board.GTS
File : RTM_Interface_Tester.GTS
Adding Layer : Top Solder
......@@ -74,7 +74,7 @@ Used DCodes :
*************************************************************
Generating : Bottom Solder
File : PTS_P2_Board.GBS
File : RTM_Interface_Tester.GBS
Adding Layer : Bottom Solder
......@@ -92,7 +92,7 @@ Used DCodes :
*************************************************************
Generating : Mechanical 1
File : PTS_P2_Board.GM1
File : RTM_Interface_Tester.GM1
Adding Layer : Mechanical 1
......@@ -103,7 +103,7 @@ Used DCodes :
*************************************************************
Generating : Mechanical 7
File : PTS_P2_Board.GM7
File : RTM_Interface_Tester.GM7
Adding Layer : Mechanical 7
......
pcb/PTS_P2_Board/Project Outputs for PTS_P2_Board/PTS_P2_Board.RUL → pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.RUL
View file @ cdc38585
DRC Rules Export File for PCB: \\cern.ch\dfs\Users\t\tstana\Desktop\PTS_P2_Board\PTS_P2_Board.PcbDoc
DRC Rules Export File for PCB: \\cern.ch\dfs\Users\t\tstana\Desktop\RTM_Interface_Tester\RTM_Interface_Tester.PcbDoc
RuleKind=Width|RuleName=Width_GND|Scope=Board|Minimum=10.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
......
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/RTM_Interface_Tester.TXT 0 → 100644
View file @ cdc38585
M48
;Layer_Color=9474304
;FILE_FORMAT=4:2
METRIC,LZ
;TYPE=PLATED
T1F00S00C0.50
T2F00S00C1.00
T3F00S00C2.80
T4F00S00C3.00
%
T01
X0016Y00289
X0028Y0029
X0042
X0054
X00378Y0017
X00252
X00633
X00771
X008Y0029
X0067
T02
X005688Y000277
X005942
X006196
X00645
X006704
X006958
X007212
X007466
X00772
X007974
X008228
X008482
X008736
X005434
X00518
X004926
X004672
X004418
X004164
X00391
X003656
X003402
X003148
X002894
X00264
X002386
X002132
X001878
X001624
X00137
X001116
X000862
Y000531
Y000785
Y001039
Y001293
X001116
X00137
X001624
Y001039
X00137
X001116
Y000785
X00137
X001624
Y000531
X00137
X001116
X001878
Y000785
Y001039
Y001293
X002132
X002386
Y001039
X002132
Y000785
X002386
Y000531
X002132
X00264
Y000785
Y001039
Y001293
X002894
X003148
X003402
X003656
Y001039
X003402
X003148
X002894
Y000785
X003148
X003402
X003656
Y000531
X003402
X003148
X002894
X00391
Y000785
Y001039
Y001293
X004164
X004418
X004672
X004926
X00518
X005434
Y001039
X00518
X004926
X004672
X004418
X004164
Y000785
X004418
X004672
X004926
X00518
X005434
Y000531
X00518
X004926
X004672
X004418
X004164
X005688
X005942
Y000785
X005688
Y001039
X005942
Y001293
X005688
X006196
X00645
X006704
X006958
X007212
X007466
X00772
X007974
X008228
Y001039
X007974
X00772
X007466
X007212
X006958
X006704
X00645
X006196
Y000785
X00645
X006704
X006958
X007212
X007466
X00772
X007974
X008228
Y000531
X007974
X00772
X007466
X007212
X006958
X006704
X00645
X006196
X008482
Y000785
Y001039
Y001293
X008736
Y001039
Y000785
Y000531
T03
X009244Y000277
X000354
T04
X0003Y0039
X0048
X0093
M30
pcb/RTM_Interface_Tester/Project Outputs for RTM_Interface_Tester/Status Report.Txt 0 → 100644
View file @ cdc38585
Output: NC Drill Files
Type : NC Drill
From : Project [RTM_Interface_Tester.PrjPCB]
Generated File[RTM_Interface_Tester.TXT]
Generated File[RTM_Interface_Tester.DRL]
Generated File[RTM_Interface_Tester.LDP]
Generated File[RTM_Interface_Tester.DRR]
Files Generated : 4
Documents Printed : 0
Finished Output Generation At 12:53:44 PM On 5/14/2013
pcb/PTS_P2_Board/PTS_P2_Board.PrjPCB → pcb/RTM_Interface_Tester/RTM_Interface_Tester.PrjPCB
View file @ cdc38585
......@@ -2,7 +2,7 @@
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=Project Outputs for PTS_P2_Board
OutputPath=Project Outputs for RTM_Interface_Tester
LogFolderPath=
ReleasesFolder=
ReleaseVaultGUID=
......@@ -31,7 +31,7 @@ PushECOToAnnotationFile=1
DItemRevisionGUID=
[Document1]
DocumentPath=PTS_P2_Board.PcbDoc
DocumentPath=RTM_Interface_Tester.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
......@@ -47,23 +47,7 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document2]
DocumentPath=PTS_P2_Board.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
[Document3]
DocumentPath=PTS_P2_Board.OutJob
DocumentPath=RTM_Interface_Tester.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
......@@ -79,63 +63,63 @@ DItemRevisionGUID=
GenerateClassCluster=0
[GeneratedDocument1]
DocumentPath=Project Outputs for PTS_P2_Board\Design Rule Check - PTS_P2_Board.html
DocumentPath=Project Outputs for RTM_Interface_Tester\Design Rule Check - RTM_Interface_Tester.html
DItemRevisionGUID=
[GeneratedDocument2]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.DRL
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.DRL
DItemRevisionGUID=
[GeneratedDocument3]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.DRR
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.DRR
DItemRevisionGUID=
[GeneratedDocument4]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.EXTREP
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.EXTREP
DItemRevisionGUID=
[GeneratedDocument5]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GBL
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.GBL
DItemRevisionGUID=
[GeneratedDocument6]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GBS
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.GBS
DItemRevisionGUID=
[GeneratedDocument7]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GM1
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.GM1
DItemRevisionGUID=
[GeneratedDocument8]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GM7
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.GM7
DItemRevisionGUID=
[GeneratedDocument9]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GTL
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.GTL
DItemRevisionGUID=
[GeneratedDocument10]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GTO
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.GTO
DItemRevisionGUID=
[GeneratedDocument11]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.GTS
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.GTS
DItemRevisionGUID=
[GeneratedDocument12]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.LDP
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.LDP
DItemRevisionGUID=
[GeneratedDocument13]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.REP
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.REP
DItemRevisionGUID=
[GeneratedDocument14]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.RUL
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.RUL
DItemRevisionGUID=
[GeneratedDocument15]
DocumentPath=Project Outputs for PTS_P2_Board\PTS_P2_Board.TXT
DocumentPath=Project Outputs for RTM_Interface_Tester\RTM_Interface_Tester.TXT
DItemRevisionGUID=
[PCBConfiguration1]
......
pcb/RTM_Interface_Tester/RTM_Interface_Tester.PrjPCBStructure 0 → 100644
View file @ cdc38585
Record=TopLevelDocument|FileName=RTM_Interface_Tester.SchDoc
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