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Conv TTL Blocking
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Conv TTL Blocking
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81f89746
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81f89746
authored
Nov 05, 2013
by
Javier Serrano
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design-review/javier.txt
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81f89746
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@@ -69,6 +69,17 @@ Page 9. Reader is left wondering why configuration register reads is
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@@ -69,6 +69,17 @@ Page 9. Reader is left wondering why configuration register reads is
limited to 16 bits. Only later in the document it is proposed as a
limited to 16 bits. Only later in the document it is proposed as a
possible design evolution. Is it so hard? Or is it just useless?
possible design evolution. Is it so hard? Or is it just useless?
conv_ttl_blo.vhd
================
Line 656: fpga_input_ttl_n_i(i) are asynchronous inputs. You need to
pass them through proper synchronizers before using them in
combinational logic whose outputs are clocked by the clk125 clock
signal. In particular, consider the fact that the signal is going to
the enable inputs of the counter flip-flops. What happens if in a
given clock cycle some FFs see the signal as '1' and others as '0'?
Todo
Todo
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