Skip to content

C
Conv TTL Blocking
Commit 84b39781 authored by gilsoriano's avatar gilsoriano
Browse files
Options

spi_master_core: s_STATUS.spi_fsm_clk modified to properly generate the flag for… 

spi_master_core: s_STATUS.spi_fsm_clk modified to properly generate the flag for reading the miso buffer.
parent 9d60a8a1
Hide whitespace changes
Inline Side-by-side
Showing with 49 additions and 32 deletions
hdl/m25p32/project/waveform/wave.do
View file @ 84b39781
......@@ -42,7 +42,7 @@ add wave -noupdate -expand -group spi_master_multifield /m25p32_top_tb/uut/inst_
add wave -noupdate -expand -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI0_core
add wave -noupdate -expand -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI1_core
add wave -noupdate -expand -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI2
add wave -noupdate -expand -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/s_SPI3_slv
add wave -noupdate -expand -group spi_master_multifield -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_SPI3_slv
add wave -noupdate -expand -group spi_master_multifield /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/rd_SPI3_o
add wave -noupdate -expand -group spi_master_multifield -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/reg_i
add wave -noupdate -expand -group spi_master_multifield -group inst_FIFO /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_fifo_i2c/clk
......@@ -69,7 +69,7 @@ add wave -noupdate -group miso_tester /m25p32_top_tb/miso_tester/spi_miso_o
add wave -noupdate -group miso_tester /m25p32_top_tb/miso_tester/spi_clk_i
add wave -noupdate -group miso_tester /m25p32_top_tb/miso_tester/s_spi_count
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {904331015 ps} 0}
WaveRestoreCursors {{Cursor 1} {907425000 ps} 0}
configure wave -namecolwidth 274
configure wave -valuecolwidth 88
configure wave -justifyvalue left
......@@ -84,4 +84,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {889270409 ps} {925781779 ps}
WaveRestoreZoom {906349380 ps} {909585368 ps}
hdl/m25p32/test/m25p32_top_tb.vhd
View file @ 84b39781
......@@ -104,6 +104,7 @@ architecture Behavioral of m25p32_top_tb is
signal s_spi_addr : STD_LOGIC_VECTOR(c_M25P32_ADDR_SIZE*8 - 1
downto 0);
signal test_id : NATURAL := 0;
signal s_miso_word_rcv : STD_LOGIC;
begin
s_SPI0 <= f_SPI0(s_SPI0_slv);
......@@ -145,6 +146,7 @@ begin
wb_rty_o => s_wb_rty,
wb_err_o => s_wb_err,
miso_word_rcv => s_miso_word_rcv,
op_finished_o => s_op_finished,
prom_mosi_o => s_spi_mosi,
......@@ -603,7 +605,7 @@ begin
-- We check operation
wait until rising_edge(s_end_inst_flag);
check_inst(test_id, operation);
if (operation = READ)
if (operation = READ)
or (operation = PP)
or (operation = SE) then
wait until rising_edge(s_end_addr_flag);
......@@ -615,6 +617,10 @@ begin
wait until rising_edge(s_end_data_flag);
check_data(test_id, operation);
end if;
--TODO 2/10/2012 work on RDSR check
if (operation = RDSR) then
wait until rising_edge(s_miso_word_rcv);
end if;
-- We check WRDI
wait until rising_edge(s_end_inst_flag);
check_inst(test_id, operation);
......
hdl/spi_master_multifield/rtl/spi_master_core.vhd
View file @ 84b39781
......@@ -148,6 +148,9 @@ signal s_read_edge_counter_manual_rst_clk : STD_LOGIC;
signal s_read_edge_counter_rst_i : STD_LOGIC;
signal s_read_edge_counter_cnt : STD_LOGIC_VECTOR(c_COUNTER_DATA_WIDTH
- 1 downto 0);
signal s_read_edge_counter_cnt_d0 : STD_LOGIC_VECTOR(c_COUNTER_DATA_WIDTH
- 1 downto 0);
signal s_spi_cs_n : STD_LOGIC;
signal s_spi_clk_manual_rst_i : STD_LOGIC;
......@@ -164,6 +167,7 @@ signal s_spi_clk_n_d0 : STD_LOGIC;
--! Watch out here, 9 is the length of those fields
signal s_spi_miso_data : STD_LOGIC_VECTOR(31 downto 0);
signal s_rd_SPI3 : STD_LOGIC;
begin
......@@ -177,6 +181,8 @@ begin
spi_cs_n_o <= s_spi_cs_n;
-- s_spi_mosi <= s_mosi
rd_SPI3_o <= s_rd_SPI3;
inst_fifo_i2c: FIFO_dispatcher
generic map(
g_data_width => 8, g_dispatcher_depth => c_INST_LENGTH)
......@@ -314,11 +320,13 @@ begin
s_spi_clk_fsm_d0 <= S0_IDLE;
s_SPI1_core_d0 <= c_SPI1_default;
s_SPI2_d0 <= c_SPI2_default;
s_read_edge_counter_cnt_d0 <= (others => '0');
else
s_clk_fsm_d0 <= s_STATUS.clk_fsm;
s_spi_clk_fsm_d0 <= s_STATUS.spi_clk_fsm;
s_SPI1_core_d0 <= s_SPI1_core;
s_SPI2_d0 <= s_SPI2;
s_read_edge_counter_cnt_d0 <= s_read_edge_counter_cnt;
end if;
end if;
end process p_fsm_delays;
......@@ -793,37 +801,33 @@ begin
-----------------------------------------------------------
--! SPI miso input reads
-----------------------------------------------------------
p_miso :process(s_read_edge_counter_clk)
p_miso :process(s_STATUS.clk_fsm, s_read_edge_counter_clk)
begin
if rising_edge(s_read_edge_counter_clk) then
if s_STATUS.clk_fsm = R0_RESET then
s_spi_miso_data <= (others => '0');
if s_STATUS.clk_fsm = R0_RESET then
s_spi_miso_data <= (others => '0');
else
if rising_edge(s_read_edge_counter_clk) then
else
s_spi_miso_data <= (others => '0');
if s_spi_clk_fsm_d0 = S5_READ then
s_spi_miso_data <= s_spi_miso_data(30 downto 0)
& spi_miso_i;
& spi_miso_i;
end if;
end if;
end if;
end process p_miso;
p_rd_miso : process(clk_i)
-----------------------------------------------------------
--! fsm to determine access to SPI lines
-----------------------------------------------------------
p_comb_rd_miso : process(s_STATUS.clk_fsm, s_STATUS.spi_clk_fsm)
begin
if rising_edge(clk_i) then
if s_STATUS.clk_fsm = R0_RESET then
s_rd_SPI3 <= '0';
else
s_rd_SPI3 <= '0';
--!TODO: change to one-clock signaling!
if ((UNSIGNED(s_read_edge_counter_cnt) mod r_SPI3'a_length) = 0)
or s_SPI2.SENT_OP = '1' then
if s_rd_SPI3 = '0' then
s_rd_SPI3 <= '1';
end if;
end if;
if s_STATUS.clk_fsm = R0_RESET then
s_rd_SPI3 <= '0';
else
s_rd_SPI3 <= '0';
if s_STATUS.spi_clk_fsm = S5U_READ then
s_rd_SPI3 <= '1';
end if;
end if;
end process p_rd_miso;
......@@ -889,7 +893,7 @@ begin
next_fsm_state1 : SPI_spi_clk_fsm;
clk : STD_LOGIC; clk_d0 : STD_LOGIC) is
begin
if (f_read_edge(s_SPI0, clk, clk_d0) = '1')
if (f_read_edge(s_SPI0_core, clk, clk_d0) = '1')
and (s_read_edge_counter_cnt(2 downto 0) = "111") then
if to_integer(UNSIGNED(s_read_edge_counter_cnt))
< to_integer(max_value) * 8 - 1 then
......@@ -904,12 +908,12 @@ begin
next_fsm_state0 : SPI_spi_clk_fsm;
next_fsm_state1 : SPI_spi_clk_fsm) is
begin
if s_SPI0.CPOL = '0' then
updater(max_value, next_fsm_state0, next_fsm_state1,
s_spi_clk, s_spi_clk_d0);
if s_SPI0_core.CPOL = '0' then
updater(max_value, next_fsm_state0, next_fsm_state1,
s_spi_clk, s_spi_clk_d0);
else
updater(max_value, next_fsm_state0, next_fsm_state1,
s_spi_clk_n, s_spi_clk_n_d0);
updater(max_value, next_fsm_state0, next_fsm_state1,
s_spi_clk_n, s_spi_clk_n_d0);
end if;
end procedure;
......@@ -947,9 +951,16 @@ begin
update_fsm(s_SPI0_core.BDATA, S4P_DATA, S6_STOP_SPI_CLK);
end if;
when S5_READ =>
update_fsm("000000" & s_SPI0.BREAD, S5U_READ, S6_STOP_SPI_CLK);
--! We force always to go into S5U_READ to produce a flag for
--! fetching the received data
update_fsm("000000" & s_SPI0_core.BREAD, S5U_READ, S5U_READ);
when S5U_READ =>
s_STATUS.spi_clk_fsm <= S5_READ;
if to_integer(UNSIGNED(s_read_edge_counter_cnt))
< to_integer(s_SPI0_core.BREAD) * 8 - 1 then
s_STATUS.spi_clk_fsm <= S5_READ;
else
s_STATUS.spi_clk_fsm <= S6_STOP_SPI_CLK;
end if;
when others =>
end case;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment