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998c7a75
Commit
998c7a75
authored
Jul 24, 2012
by
gilsoriano
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SPI big cleanup and debug. Now every SPI mode works correctly.
parent
44b0a8e9
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5 changed files
with
265 additions
and
268 deletions
+265
-268
gc_clk_divider.vhd
hdl/ctdah_lib/rtl/gc_clk_divider.vhd
+3
-3
spiSpecs.pdf
hdl/spi_master_multifield/doc/spiSpecs.pdf
+0
-0
spiSpecs.tex
hdl/spi_master_multifield/doc/spiSpecs.tex
+5
-1
spi_master_core.vhd
hdl/spi_master_multifield/rtl/spi_master_core.vhd
+248
-230
spi_master_core_tb.vhd
hdl/spi_master_multifield/test/spi_master_core_tb.vhd
+9
-34
No files found.
hdl/ctdah_lib/rtl/gc_clk_divider.vhd
View file @
998c7a75
...
...
@@ -68,8 +68,8 @@ begin
if
rising_edge
(
clk_i
)
then
if
rst_i
=
'1'
then
s_clk_o
<=
'0'
;
clk_i_count
<=
unsigned
(
divider_i
);
--
clk_i_count <= to_unsigned(1, g_clk_division_logSize);
--
clk_i_count <= unsigned(divider_i);
clk_i_count
<=
to_unsigned
(
1
,
g_clk_division_logSize
);
else
if
oe_n_i
=
'0'
then
clk_i_count
<=
clk_i_count
+
1
;
...
...
@@ -79,7 +79,7 @@ begin
else
end
if
;
else
--
s_clk_o <= '0';
s_clk_o
<=
'0'
;
end
if
;
end
if
;
else
...
...
hdl/spi_master_multifield/doc/spiSpecs.pdf
View file @
998c7a75
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hdl/spi_master_multifield/doc/spiSpecs.tex
View file @
998c7a75
...
...
@@ -101,7 +101,11 @@ The SPI0 is a write-read register.\\
\textbf
{
Bits
}
&
\textbf
{
Field
}
&
\textbf
{
Meaning
}
&
\textbf
{
Default
}
\\
\hline
\hline
4-0
&
x
&
Reserved
&
\textbf
{
"00000"
}
\\
0
&
\textbf
{
CPOL
}
&
Clock POLarity when idle
&
\textbf
{
"00000"
}
\\
\hline
1
&
\textbf
{
CPHA
}
&
Clock PHAse
&
\textbf
{
"00000"
}
\\
\hline
4-2
&
x
&
Reserved
&
\textbf
{
"00000"
}
\\
\hline
13-5
&
\textbf
{
BDATA
}
&
Bytes of DATA to be sent
&
\textbf
{
c
\_
INST
\_
LENGTH
}
\\
\hline
...
...
hdl/spi_master_multifield/rtl/spi_master_core.vhd
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998c7a75
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hdl/spi_master_multifield/test/spi_master_core_tb.vhd
View file @
998c7a75
...
...
@@ -77,10 +77,7 @@ architecture behavior of spi_master_core_tb is
signal
s_SPI2
:
r_SPI2
;
signal
spi_miso_i
:
STD_LOGIC
:
=
'0'
;
signal
s_cpol
:
STD_LOGIC
;
signal
s_cpha
:
STD_LOGIC
;
--Outputs
--Outputs
signal
spi_mosi_o
:
STD_LOGIC
;
signal
spi_clk_o
:
STD_LOGIC
;
signal
spi_cs_n_o
:
STD_LOGIC
;
...
...
@@ -389,6 +386,12 @@ begin
inst_i
,
addr_i
,
data_i
);
wait
for
c_WISHBONE_PERIOD
*
10
;
spi_command
(
'0'
,
'1'
,
1
,
1
,
1
,
'1'
,
'1'
,
'1'
,
inst_i
,
addr_i
,
data_i
);
wait
for
c_WISHBONE_PERIOD
*
10
;
spi_command
(
'1'
,
'0'
,
1
,
1
,
1
,
'1'
,
'1'
,
'1'
,
...
...
@@ -401,40 +404,12 @@ begin
inst_i
,
addr_i
,
data_i
);
wait
for
c_WISHBONE_PERIOD
*
10
;
spi_command
(
'0'
,
'
1
'
,
1
,
1
,
1
,
spi_command
(
'0'
,
'
0
'
,
1
,
3
,
256
,
'1'
,
'1'
,
'1'
,
inst_i
,
addr_i
,
data_i
);
wait
for
c_WISHBONE_PERIOD
*
10
;
-- cpol <= '1';
-- cpha <= '0';
-- set_SPI_mode (cpol, cpha);
--
-- spi_command( 1, 1, 1,
-- '1', '1', '1',
-- inst_i, addr_i, data_i);
-- wait for c_WISHBONE_PERIOD*10;
-- spi_command( 1, 3, 256,
-- '1', '1', '1',
-- inst_i, addr_i, data_i);
-- wait for c_WISHBONE_PERIOD*10;
--
-- spi_command( 1, 0, 0,
-- '1', '0', '0',
-- inst_i, addr_i, data_i);
-- wait for c_WISHBONE_PERIOD*10;
--
-- spi_command( 1, 3, 1,
-- '0', '1', '0',
-- inst_i, addr_i, data_i);
-- wait for c_WISHBONE_PERIOD*10;
--
-- spi_command( 1, 1, 2,
-- '0', '0', '1',
-- inst_i, addr_i, data_i);
-- wait for c_WISHBONE_PERIOD*10;
wait
;
end
process
;
...
...
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