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Commit a81703d3 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Big cleanup of the repo. All hdl subfolders have a .gitignore file

parent ef23e750
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hdl/.gitattributes 0 → 100644
View file @ a81703d3
#Ignore generated LaTeX files
*.aux
*.lof
*.log
*.lot
*.out
*.toc
hdl/IMAGES/image1/project/image1.gise
View file @ a81703d3
......@@ -85,17 +85,12 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="image1_top.lso"/>
<outfile xil_pn:name="image1_top.ngc"/>
<outfile xil_pn:name="image1_top.ngr"/>
<outfile xil_pn:name="image1_top.prj"/>
<outfile xil_pn:name="image1_top.stx"/>
<outfile xil_pn:name="image1_top.syr"/>
<outfile xil_pn:name="image1_top.xst"/>
<outfile xil_pn:name="image1_top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1354033300" xil_pn:in_ck="-7461616560160808584" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1354033300">
<status xil_pn:value="SuccessfullyRun"/>
......@@ -103,8 +98,9 @@
</transform>
<transform xil_pn:end_ts="1354033381" xil_pn:in_ck="4649869214785825988" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1354033375">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
......
hdl/IMAGES/image1/project/image1.xise
View file @ a81703d3
......@@ -134,18 +134,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
......@@ -154,6 +146,16 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../test/image1_top_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../test/image1_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="65"/>
</file>
</files>
<properties>
......@@ -393,8 +395,8 @@
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.image1_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/xwb_sdb_crossbar" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.xwb_sdb_crossbar" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/rtl/image1_pkg.vhd
View file @ a81703d3
......@@ -13,7 +13,7 @@ use work.rtm_detector_pkg.ALL;
package image1_pkg is
constant c_WB_CLK_PERIOD : TIME := 8 ns;
constant c_WB_CLK_PERIOD : TIME := 50 ns;
constant c_RST_CLKS : NATURAL := 256; --! @8ns
constant c_NUM_MASTERS : NATURAL := 1;
......
hdl/IMAGES/image1/rtl/image1_top.vhd
View file @ a81703d3
......@@ -11,29 +11,27 @@ use UNISIM.VCOMPONENTS.ALL;
entity image1_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (
FPGA_CLK_P : in STD_LOGIC;
FPGA_CLK_N : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
clk_i : in STD_LOGIC; --Using the 20MHz clock
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
......@@ -41,22 +39,22 @@ entity image1_top is
FPGA_PROM_MOSI : out STD_LOGIC;
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
led_link_up_o : out STD_LOGIC;
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP : in STD_LOGIC_VECTOR(2 downto 0));
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP : in STD_LOGIC_VECTOR(2 downto 0));
end image1_top;
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ a81703d3
This diff is collapsed.
hdl/IMAGES/image1/test/image1_top_tb.vhd_OLD deleted 100644 → 0
View file @ ef23e750
This diff is collapsed.
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd 0 → 100644
View file @ a81703d3
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--! Packages from IP cores
--use work.wishbone_pkg.ALL;
--use work.i2c_slave_pkg.ALL;
--use work.m25p32_pkg.ALL;
--use work.multiboot_pkg.ALL;
--use work.rtm_detector_pkg.ALL;
package image1_top_pkg is
constant c_NUMBER_OF_CHANNELS : NATURAL := 6;
component image1_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (FPGA_CLK_P : in STD_LOGIC;
FPGA_CLK_N : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
led_ttl_o : out STD_LOGIC;
led_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
led_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_front : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_front : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_i_rear : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
pulse_o_rear : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
inv_i : in STD_LOGIC_VECTOR(4 downto 1);
inv_o : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_OE : out STD_LOGIC;
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_OE : out STD_LOGIC;
FPGA_GA : in STD_LOGIC_VECTOR(4 downto 0);
FPGA_GAP : in STD_LOGIC;
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK : out STD_LOGIC;
FPGA_PROM_CSO_B_N : out STD_LOGIC;
FPGA_PROM_DIN : in STD_LOGIC;
FPGA_PROM_MOSI : out STD_LOGIC;
--! This LED will show the status of the PLL
led_link_up_o : out STD_LOGIC;
led_pps_o : out STD_LOGIC;
led_wr_ok_o : out STD_LOGIC;
fpga_o_en : out STD_LOGIC;
fpga_o_blo_en : out STD_LOGIC;
fpga_o_ttl_en : out STD_LOGIC;
fpga_o_inv_en : out STD_LOGIC;
level : in STD_LOGIC;
switch_i : in STD_LOGIC; --! General enable
manual_rst_n_o : out STD_LOGIC; --! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM : in STD_LOGIC_VECTOR(2 downto 0);
FPGA_RTMP : in STD_LOGIC_VECTOR(2 downto 0));
end component;
type t_pulse_vector is
record
FRONT : STD_LOGIC_VECTOR(c_NUMBER_OF_CHANNELS - 1 downto 0);
REAR : STD_LOGIC_VECTOR(c_NUMBER_OF_CHANNELS - 1 downto 0);
end record;
subtype t_pulse_led_vector is t_pulse_vector;
type t_fpga_en is
record
GEN : STD_LOGIC;
BLO : STD_LOGIC;
TTL : STD_LOGIC;
INV : STD_LOGIC;
end record;
type t_I2C_master_out is
record
SCL : STD_LOGIC;
SDA : STD_LOGIC;
end record;
subtype t_I2C_slave_in is t_I2C_master_out;
type t_I2C_master_in is
record
SDA : STD_LOGIC;
end record;
subtype t_I2C_slave_out is t_I2C_master_in;
type t_SPI_master_out is
record
CCLK : STD_LOGIC;
CSO_B_N : STD_LOGIC;
MOSI : STD_LOGIC;
end record;
subtype t_SPI_slave_in is t_SPI_master_out;
type t_SPI_master_in is
record
DIN : STD_LOGIC;
end record;
subtype t_SPI_slave_out is t_SPI_master_in;
type t_RTM_id is
record
RTMM : STD_LOGIC_VECTOR(2 downto 0);
RTMP : STD_LOGIC_VECTOR(2 downto 0);
end record;
end image1_top_pkg;
package body image1_top_pkg is
end image1_top_pkg;
hdl/basic_trigger/.gitignore 0 → 100644
View file @ a81703d3
#Ignore LaTeX trash
doc/.*
doc/.*_*
doc/*.*
doc/.*.*.swp
doc/.*.*.swp
doc/Figures/*.eps
!doc/*.tex
!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
project/bitstream/*.*
!project/bitstream/basic_trigger_top.bit
!project/project.gise
!project/project.xise
!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
test/.*.*.swo
test/.*.*.swp
hdl/basic_trigger/rtl/basic_trigger_top.vhd
View file @ a81703d3
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 09:58:06 10/12/2011
--
-- Create Date: 09:58:06 10/12/2011
-- Design Name: HDL trigger top
-- Module Name: trigger - Behavioral
-- Module Name: trigger - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Tool versions:
-- Description: This is the wishbone trigger which receives a input
-- and outputs a trigger signal for the pulse converter.
-- It internally debounces the inputs and control the output
......@@ -15,9 +15,9 @@
-- The registers it has can be modified via wishbone access.
-- Dependencies: none
--
-- Revision:
-- Revision:
-- Revision 0.1
-- Additional Comments:
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
......@@ -30,8 +30,7 @@ use UNISIM.VCOMPONENTS.ALL;
entity basic_trigger_top is
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (
FPGA_CLK_P : in STD_LOGIC;
FPGA_CLK_N : in STD_LOGIC;
clk_125m_i : in STD_LOGIC;
led_pw_o : out STD_LOGIC;
led_err_o : out STD_LOGIC;
......@@ -69,8 +68,8 @@ end basic_trigger_top;
architecture Behavioral of basic_trigger_top is
signal s_pulse_i : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_i_front : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_i : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_i_front : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_pulse_n_o : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
signal s_led : STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1);
......@@ -127,8 +126,8 @@ begin
led_ttl_o <= not(s_level);
led_link_up_o <= not(s_locked);
led_pps_o <= '1';
led_wr_ok_o <= '1';
led_pps_o <= '1';
led_wr_ok_o <= '1';
--! s_level '1' means TTL input, as we have one inverter in the board we
--! invert here.
......@@ -151,12 +150,7 @@ begin
--! and a buffer in the output, there's no need
--! of invert here.
U_Buf_CLK_PLL : IBUFGDS
generic map (DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE)
port map (O => s_clk_125m_i, -- Buffer output
I => FPGA_CLK_P,
IB => FPGA_CLK_N);
s_clk_125m_i <= clk_125m_i;
-- set up the fabric PLL_BASE to drive the BUFPLL
pll_base_inst : PLL_BASE
......@@ -195,13 +189,13 @@ begin
i_repetitors: for i in 1 to g_NUMBER_OF_CHANNELS generate
begin
trigger: basic_trigger_core
port map (
wb_rst_i => s_rst(c_RST_CLKS - 1),
wb_clk_i => s_clk_200m,
port map (
wb_rst_i => s_rst(c_RST_CLKS - 1),
wb_clk_i => s_clk_200m,
pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i),
pulse_n_o => s_pulse_n_o(i),
pulse_i => s_pulse_i(i),
pulse_o => s_pulse_o(i),
pulse_n_o => s_pulse_n_o(i),
crop_o => open,
......
hdl/basic_trigger_async/.gitignore 0 → 100644
View file @ a81703d3
#Ignore LaTeX trash
doc/.*
doc/.*_*
doc/*.*
doc/.*.*.swp
doc/.*.*.swp
doc/Figures/*.eps
!doc/*.tex
!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
project/bitstream_async/*.*
!project/bitstream_async/basic_trigger_top.bit
!project/bitstream_async/basic_trigger_top.bit!project/project.gise
!project/project.xise
!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
test/.*.*.swo
test/.*.*.swp
hdl/i2c_slave_wb_master/.gitignore
View file @ a81703d3
#Ignore LaTeX trash
./doc/.*
./doc/.*.swo
./doc/.*.swp
./doc/Figures/*.eps
doc/.*
doc/.*_*
doc/*.*
doc/.*.*.swp
doc/.*.*.swp
doc/Figures/*.eps
!doc/*.tex
!doc/*.pdf
#Ignore autotrash from ISE
./project/
!/project/project.gise
!/project/project.xise
!/project/waveform/
project/*
project/*/
!project/project.gise
!project/project.xise
!project/waveform/
#Ignore swap files at rtl/ and test/ folders
./rtl/.*.swo
./rtl/.*.swp
./test/.*.swo
./test/.*.swp
rtl/.*.*.swo
rtl/.*.*.swp
test/.*.*.swo
test/.*.*.swp
hdl/i2c_slave_wb_master/doc/Figures/I2C_drawings.svg
View file @ a81703d3
......@@ -71,7 +71,7 @@
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
......@@ -6555,7 +6555,10 @@
<g
style="fill:none;stroke:#c00000;stroke-width:2;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
transform="translate(-76,0)"
id="g8125-6-7-5">
id="g8125-6-7-5"
inkscape:export-filename="/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/i2c_slave_wb_master/doc/Figures/i2c_write.png"
inkscape:export-xdpi="300"
inkscape:export-ydpi="300">
<g
style="fill:none;stroke:#c00000;stroke-width:2;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="g8051-7-4-98-5"
......@@ -6594,7 +6597,10 @@
<g
id="g8125-7-3-6-5"
style="fill:none;stroke:#c00000;stroke-width:2;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
transform="translate(44,-1.7812499e-7)">
transform="translate(44,-1.7812499e-7)"
inkscape:export-filename="/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/i2c_slave_wb_master/doc/Figures/i2c_write.png"
inkscape:export-xdpi="300"
inkscape:export-ydpi="300">
<g
style="fill:none;stroke:#c00000;stroke-width:2;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="g8051-7-8-7-0-7"
......@@ -6636,7 +6642,10 @@
id="g8125-6-7-5-18">
<g
id="g15119"
transform="translate(-6.5213013,0)">
transform="translate(-6.5213013,0)"
inkscape:export-filename="/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/i2c_slave_wb_master/doc/Figures/i2c_write.png"
inkscape:export-xdpi="300"
inkscape:export-ydpi="300">
<g
style="fill:none;stroke:#c00000;stroke-width:2;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="g15107"
......@@ -6678,7 +6687,10 @@
</g>
<g
id="g15173"
transform="translate(12,0)">
transform="translate(12,0)"
inkscape:export-filename="/media/BACKUP/CERN/contrib/ohwr-git/conv-ttl-blo/hdl/i2c_slave_wb_master/doc/Figures/i2c_write.png"
inkscape:export-xdpi="300"
inkscape:export-ydpi="300">
<g
style="fill:none;stroke:#0000be;stroke-width:2;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="g15107-1"
......
hdl/i2c_slave_wb_master/project/project.gise
View file @ a81703d3
......@@ -169,11 +169,10 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1352382626" xil_pn:in_ck="6441921431846390163" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8022121412301228921" xil_pn:start_ts="1352382619">
<status xil_pn:value="FailedRun"/>
<transform xil_pn:end_ts="1353947874" xil_pn:in_ck="6441921431846390163" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8022121412301228921" xil_pn:start_ts="1353947856">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="i2c_bit.ngr"/>
<outfile xil_pn:name="i2c_slave_core.ngr"/>
......@@ -181,6 +180,7 @@
<outfile xil_pn:name="i2c_slave_top.ngc"/>
<outfile xil_pn:name="i2c_slave_top.ngr"/>
<outfile xil_pn:name="i2c_slave_top.prj"/>
<outfile xil_pn:name="i2c_slave_top.stx"/>
<outfile xil_pn:name="i2c_slave_top.syr"/>
<outfile xil_pn:name="i2c_slave_top.xst"/>
<outfile xil_pn:name="i2c_slave_top_tb_beh.prj"/>
......
hdl/i2c_slave_wb_master/project/project.xise
View file @ a81703d3
......@@ -25,15 +25,15 @@
</file>
<file xil_pn:name="../rtl/i2c_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../rtl/i2c_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../test/i2c_slave_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
......@@ -55,7 +55,7 @@
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_clk_divider.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ a81703d3
......@@ -525,20 +525,24 @@ begin
end process;
--! @brief Small process that records the length of a
--! bit over the I2C interface.
--! @param i2c_SLA_fsm Actual value of the fsm
--! @param i2c_SLA_fsm_d0 One-wb_clocked delayed value of the fsm
p_LT_SCLP: process(i2c_SLA_fsm,
i2c_SLA_fsm_d0)
variable v_count : STD_LOGIC_VECTOR(23 downto 0);
--! @brief Small process that records the length of a
--! bit over the I2C interface.
--! @param clk Main clock
p_LT_SCLP: process(clk)
variable v_count : STD_LOGIC_VECTOR(23 downto 0);
begin
if i2c_SLA_fsm = S2A_I2C_ADDR_ACK
and i2c_SLA_fsm_d0 = S2_I2C_ADDR then
if rising_edge(clk) then
if i2c_SLA_fsm = R0_RESET then
s_LT.SCLP <= c_LT_default.SCLP;
else
if i2c_SLA_fsm = S2A_I2C_ADDR_ACK
and i2c_SLA_fsm_d0 = S2_I2C_ADDR then
--! Here we do a division bit 8, because the watchdog timer,
--! is counting for 8 scl clocks
v_count := s_watchdog_cnt_slv(24 - 1 + 3 downto 3);
s_LT.SCLP <= UNSIGNED(v_count);
v_count := s_watchdog_cnt_slv(24 - 1 + 3 downto 3);
s_LT.SCLP <= UNSIGNED(v_count);
end if;
end if;
end if;
end process;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
View file @ a81703d3
......@@ -91,6 +91,7 @@ begin
pf_wb_addr_o <= s_pf_wb_addr;
rd_done_o <= s_rd_done;
wr_done_o <= s_wr_done;
--! Added for simulation
s_CTR0 <= f_CTR0(s_CTR0_slv);
inst_i2c_slave_core: i2c_slave_core
......
hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
View file @ a81703d3
......@@ -62,10 +62,6 @@ architecture Behavioral of i2c_master_driver is
signal s_active_link : STD_LOGIC := '0';
signal s_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0);
signal s_DTX : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
file_open(s_file_handler, c_LOG_PATH, WRITE_MODE);
......@@ -87,7 +83,7 @@ begin
p_sda: process
variable v_bit_number : NATURAL := 0;
variable v_write_data : STD_LOGIC_VECTOR(g_RD_DATA_LENGTH - 1 downto 0);
variable v_i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0);
--! @brief Function that returns strings for the acked field to be
--! logged.
......@@ -118,17 +114,6 @@ begin
return v_return;
end function;
function order_i2c_addr_op(
i2c_addr_op : STD_LOGIC_VECTOR(7 downto 0))
return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(7 downto 0);
begin
for i in 0 to 7 loop
v_return(7-i) := i2c_addr_op(i);
end loop;
return v_return;
end function;
--! @brief Function to reorder data before being sent by driver
--! through SDA
--! @param data Data to be reordered before being sent
......@@ -199,9 +184,10 @@ begin
wait until falling_edge(s_scl_clk);
end procedure;
--! @brieg Procedure to start/restart I2C communication
procedure start_restart_I2c is
begin
begin
if start_i = '1' then
wait until rising_edge(s_scl_clk);
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '0';
......@@ -211,86 +197,22 @@ begin
s_start_done <= '1';
wait until rising_edge(tb_clk);
s_start_done <= '0';
end procedure;
--! @brief Procedure to pause I2c communication
procedure pause_I2C is
begin
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '0';
wait until rising_edge(s_scl_clk);
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '1';
s_active_link <= '1';
--! We allow one clock to let i2c_slave_core.vhd to react
wait until rising_edge(tb_clk);
s_pause_done <= '1';
wait until rising_edge(tb_clk);
s_pause_done <= '0';
s_active_link <= '0';
end procedure;
procedure read_bit is
variable v_bit_rcv : STD_LOGIC;
begin
wait until rising_edge(s_scl_clk);
v_bit_rcv := sda_master_i;
for i in 0 to (g_SCL_PERIOD/2)/(1 ns) - 1 loop
if v_bit_rcv /= sda_master_i then
--! Here we report an error
end if;
wait for 1 ns;
end loop;
wait until falling_edge(s_scl_clk);
s_DTX(s_DTX'length - 1) <= v_bit_rcv;
end procedure;
procedure shift_bit is
begin
for i in 1 to s_DTX'length - 1 loop
s_DTX(i-1) <= s_DTX(i);
end loop;
end procedure;
procedure read_byte is
begin
for i in 0 to 7 loop
read_bit;
shift_bit;
end loop;
--! At the end we are just in the falling edge of scl
end procedure;
procedure place_ack is
begin
elsif pause_i = '1' then
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '0';
wait until falling_edge(s_scl_clk);
s_sda_master_o <= '1';
end procedure;
procedure place_nack is
begin
wait until rising_edge(s_scl_clk);
wait for g_SCL_PERIOD/4;
s_sda_master_o <= '1';
s_active_link <= '1';
wait until falling_edge(s_scl_clk);
s_sda_master_o <= '0';
end procedure;
begin
if start_i = '1' then
start_restart_I2c;
elsif pause_i = '1' then
pause_I2C;
s_pause_done <= '1';
wait for 1 ns;
s_pause_done <= '0';
elsif write_i = '1' then
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
v_i2c_addr_op := i2c_addr_op_i;
v_i2c_addr_op(0) := '0';
send_byte(order_i2c_addr_op(v_i2c_addr_op));
send_byte(i2c_addr_op_i);
check_ack(s_test_id, "WRITE", ADDRESS_0);
--! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8));
......@@ -310,47 +232,8 @@ begin
--! 7.- Send DATA3
send_byte(wr_data_i(31 downto 24));
check_ack(s_test_id, "WRITE", DATA3);
pause_I2C;
s_write_done <= '1';
wait until rising_edge(tb_clk);
s_write_done <= '0';
s_active_link <= '0';
elsif read_i = '1' then
s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0]
v_i2c_addr_op := i2c_addr_op_i;
v_i2c_addr_op(0) := '0';
send_byte(order_i2c_addr_op(v_i2c_addr_op));
check_ack(s_test_id, " READ", ADDRESS_0);
--! 2.- Send wishbone address high
send_byte(wishbone_addr_i(15 downto 8));
check_ack(s_test_id, " READ", WISHBONE_HIGH);
--! 3.- Send wishbone address low
send_byte(wishbone_addr_i(7 downto 0));
check_ack(s_test_id, " READ", WISHBONE_LOW);
--! 4.- We have to place a start condition
start_restart_I2c;
--! 5.- Send [ADDRESS|1]
v_i2c_addr_op(7 downto 1) := i2c_addr_op_i(7 downto 1);
v_i2c_addr_op(0) := '1';
send_byte(order_i2c_addr_op(v_i2c_addr_op));
check_ack(s_test_id, " READ", ADDRESS_0);
--! 6.- Read DATA0
read_byte;
place_ack;
--! 7.- Read DATA1
read_byte;
place_ack;
--! 8.- Read DATA2
read_byte;
place_ack;
--! 9.- Read DATA3
read_byte;
place_ack;
pause_I2C;
s_read_done <= '1';
wait until rising_edge(tb_clk);
s_read_done <= '0';
end if;
wait until rising_edge(tb_clk);
end process;
......
hdl/m25p32/.gitignore 0 → 100644
View file @ a81703d3
#Ignore LaTeX trash
doc/.*
doc/.*_*
doc/*.*
doc/.*.*.swp
doc/.*.*.swp
doc/Figures/*.eps
!doc/*.tex
!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
!project/project.gise
!project/project.xise
!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
test/.*.*.swo
test/.*.*.swp
test/sv/*
hdl/multiboot/.gitignore 0 → 100644
View file @ a81703d3
#Ignore LaTeX trash
doc/.*
doc/.*_*
doc/*.*
doc/.*.*.swp
doc/.*.*.swp
doc/Figures/*.eps
!doc/*.tex
!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
!project/project.gise
!project/project.xise
!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
test/.*.*.swo
test/.*.*.swp
hdl/multiboot/project/multiboot.xise
View file @ a81703d3
......@@ -45,11 +45,11 @@
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ctdah_lib/test/wishbone_driver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
......
hdl/multiboot/rtl/basic_trigger_top.rbt 0 → 100644
View file @ a81703d3
This diff is collapsed.
hdl/multiboot/rtl/multiboot_pkg.vhd
View file @ a81703d3
......@@ -361,7 +361,7 @@ package body multiboot_pkg is
--! @brief STAT register translation function from r_STAT to slv
--! @param r_register slv to be translated
function f_STD_LOGIC_VECTOR (r_register : r_STAT) return STD_LOGIC_VECTOR is
variable v_return : STD_LOGIC_VECTOR(31 downto 0);
variable v_return : STD_LOGIC_VECTOR(15 downto 0);
begin
v_return(0) := r_register.CRC;
v_return(1) := r_register.ID;
......
hdl/multiboot/rtl/multiboot_regs.vhd
View file @ a81703d3
......@@ -126,13 +126,19 @@ begin
when '0' =>
case v_wb_addr is
when CTR0_addr =>
s_wb_data_o <= f_STD_LOGIC_VECTOR(s_CTR0);
s_wb_data_o (31 downto 8) <= (others => '0');
s_wb_data_o ( 7 downto 0)
<= f_STD_LOGIC_VECTOR(s_CTR0);
s_wb_ack <= '1';
when CTR1_addr =>
s_wb_data_o <= f_STD_LOGIC_VECTOR(s_CTR1);
s_wb_data_o (31 downto 8) <= (others => '0');
s_wb_data_o ( 7 downto 0)
<= f_STD_LOGIC_VECTOR(s_CTR1);
s_wb_ack <= '1';
when STAT_addr =>
s_wb_data_o <= f_STD_LOGIC_VECTOR(s_STAT);
s_wb_data_o (31 downto 16) <= (others => '0');
s_wb_data_o (15 downto 0)
<= f_STD_LOGIC_VECTOR(s_STAT);
s_wb_ack <= '1';
when c_MBA_addr =>
s_wb_data_o <= f_STD_LOGIC_VECTOR(s_MBA);
......
hdl/multiboot/test/basic_trigger_top.rbt 0 → 100644
View file @ a81703d3
This diff is collapsed.
hdl/multiboot/test/log/multiboot_core_tb.log 0 → 100644
View file @ a81703d3
-----------------------------------------
----- multiboot_core_tb.vhd -----
-----------------------------------------
Test ID Status Description
0x0 OK GENERAL1_ICAP register initialization
0x1 OK GENERAL2_ICAP register initialization
0x2 OK GENERAL3_ICAP register initialization
0x3 OK GENERAL4_ICAP register initialization
0x4 OK STAT_ICAP register initialization
0x5 OK Multiboot sequence is correct
0x6 OK GENERAL1 write sequence is correct
0x7 OK GENERAL2 write sequence is correct
hdl/multiboot/test/modelsim/multiboot_wave.do 0 → 100644
View file @ a81703d3
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider multiboot_regs.vhd
add wave -noupdate /multiboot_tb/uut/multiboot_regs_inst/CTRL_s
add wave -noupdate /multiboot_tb/uut/multiboot_regs_inst/STAT_s
add wave -noupdate /multiboot_tb/uut/multiboot_regs_inst/GENERAL1_s
add wave -noupdate /multiboot_tb/uut/multiboot_regs_inst/GENERAL2_s
add wave -noupdate /multiboot_tb/uut/multiboot_regs_inst/GENERAL3_s
add wave -noupdate /multiboot_tb/uut/multiboot_regs_inst/GENERAL4_s
add wave -noupdate -divider multiboot_core.vhd
add wave -noupdate -divider multiboot_top.vhd
add wave -noupdate /multiboot_tb/wb_rst_i
add wave -noupdate /multiboot_tb/wb_clk
add wave -noupdate /multiboot_tb/wb_we_i
add wave -noupdate -group wb_ops /multiboot_tb/wb_stb_i
add wave -noupdate -group wb_ops /multiboot_tb/wb_cyc_i
add wave -noupdate -group wb_ops /multiboot_tb/wb_ack_o
add wave -noupdate -group wb_ops /multiboot_tb/wb_rty_o
add wave -noupdate -group wb_ops /multiboot_tb/wb_err_o
add wave -noupdate -group wb_data -radix hexadecimal /multiboot_tb/wb_data_i
add wave -noupdate -group wb_data -radix hexadecimal /multiboot_tb/wb_data_o
add wave -noupdate -group wb_data -radix hexadecimal /multiboot_tb/wb_addr_i
add wave -noupdate -divider multiboot_top_tb.vhd
add wave -noupdate -radix hexadecimal /multiboot_tb/GENERAL1_data
add wave -noupdate -radix hexadecimal /multiboot_tb/GENERAL2_data
add wave -noupdate -radix hexadecimal /multiboot_tb/GENERAL3_data
add wave -noupdate -radix hexadecimal /multiboot_tb/GENERAL4_data
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {125000 ps} 0}
configure wave -namecolwidth 388
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {1470 ns}
hdl/rtm_detector/.gitignore 0 → 100644
View file @ a81703d3
#Ignore swap files
rtl/.*.*.swo
rtl/.*.*.swp
rtl/.swp
rtl/.swo
hdl/rtm_detector/rtl/rtm_detector.vhd 0 → 100644
View file @ a81703d3
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.rtm_detector_pkg.ALL;
entity rtm_detector is
generic(g_identifier_RTMM : t_RTMM;
g_identifier_RTMP : t_RTMP);
port (RTMM_i : in STD_LOGIC_VECTOR(2 downto 0);
RTMP_i : in STD_LOGIC_VECTOR(2 downto 0);
ok_RTMM_o : out STD_LOGIC;
ok_RTMP_o : out STD_LOGIC);
end rtm_detector;
architecture Behavioral of rtm_detector is
signal s_identifier_RTMM : UNSIGNED(2 downto 0)
:= f_UNSIGNED(g_identifier_RTMM);
signal s_identifier_RTMP : UNSIGNED(2 downto 0)
:= f_UNSIGNED(g_identifier_RTMP);
signal s_RTMM : UNSIGNED(2 downto 0);
signal s_RTMP : UNSIGNED(2 downto 0);
begin
s_RTMM <= UNSIGNED(RTMM_i);
s_RTMP <= UNSIGNED(RTMP_i);
ok_RTMM_o <= '1' when s_RTMM = s_identifier_RTMM
else '0';
ok_RTMP_o <= '1' when s_RTMP = s_identifier_RTMP
else '0';
end Behavioral;
hdl/rtm_detector/rtl/rtm_detector_pkg.vhd 0 → 100644
View file @ a81703d3
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package rtm_detector_pkg is
--! Please refer to:
--! http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--! to see conventions used to guarantee consistency between front board
--! and read transition modules
--! It should be noted that the RTMM, and RTMP pins are pulled up in
--! all the Front boards.
--! On 27/Nov/2012 the correspondencies are:
--!
--! __________________________________________
--! | Board | RTMM[2] | RTMM[1] | RTMM[0] |
--! +-----------------------------------------+
--! | Error | '1' | '1' | '1' |
--! | RTMM_V1 | '1' | '1' | '0' |
--! | Reserved0 | '1' | '0' | '1' |
--! | Reserved1 | '1' | '0' | '0' |
--! | Reserved2 | '0' | '1' | '1' |
--! | Reserved3 | '0' | '1' | '0' |
--! | Reserved4 | '0' | '0' | '1' |
--! | Reserved5 | '0' | '0' | '0' |
--! +-----------+---------+---------+---------+
--!
--! _____________________________________________
--! | Board | RTMP[2] | RTMP[1] | RTMP[0] |
--! +-------------------------------------------+
--! | Error | '1' | '1' | '1' |
--! | Blocking_V1 | '1' | '1' | '0' |
--! | RS485_V1 | '1' | '0' | '1' |
--! | Reserved0 | '1' | '0' | '0' |
--! | Reserved1 | '0' | '1' | '1' |
--! | Reserved2 | '0' | '1' | '0' |
--! | Reserved3 | '0' | '0' | '1' |
--! | Reserved4 | '0' | '0' | '0' |
--! +-------------+---------+---------+---------+
--!
--! It should be noted that there is an inverter before the FPGA,
--! so the signals/constant will be negated in rtm_detector.vhd
type t_RTMM is (RTMM_ERROR,
RTMM_V1,
RESERVED0,
RESERVED1,
RESERVED2,
RESERVED3,
RESERVED4,
RESERVED5);
type t_RTMP is (RTMP_ERROR,
RTMP_BLOCKING_V1,
RTMP_RS485_V1,
RESERVED0,
RESERVED1,
RESERVED2,
RESERVED3,
RESERVED4);
constant c_RTMM_ERROR : UNSIGNED(2 downto 0) := "111";
constant c_RTMM_V1 : UNSIGNED(2 downto 0) := "110";
constant c_RTMM_RESERVED0 : UNSIGNED(2 downto 0) := "101";
constant c_RTMM_RESERVED1 : UNSIGNED(2 downto 0) := "100";
constant c_RTMM_RESERVED2 : UNSIGNED(2 downto 0) := "011";
constant c_RTMM_RESERVED3 : UNSIGNED(2 downto 0) := "010";
constant c_RTMM_RESERVED4 : UNSIGNED(2 downto 0) := "001";
constant c_RTMM_RESERVED5 : UNSIGNED(2 downto 0) := "000";
constant c_RTMP_ERROR : UNSIGNED(2 downto 0) := "111";
constant c_RTMP_BLOCKING_V1 : UNSIGNED(2 downto 0) := "110";
constant c_RTMP_RS485_V1 : UNSIGNED(2 downto 0) := "101";
constant c_RTMP_RESERVED0 : UNSIGNED(2 downto 0) := "100";
constant c_RTMP_RESERVED1 : UNSIGNED(2 downto 0) := "011";
constant c_RTMP_RESERVED2 : UNSIGNED(2 downto 0) := "010";
constant c_RTMP_RESERVED3 : UNSIGNED(2 downto 0) := "001";
constant c_RTMP_RESERVED4 : UNSIGNED(2 downto 0) := "000";
function f_UNSIGNED(identifier: t_RTMM) return UNSIGNED;
function f_UNSIGNED(identifier: t_RTMP) return UNSIGNED;
function f_RTMM(bit_code: UNSIGNED(2 downto 0)) return t_RTMM;
function f_RTMP(bit_code: UNSIGNED(2 downto 0)) return t_RTMP;
end rtm_detector_pkg;
package body rtm_detector_pkg is
--! @brief translation function from t_rtmp to unsigned
--! @param identifier t_rtmp type to be translated
function f_UNSIGNED(identifier: t_RTMM) return UNSIGNED is
variable v_return : UNSIGNED(2 downto 0);
begin
v_return := c_RTMM_ERROR;
case identifier is
when RTMM_ERROR =>
null;
when RTMM_V1 =>
v_return := c_RTMM_V1;
when RESERVED0 =>
v_return := c_RTMM_RESERVED0;
when RESERVED1 =>
v_return := c_RTMM_RESERVED1;
when RESERVED2 =>
v_return := c_RTMM_RESERVED2;
when RESERVED3 =>
v_return := c_RTMM_RESERVED3;
when RESERVED4 =>
v_return := c_RTMM_RESERVED4;
when RESERVED5 =>
v_return := c_RTMM_RESERVED5;
when others =>
null;
end case;
return v_return;
end f_UNSIGNED;
--! @brief translation function from t_rtmp to unsigned
--! @param identifier t_rtmp type to be translated
function f_UNSIGNED(identifier: t_RTMP) return UNSIGNED is
variable v_return : UNSIGNED(2 downto 0);
begin
v_return := c_RTMP_ERROR;
case identifier is
when RTMP_ERROR =>
null;
when RTMP_BLOCKING_V1 =>
v_return := c_RTMP_BLOCKING_V1;
when RTMP_RS485_V1 =>
v_return := c_RTMP_RS485_V1;
when RESERVED0 =>
v_return := c_RTMP_RESERVED0;
when RESERVED1 =>
v_return := c_RTMP_RESERVED1;
when RESERVED2 =>
v_return := c_RTMP_RESERVED2;
when RESERVED3 =>
v_return := c_RTMP_RESERVED3;
when RESERVED4 =>
v_return := c_RTMP_RESERVED4;
when others =>
null;
end case;
return v_return;
end f_UNSIGNED;
--! @brief translation function from unsigned to t_RTMM
--! @param bit_code bit_code to be translated
function f_RTMM(bit_code: UNSIGNED(2 downto 0)) return t_RTMM is
variable v_return : t_RTMM;
begin
v_return := RTMM_ERROR;
case bit_code is
when c_RTMM_ERROR =>
null;
when c_RTMM_V1 =>
v_return := RTMM_V1;
when c_RTMM_RESERVED0 =>
v_return := RESERVED0;
when c_RTMM_RESERVED1 =>
v_return := RESERVED1;
when c_RTMM_RESERVED2 =>
v_return := RESERVED2;
when c_RTMM_RESERVED3 =>
v_return := RESERVED3;
when c_RTMM_RESERVED4 =>
v_return := RESERVED4;
when c_RTMM_RESERVED5 =>
v_return := RESERVED5;
when others =>
null;
end case;
return v_return;
end f_RTMM;
--! @brief translation function from unsigned to t_RTMP
--! @param bit_code bit_code to be translated
function f_RTMP(bit_code: UNSIGNED(2 downto 0)) return t_RTMP is
variable v_return : t_RTMP;
begin
v_return := RTMP_ERROR;
case bit_code is
when c_RTMP_ERROR =>
null;
when c_RTMP_BLOCKING_V1 =>
v_return := RTMP_BLOCKING_V1;
when c_RTMP_RS485_V1 =>
v_return := RTMP_RS485_V1;
when c_RTMP_RESERVED0 =>
v_return := RESERVED0;
when c_RTMP_RESERVED1 =>
v_return := RESERVED1;
when c_RTMP_RESERVED2 =>
v_return := RESERVED2;
when c_RTMP_RESERVED3 =>
v_return := RESERVED3;
when c_RTMP_RESERVED4 =>
v_return := RESERVED4;
when others =>
null;
end case;
return v_return;
end f_RTMP;
end rtm_detector_pkg;
hdl/spi_master_multifield/.gitignore 0 → 100644
View file @ a81703d3
#Ignore LaTeX trash
doc/.*
doc/.*_*
doc/*.*
doc/.*.*.swp
doc/.*.*.swp
doc/Figures/*.eps
!doc/*.tex
!doc/*.pdf
#Ignore autotrash from ISE
project/*
project/*/
!project/project.gise
!project/project.xise
!project/waveform/
#Ignore swap files at rtl/ and test/ folders
rtl/.*.*.swo
rtl/.*.*.swp
test/.*.*.swo
test/.*.*.swp
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