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Conv TTL Blocking
Commit a9e62b25 authored by Carlos Gil Soriano's avatar Carlos Gil Soriano
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Committed last modification on IP cores for remote programming before merging:… 

Committed last modification on IP cores for remote programming before merging: ctdah_lib, i2c_slave_wb_master, m25p32, multiboot, spi_master_multifield
parent 078498ba
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hdl/m25p32/test/m25p32_top_tb_pkg.vhd
View file @ a9e62b25
......@@ -39,10 +39,8 @@ package m25p32_top_tb_pkg is
constant c_WISHBONE_PERIOD : TIME := 50 ns; --! Working at 20MHz
component m25p32_top is
generic(
g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port (
wb_rst_i : in STD_LOGIC;
generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
port (wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
......@@ -62,8 +60,7 @@ package m25p32_top_tb_pkg is
prom_mosi_o : out STD_LOGIC;
prom_cclk_o : out STD_LOGIC;
prom_cs0_b_n_o : out STD_LOGIC;
prom_din_i : in STD_LOGIC
);
prom_din_i : in STD_LOGIC);
end component;
procedure wishbone_write (
......
hdl/multiboot/test/multiboot_core_tb.vhd
View file @ a9e62b25
-- TestBench Template
library IEEE;
library work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
use work.multiboot_pkg.ALL;
ENTITY multiboot_core_tb IS
END multiboot_core_tb;
entity multiboot_core_tb is
end multiboot_core_tb;
ARCHITECTURE behavior OF multiboot_core_tb IS
architecture behavior of multiboot_core_tb is
component multiboot_core
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
CTRL0_i : in STD_LOGIC_VECTOR (15 downto 0);
CTRL1_o : out STD_LOGIC_VECTOR (15 downto 0);
STAT_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL1_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL2_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL3_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL4_i : in STD_LOGIC_VECTOR (15 downto 0);
GENERAL1_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL2_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL3_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0);
GENERAL4_ICAP_o : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
constant c_CLK_PERIOD : TIME := 50 ns;
signal rst : STD_LOGIC;
signal clk : STD_LOGIC;
signal CTRL0_i : STD_LOGIC_VECTOR (15 downto 0);
signal CTRL1_o : STD_LOGIC_VECTOR (15 downto 0);
signal STAT_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL1_i : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL2_i : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL3_i : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL4_i : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL1_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL2_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL3_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
signal GENERAL4_ICAP_o : STD_LOGIC_VECTOR (15 downto 0);
constant clk_period : TIME := 200 ns;
constant OP_FULLMULTIBOOT : STD_LOGIC_VECTOR(3 downto 0) := X"0";
constant OP_WR_GENERAL1 : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant OP_WR_GENERAL2 : STD_LOGIC_VECTOR(3 downto 0) := X"2";
constant OP_WR_GENERAL3 : STD_LOGIC_VECTOR(3 downto 0) := X"3";
constant OP_WR_GENERAL4 : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant OP_RD_GENERAL1 : STD_LOGIC_VECTOR(3 downto 0) := X"5";
constant OP_RD_GENERAL2 : STD_LOGIC_VECTOR(3 downto 0) := X"6";
constant OP_RD_GENERAL3 : STD_LOGIC_VECTOR(3 downto 0) := X"7";
constant OP_RD_GENERAL4 : STD_LOGIC_VECTOR(3 downto 0) := X"8";
constant OP_IPROG : STD_LOGIC_VECTOR(3 downto 0) := X"C";
constant OP_STAT : STD_LOGIC_VECTOR(3 downto 0) := X"D";
signal CTR0_o : r_CTR0;
signal CTR1_i : r_CTR1;
signal STAT_i : r_STAT;
signal MBA_i : r_BAR;
signal GBA_i : r_BAR;
signal MBA_ICAP_o : STD_LOGIC_VECTOR (23 downto 0);
signal GBA_ICAP_o : STD_LOGIC_VECTOR (23 downto 0));
file file_handler : TEXT;
constant log_path : STRING := "../test/log/multiboot_core_tb.log";
constant c_LOG_PATH : STRING := "../test/log/multiboot_core_tb.log";
constant sep : CHARACTER := ht;
begin
uut: multiboot_core
port map(
clk => clk,
port map(clk => clk,
rst => rst,
CTRL0_i => CTRL0_i,
CTRL1_o => CTRL1_o,
STAT_ICAP_o => STAT_ICAP_o,
GENERAL1_i => GENERAL1_i,
GENERAL2_i => GENERAL2_i,
GENERAL3_i => GENERAL3_i,
GENERAL4_i => GENERAL4_i,
GENERAL1_ICAP_o => GENERAL1_ICAP_o,
GENERAL2_ICAP_o => GENERAL2_ICAP_o,
GENERAL3_ICAP_o => GENERAL3_ICAP_o,
GENERAL4_ICAP_o => GENERAL4_ICAP_o
);
CTR0_o => CTR0_o,
CTR1_i => CTR1_i,
STAT_i => STAT_i,
MBA_i => MBA_i,
GBA_i => GBA_i,
MBA_ICAP_o => MBA_addr_o,
GBA_ICAP_o => GBA_addr_o);
clk_process: process
begin
clk <= '1';
wait for clk_period/2;
wait for c_CLK_PERIOD/2;
clk <= '0';
wait for clk_period/2;
wait for c_CLK_PERIOD/2;
end process;
......@@ -95,23 +55,18 @@ begin
procedure reset_proc is
begin
wait for clk_period;
GENERAL1_i <= (others => '0');
GENERAL2_i <= (others => '0');
GENERAL3_i <= (others => '0');
GENERAL4_i <= (others => '0');
CTRL0_i <= (others => '0');
wait until rising_edge(clk);
rst <= '1';
wait for clk_period;
CTR1_i <= c_CTR1_default;
wait for c_CLK_PERIOD;
rst <= '0';
wait for clk_period*25;
wait for c_CLK_PERIOD*25;
end reset_proc;
procedure assert16_to_file(data:STD_LOGIC_VECTOR(15 downto 0);
reference:STD_LOGIC_VECTOR(15 downto 0);
test_id :string; msg :string) is
procedure assert16_to_file(data : STD_LOGIC_VECTOR(15 downto 0);
reference : STD_LOGIC_VECTOR(15 downto 0);
test_id : STRING;
msg : STRING) is
variable line_buffer : LINE;
begin
if data = reference then
......@@ -123,10 +78,10 @@ begin
assert data = reference report "Bad"&msg;
end procedure;
procedure assert32_to_file(data:STD_LOGIC_VECTOR(31 downto 0);
reference:STD_LOGIC_VECTOR(31 downto 0);
test_id :string; msg :string) is
procedure assert32_to_file(data : STD_LOGIC_VECTOR(31 downto 0);
reference : STD_LOGIC_VECTOR(31 downto 0);
test_id : STRING;
msg : STRING) is
variable line_buffer : LINE;
begin
if data = reference then
......@@ -138,11 +93,10 @@ begin
assert data = reference report "Bad"&msg;
end procedure;
variable header_line_buffer : LINE;
begin
file_open(file_handler, log_path, WRITE_MODE);
begin
file_open(file_handler, c_LOG_PATH, WRITE_MODE);
write(header_line_buffer, string'("-----------------------------------------"));
writeline(file_handler, header_line_buffer);
write(header_line_buffer, string'("----- multiboot_core_tb.vhd -----"));
......@@ -156,7 +110,7 @@ begin
-- Initialization assert
wait for 2*clk_period;
wait for 2*c_CLK_PERIOD;
reset_proc;
assert16_to_file(GENERAL1_ICAP_o, X"0000", "0x0", "GENERAL1_ICAP register initialization");
assert16_to_file(GENERAL2_ICAP_o, X"0000", "0x1", "GENERAL2_ICAP register initialization");
......@@ -170,126 +124,124 @@ begin
GENERAL4_i <= X"DEF0";
-- We will test the full multiboot sequence
CTRL0_i(3 downto 0) <= OP_FULLMULTIBOOT;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
CTR0_i(3 downto 0) <= OP_FULLMULTIBOOT;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 13*clk_period;
wait for clk_period/2;
wait for 13*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x5", "Multiboot sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_WR_GENERAL1;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
assert16_to_file(CTR1_o, X"0001", "0x5", "Multiboot sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_WR_GENERAL1;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*clk_period;
wait for clk_period/2;
wait for 5*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x6", "GENERAL1 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_WR_GENERAL2;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
assert16_to_file(CTR1_o, X"0001", "0x6", "GENERAL1 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_WR_GENERAL2;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*clk_period;
wait for clk_period/2;
wait for 5*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x7", "GENERAL2 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_WR_GENERAL3;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
assert16_to_file(CTR1_o, X"0001", "0x7", "GENERAL2 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_WR_GENERAL3;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*clk_period;
wait for clk_period/2;
wait for 5*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x8", "GENERAL3 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_WR_GENERAL4;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
assert16_to_file(CTR1_o, X"0001", "0x8", "GENERAL3 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_WR_GENERAL4;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 5*clk_period;
wait for clk_period/2;
wait for 5*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0x9", "GENERAL4 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_RD_GENERAL1;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
assert16_to_file(CTR1_o, X"0001", "0x9", "GENERAL4 write sequence is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_RD_GENERAL1;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*clk_period;
wait for clk_period/2;
wait for 15*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0xA", "GENERAL1 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_RD_GENERAL2;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
assert16_to_file(CTR1_o, X"0001", "0xA", "GENERAL1 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_RD_GENERAL2;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*clk_period;
wait for clk_period/2;
wait for 15*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0xB", "GENERAL2 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_RD_GENERAL3;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
assert16_to_file(CTR1_o, X"0001", "0xB", "GENERAL2 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_RD_GENERAL3;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*clk_period;
wait for clk_period/2;
wait for 15*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0xC", "GENERAL3 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
CTRL0_i(3 downto 0) <= OP_RD_GENERAL4;
CTRL0_i(4) <= '1';
CTRL0_i(15 downto 5) <= (others => '0');
assert16_to_file(CTR1_o, X"0001", "0xC", "GENERAL3 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
CTR0_i(3 downto 0) <= OP_RD_GENERAL4;
CTR0_i(4) <= '1';
CTR0_i(15 downto 5) <= (others => '0');
-- Every wb_clk cycle the fsm should move one state. The chain state will be:
-- {S0_IDLE, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, Q0_OK, }
wait for 15*clk_period;
wait for clk_period/2;
wait for 15*c_CLK_PERIOD;
wait for c_CLK_PERIOD/2;
wait until rising_edge(clk);
assert16_to_file(CTRL1_o, X"0001", "0xD", "GENERAL4 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTRL0_i(4) bit
CTRL0_i(4) <= '0';
wait for 100*clk_period;
assert16_to_file(CTR1_o, X"0001", "0xD", "GENERAL4 fsm readback is correct");
-- We act as the multiboot_regs.vhd by deasserting CTR0_i(4) bit
CTR0_i(4) <= '0';
wait for 100*c_CLK_PERIOD;
assert false report "No error. Simulation ends." severity failure;
end process tb;
end process tb;
end;
end;
hdl/multiboot/test/multiboot_top_tb.vhd
View file @ a9e62b25
-- TestBench Template
library IEEE;
library work;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE std.textio.ALL;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use STD.TEXTIO.ALL;
use work.multiboot_pkg.ALL;
ENTITY multiboot_tb IS
END multiboot_tb;
entity multiboot_tb is
end multiboot_tb;
ARCHITECTURE behavior OF multiboot_tb IS
architecture behavior of multiboot_tb is
-- Component Declaration
component multiboot_top is
......@@ -41,23 +43,7 @@ ARCHITECTURE behavior OF multiboot_tb IS
signal wb_rty_o : STD_LOGIC;
signal wb_err_o : STD_LOGIC;
constant wb_clk_period : TIME := 50 ns;
constant OP_FULLMULTIBOOT : STD_LOGIC_VECTOR(3 downto 0) := X"0";
constant OP_GENERAL1 : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant OP_GENERAL2 : STD_LOGIC_VECTOR(3 downto 0) := X"2";
constant OP_GENERAL3 : STD_LOGIC_VECTOR(3 downto 0) := X"3";
constant OP_GENERAL4 : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant OP_IPROG : STD_LOGIC_VECTOR(3 downto 0) := X"7";
constant OP_STAT : STD_LOGIC_VECTOR(3 downto 0) := X"D";
constant CTRL0_addr : STD_LOGIC_VECTOR(3 downto 0) := X"0";
constant CTRL1_addr : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant STAT_addr : STD_LOGIC_VECTOR(3 downto 0) := X"2";
constant GENERAL1_addr : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant GENERAL2_addr : STD_LOGIC_VECTOR(3 downto 0) := X"5";
constant GENERAL3_addr : STD_LOGIC_VECTOR(3 downto 0) := X"6";
constant GENERAL4_addr : STD_LOGIC_VECTOR(3 downto 0) := X"7";
constant c_WB_CLK_PERIOD : TIME := 50 ns;
signal CTRL_data : STD_LOGIC_VECTOR(31 downto 0);
signal GENERAL1_data : STD_LOGIC_VECTOR(31 downto 0);
......@@ -66,14 +52,13 @@ ARCHITECTURE behavior OF multiboot_tb IS
signal GENERAL4_data : STD_LOGIC_VECTOR(31 downto 0);
file file_handler : TEXT;
constant log_path : STRING := "../test/log/multiboot_top_tb.log";
constant c_LOG_PATH : STRING := "../test/log/multiboot_top_tb.log";
constant sep : CHARACTER := ht;
begin
uut: multiboot_top
port map(
wb_rst_i => wb_rst_i,
port map(wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
......@@ -84,15 +69,14 @@ begin
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o
);
wb_err_o => wb_err_o);
wb_clk_process: process
begin
wb_clk <= '1';
wait for wb_clk_period/2;
wait for c_WB_CLK_PERIOD/2;
wb_clk <= '0';
wait for wb_clk_period/2;
wait for c_WB_CLK_PERIOD/2;
end process;
......@@ -100,11 +84,11 @@ begin
procedure rst is
begin
wait for wb_clk_period;
wait for c_WB_CLK_PERIOD;
wb_rst_i <= '1';
wait for wb_clk_period;
wait for c_WB_CLK_PERIOD;
wb_rst_i <= '0';
wait for wb_clk_period*25;
wait for c_WB_CLK_PERIOD*25;
end rst;
procedure read_wishbone(addr: STD_LOGIC_VECTOR(3 downto 0)) is
......@@ -114,7 +98,7 @@ begin
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_addr_i <= addr;
wait for wb_clk_period*3/2;
wait for c_WB_CLK_PERIOD*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
......@@ -130,7 +114,7 @@ begin
wb_cyc_i <= '1';
wb_addr_i <= addr;
wb_data_i <= data;
wait for wb_clk_period*3/2;
wait for c_WB_CLK_PERIOD*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
......@@ -172,11 +156,11 @@ begin
variable header_line_buffer : LINE;
begin
file_open(file_handler, log_path, WRITE_MODE);
file_open(file_handler, c_LOG_PATH, WRITE_MODE);
write(header_line_buffer, string'("Test ID"&sep&"Status"&sep&"Description"));
writeline(file_handler, header_line_buffer);
wait for 2*wb_clk_period;
wait for 2*c_WB_CLK_PERIOD;
rst;
GENERAL1_data <= (others => '0');
GENERAL2_data <= (others => '0');
......@@ -184,7 +168,7 @@ begin
GENERAL4_data <= (others => '0');
wait for 2*wb_clk_period;
wait for 2*c_WB_CLK_PERIOD;
read_wishbone(CTRL_addr);
assert32_to_file(wb_data_o, X"00000000","0x0","CTRL register initialization");
read_wishbone(STAT_addr);
......
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