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Conv TTL Blocking
Commit b7d1c1a8 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Project files deletion

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installation/V2/basic_trigger/project/_impact.cmd deleted 100644 → 0
View file @ 45b75c34
setMode -bs
setMode -bs
setMode -bs
setMode -bs
setCable -port auto
Identify -inferir
identifyMPM
assignFile -p 1 -file "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bit"
Program -p 1
Program -p 1
setMode -bs
setMode -bs
setMode -ss
setMode -sm
setMode -hw140
setMode -spi
setMode -acecf
setMode -acempm
setMode -pff
setMode -bs
saveProjectFile -file "/home/tstana/Projects/fmc-adc-100m14b4cha/hdl/spec/syn/leds/spec_leds.data//auto_project.ipf"
setMode -bs
deleteDevice -position 1
setMode -bs
setMode -ss
setMode -sm
setMode -hw140
setMode -spi
setMode -acecf
setMode -acempm
setMode -pff
installation/V2/basic_trigger/project/_impact.log deleted 100644 → 0
View file @ 45b75c34
iMPACT Version: 14.2
iMPACT log file Started on Fri Jan 18 18:25:24 2013
Welcome to iMPACT
iMPACT Version: 14.2
Project:/home/tstana/Projects/fmc-adc-100m14b4cha/hdl/spec/syn/leds/spec_leds.data//auto_project.ipf created.
// *** BATCH CMD : setMode -bs
GUI --- Auto connect to cable...
// *** BATCH CMD : setCable -port auto
INFO:iMPACT - Digilent Plugin: Plugin Version: 2.2.10
INFO:iMPACT - Digilent Plugin: no JTAG device was found.
AutoDetecting cable. Please wait.
PROGRESS_START - Starting Operation.
OS platform = i686.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin/xusbdfwu.hex = 1030.
File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1030.
Using libusb.
Kernel release = 3.2.0-36-generic-pae.
Max current requested during enumeration is 300 mA.
Type = 0x0005.
write (count, cmdBuffer, dataBuffer) failed 20000020.
Cable Type = 3, Revision = 0.
Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 2300.
File version of /opt/Xilinx/14.2/ISE_DS/ISE/data/xusb_xp2.hex = 2401.
Firmware hex file version = 2401.
Downloading /opt/Xilinx/14.2/ISE_DS/ISE/data/xusb_xp2.hex.
Downloaded firmware version = 2401.
PLD file version = 200Dh.
PLD version = 200Dh.
PROGRESS_END - End Operation.
Elapsed time = 0 sec.
Type = 0x0005.
ESN option: 000013C9ED3601.
Attempting to identify devices in the boundary-scan chain configuration...
INFO:iMPACT - Current time: 1/18/13 6:25 PM
// *** BATCH CMD : Identify -inferir
PROGRESS_START - Starting Operation.
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc6slx45t, Version : 3
INFO:iMPACT:1777 -
Reading /opt/Xilinx/14.2/ISE_DS/ISE/spartan6/data/xc6slx45t.bsd...
INFO:iMPACT:501 - '1': Added Device xc6slx45t successfully.
----------------------------------------------------------------------
done.
PROGRESS_END - End Operation.
Elapsed time = 0 sec.
// *** BATCH CMD : identifyMPM
// *** BATCH CMD : assignFile -p 1 -file"/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bit"
'1': Loading file'/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bit' ...
done.
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
UserID read from the bitstream file = 0xFFFFFFFF.
Data width read from the bitstream file = 1.
INFO:iMPACT:501 - '1': Added Device xc6slx45t successfully.
----------------------------------------------------------------------
INFO:iMPACT - Current time: 1/18/13 6:26 PM
// *** BATCH CMD : Program -p 1
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Programming device...
PROGRESS_START - Starting Operation.
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
'1': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 1
[4] GWE STATUS : 1
[5] GHIGH STATUS : 1
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 1
[9] MODE PIN M[0] : 1
[10] MODE PIN M[1] : 1
[11] RESERVED : 0
[12] INIT_B PIN : 1
[13] DONE PIN : 1
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1100 1110 1100
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT:188 - '1': Programming completed successfully.
LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '1': Checking done pin....done.
'1': Programmed successfully.
PROGRESS_END - End Operation.
Elapsed time = 4 sec.
INFO:iMPACT - Current time: 1/18/13 6:28 PM
Updating config file/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.bit...
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
// *** BATCH CMD : Program -p 1
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Programming device...
PROGRESS_START - Starting Operation.
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
'1': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 1
[4] GWE STATUS : 1
[5] GHIGH STATUS : 1
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 1
[9] MODE PIN M[0] : 1
[10] MODE PIN M[1] : 1
[11] RESERVED : 0
[12] INIT_B PIN : 1
[13] DONE PIN : 1
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1100 1110 1100
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT:188 - '1': Programming completed successfully.
LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '1': Checking done pin....done.
'1': Programmed successfully.
PROGRESS_END - End Operation.
Elapsed time = 4 sec.
Project:'/home/tstana/Projects/fmc-adc-100m14b4cha/hdl/spec/syn/leds/spec_leds.data//auto_project.ipf' created.
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setMode -ss
// *** BATCH CMD : setMode -sm
// *** BATCH CMD : setMode -hw140
// *** BATCH CMD : setMode -spi
// *** BATCH CMD : setMode -acecf
// *** BATCH CMD : setMode -acempm
// *** BATCH CMD : setMode -pff
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : saveProjectFile -file"/home/tstana/Projects/fmc-adc-100m14b4cha/hdl/spec/syn/leds/spec_leds.data//auto_project.ipf"
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : deleteDevice -position 1
// *** BATCH CMD : setMode -bs
// *** BATCH CMD : setMode -ss
// *** BATCH CMD : setMode -sm
// *** BATCH CMD : setMode -hw140
// *** BATCH CMD : setMode -spi
// *** BATCH CMD : setMode -acecf
// *** BATCH CMD : setMode -acempm
// *** BATCH CMD : setMode -pff
installation/V2/basic_trigger/project/_ngo/netlist.lst deleted 100644 → 0
View file @ 45b75c34
/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.ngc 1358530026
OK
installation/V2/basic_trigger/project/_xmsgs/bitgen.xmsgs deleted 100644 → 0
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
installation/V2/basic_trigger/project/_xmsgs/map.xmsgs deleted 100644 → 0
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
</messages>
installation/V2/basic_trigger/project/_xmsgs/ngdbuild.xmsgs deleted 100644 → 0
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
installation/V2/basic_trigger/project/_xmsgs/par.xmsgs deleted 100644 → 0
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
installation/V2/basic_trigger/project/_xmsgs/pn_parser.xmsgs deleted 100644 → 0
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/rtl/basic_trigger_v2_pkg.vhd&quot; into library work</arg>
</msg>
</messages>
installation/V2/basic_trigger/project/_xmsgs/trce.xmsgs deleted 100644 → 0
View file @ 45b75c34
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>
installation/V2/basic_trigger/project/_xmsgs/xst.xmsgs deleted 100644 → 0
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This source diff could not be displayed because it is too large. You can view the blob instead.
installation/V2/basic_trigger/project/basic_trigger_v2_top.bgn deleted 100644 → 0
View file @ 45b75c34
Release 14.2 - Bitgen P.28xd (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx45t.nph' in environment
/opt/Xilinx/14.2/ISE_DS/ISE/.
"basic_trigger_v2_top" is an NCD, version 3.2, device xc6slx45t, package
fgg484, speed -3
Opened constraints file basic_trigger_v2_top.pcf.
Fri Jan 18 18:28:12 2013
/opt/Xilinx/14.2/ISE_DS/ISE/bin/lin/unwrapped/bitgen -filter iseconfig/filter.filter -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 basic_trigger_v2_top.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 2** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No** |
+----------------------+----------------------+
| Reset_on_err | No** |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No** |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk** |
+----------------------+----------------------+
| sw_gwe_cycle | 5** |
+----------------------+----------------------+
| sw_gts_cycle | 4** |
+----------------------+----------------------+
| multipin_wakeup | No** |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No** |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| CrcCoverage | No* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| next_config_reboot | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | 0xFFFF |
+----------------------+----------------------+
| spi_buswidth | 1** |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from basic_trigger_v2_top.pcf.
Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "basic_trigger_v2_top.bit".
Bitstream generation is complete.
installation/V2/basic_trigger/project/basic_trigger_v2_top.bld deleted 100644 → 0
View file @ 45b75c34
Release 14.2 ngdbuild P.28xd (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.2/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -filter
iseconfig/filter.filter -intstyle ise -dd _ngo -nt timestamp -uc
/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/constraints/Blo
V2.ucf -p xc6slx45t-fgg484-3 basic_trigger_v2_top.ngc basic_trigger_v2_top.ngd
Reading NGO file
"/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_
trigger_v2_top.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file
"/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/constraints/Bl
oV2.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 109176 kilobytes
Writing NGD file "basic_trigger_v2_top.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "basic_trigger_v2_top.bld"...
installation/V2/basic_trigger/project/basic_trigger_v2_top.cmd_log deleted 100644 → 0
View file @ 45b75c34
xst -intstyle ise -filter "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/filter.filter" -ifn "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.xst" -ofn "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.syr"
ngdbuild -filter "iseconfig/filter.filter" -intstyle ise -dd _ngo -nt timestamp -uc /home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/constraints/BloV2.ucf -p xc6slx45t-fgg484-3 basic_trigger_v2_top.ngc basic_trigger_v2_top.ngd
map -filter "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/filter.filter" -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o basic_trigger_v2_top_map.ncd basic_trigger_v2_top.ngd basic_trigger_v2_top.pcf
par -filter "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/filter.filter" -w -intstyle ise -ol high -mt off basic_trigger_v2_top_map.ncd basic_trigger_v2_top.ncd basic_trigger_v2_top.pcf
trce -filter /home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/filter.filter -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml basic_trigger_v2_top.twx basic_trigger_v2_top.ncd -o basic_trigger_v2_top.twr basic_trigger_v2_top.pcf
bitgen -filter "iseconfig/filter.filter" -intstyle ise -f basic_trigger_v2_top.ut basic_trigger_v2_top.ncd
xst -intstyle ise -filter "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/filter.filter" -ifn "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.xst" -ofn "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/basic_trigger_v2_top.syr"
ngdbuild -filter "iseconfig/filter.filter" -intstyle ise -dd _ngo -nt timestamp -uc /home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/constraints/BloV2.ucf -p xc6slx45t-fgg484-3 basic_trigger_v2_top.ngc basic_trigger_v2_top.ngd
map -filter "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/filter.filter" -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o basic_trigger_v2_top_map.ncd basic_trigger_v2_top.ngd basic_trigger_v2_top.pcf
par -filter "/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/filter.filter" -w -intstyle ise -ol high -mt off basic_trigger_v2_top_map.ncd basic_trigger_v2_top.ncd basic_trigger_v2_top.pcf
trce -filter /home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/filter.filter -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml basic_trigger_v2_top.twx basic_trigger_v2_top.ncd -o basic_trigger_v2_top.twr basic_trigger_v2_top.pcf
bitgen -filter "iseconfig/filter.filter" -intstyle ise -f basic_trigger_v2_top.ut basic_trigger_v2_top.ncd
installation/V2/basic_trigger/project/basic_trigger_v2_top.drc deleted 100644 → 0
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Release 14.2 Drc P.28xd (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Fri Jan 18 18:28:12 2013
drc -z basic_trigger_v2_top.ncd basic_trigger_v2_top.pcf
DRC detected 0 errors and 0 warnings.
installation/V2/basic_trigger/project/basic_trigger_v2_top.ncd deleted 100644 → 0
View file @ 45b75c34
This source diff could not be displayed because it is too large. You can view the blob instead.
installation/V2/basic_trigger/project/basic_trigger_v2_top.ngc deleted 100644 → 0
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This source diff could not be displayed because it is too large. You can view the blob instead.
installation/V2/basic_trigger/project/basic_trigger_v2_top.par deleted 100644 → 0
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Release 14.2 par P.28xd (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
tstana-unit:: Fri Jan 18 18:27:40 2013
par -filter
/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconf
ig/filter.filter -w -intstyle ise -ol high -mt off basic_trigger_v2_top_map.ncd
basic_trigger_v2_top.ncd basic_trigger_v2_top.pcf
Constraints file: basic_trigger_v2_top.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment /opt/Xilinx/14.2/ISE_DS/ISE/.
"basic_trigger_v2_top" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.22 2012-07-09".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 283 out of 54,576 1%
Number used as Flip Flops: 283
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 648 out of 27,288 2%
Number used as logic: 625 out of 27,288 2%
Number using O6 output only: 341
Number using O5 output only: 181
Number using O5 and O6: 103
Number used as ROM: 0
Number used as Memory: 8 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 8
Number using O6 output only: 8
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 15
Number with same-slice register load: 3
Number with same-slice carry load: 12
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 220 out of 6,822 3%
Nummber of MUXCYs used: 416 out of 13,644 3%
Number of LUT Flip Flop pairs used: 678
Number with an unused Flip Flop: 402 out of 678 59%
Number with an unused LUT: 30 out of 678 4%
Number of fully used LUT-FF pairs: 246 out of 678 36%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 65 out of 296 21%
Number of LOCed IOBs: 65 out of 65 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 11 secs
Finished initial Timing Analysis. REAL time: 11 secs
Starting Router
Phase 1 : 2114 unrouted; REAL time: 12 secs
Phase 2 : 1658 unrouted; REAL time: 14 secs
Phase 3 : 318 unrouted; REAL time: 17 secs
Phase 4 : 318 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 19 secs
Updating file: basic_trigger_v2_top.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Total REAL time to Router completion: 20 secs
Total CPU time to Router completion: 13 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| s_clk_200m | BUFGMUX_X2Y2| No | 104 | 0.061 | 1.274 |
+---------------------+--------------+------+------+------------+-------------+
| CLK20_VCXO_BUFGP | BUFGMUX_X3Y7| No | 13 | 0.010 | 1.250 |
+---------------------+--------------+------+------+------------+-------------+
| s_clk_125m_i_BUFG | BUFGMUX_X2Y3| No | 5 | 0.021 | 1.267 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_clk_i = PERIOD TIMEGRP "CLK20_VCXO" 20 | SETUP | 46.865ns| 3.135ns| 0| 0
MHz HIGH 50% | HOLD | 0.439ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 20 secs
Total CPU time to PAR completion: 14 secs
Peak Memory Usage: 232 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
Writing design to file basic_trigger_v2_top.ncd
PAR done!
installation/V2/basic_trigger/project/basic_trigger_v2_top.pcf deleted 100644 → 0
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//! **************************************************************************
// Written by: Map P.28xd on Fri Jan 18 18:27:36 2013
//! **************************************************************************
SCHEMATIC START;
COMP "PULSE_REAR_LED<1>" LOCATE = SITE "AB17" LEVEL 1;
COMP "PULSE_REAR_LED<2>" LOCATE = SITE "AB19" LEVEL 1;
COMP "PULSE_REAR_LED<3>" LOCATE = SITE "AA16" LEVEL 1;
COMP "PULSE_REAR_LED<4>" LOCATE = SITE "AA18" LEVEL 1;
COMP "PULSE_REAR_LED<5>" LOCATE = SITE "AB16" LEVEL 1;
COMP "PULSE_REAR_LED<6>" LOCATE = SITE "AB18" LEVEL 1;
COMP "MR_N" LOCATE = SITE "T22" LEVEL 1;
COMP "LED_WR_OWNADDR_I2C" LOCATE = SITE "N15" LEVEL 1;
COMP "FPGA_TRIG_TTL_OE" LOCATE = SITE "N3" LEVEL 1;
COMP "CLK20_VCXO" LOCATE = SITE "E16" LEVEL 1;
COMP "PULSE_FRONT_LED_N<1>" LOCATE = SITE "H5" LEVEL 1;
COMP "PULSE_FRONT_LED_N<2>" LOCATE = SITE "J6" LEVEL 1;
COMP "PULSE_FRONT_LED_N<3>" LOCATE = SITE "K6" LEVEL 1;
COMP "PULSE_FRONT_LED_N<4>" LOCATE = SITE "K5" LEVEL 1;
COMP "PULSE_FRONT_LED_N<5>" LOCATE = SITE "M7" LEVEL 1;
COMP "PULSE_FRONT_LED_N<6>" LOCATE = SITE "M6" LEVEL 1;
COMP "RST_N" LOCATE = SITE "N20" LEVEL 1;
COMP "LED_MULTICAST_2_0" LOCATE = SITE "P16" LEVEL 1;
COMP "LED_MULTICAST_3_1" LOCATE = SITE "P17" LEVEL 1;
COMP "FPGA_CLK_N" LOCATE = SITE "G11" LEVEL 1;
COMP "FPGA_CLK_P" LOCATE = SITE "H12" LEVEL 1;
COMP "LED_WR_LINK_SYSERROR" LOCATE = SITE "R15" LEVEL 1;
COMP "FPGA_INPUT_TTL_N<1>" LOCATE = SITE "T2" LEVEL 1;
COMP "FPGA_INPUT_TTL_N<2>" LOCATE = SITE "U3" LEVEL 1;
COMP "FPGA_INPUT_TTL_N<3>" LOCATE = SITE "V5" LEVEL 1;
COMP "FPGA_INPUT_TTL_N<4>" LOCATE = SITE "W4" LEVEL 1;
COMP "FPGA_INPUT_TTL_N<5>" LOCATE = SITE "T6" LEVEL 1;
COMP "FPGA_INPUT_TTL_N<6>" LOCATE = SITE "T3" LEVEL 1;
COMP "FPGA_OUT_TTL<1>" LOCATE = SITE "C1" LEVEL 1;
COMP "FPGA_OUT_TTL<2>" LOCATE = SITE "F2" LEVEL 1;
COMP "FPGA_OUT_TTL<3>" LOCATE = SITE "F5" LEVEL 1;
COMP "FPGA_OUT_TTL<4>" LOCATE = SITE "H4" LEVEL 1;
COMP "FPGA_OUT_TTL<5>" LOCATE = SITE "J4" LEVEL 1;
COMP "FPGA_OUT_TTL<6>" LOCATE = SITE "H2" LEVEL 1;
COMP "LED_WR_OK_SYSPW" LOCATE = SITE "R16" LEVEL 1;
COMP "FPGA_BLO_IN<1>" LOCATE = SITE "Y9" LEVEL 1;
COMP "FPGA_BLO_IN<2>" LOCATE = SITE "AA10" LEVEL 1;
COMP "FPGA_BLO_IN<3>" LOCATE = SITE "W12" LEVEL 1;
COMP "FPGA_BLO_IN<4>" LOCATE = SITE "AA6" LEVEL 1;
COMP "FPGA_BLO_IN<5>" LOCATE = SITE "Y7" LEVEL 1;
COMP "FPGA_BLO_IN<6>" LOCATE = SITE "AA8" LEVEL 1;
COMP "LED_CTRL0" LOCATE = SITE "M18" LEVEL 1;
COMP "LED_CTRL1" LOCATE = SITE "M17" LEVEL 1;
COMP "LED_WR_GMT_TTL_TTLN" LOCATE = SITE "N16" LEVEL 1;
COMP "LED_CTRL0_OEN" LOCATE = SITE "T20" LEVEL 1;
COMP "LED_CTRL1_OEN" LOCATE = SITE "U19" LEVEL 1;
COMP "INV_IN_N<1>" LOCATE = SITE "V2" LEVEL 1;
COMP "INV_IN_N<2>" LOCATE = SITE "W3" LEVEL 1;
COMP "INV_IN_N<3>" LOCATE = SITE "Y2" LEVEL 1;
COMP "INV_IN_N<4>" LOCATE = SITE "AA2" LEVEL 1;
COMP "EXTRA_SWITCH<1>" LOCATE = SITE "F22" LEVEL 1;
COMP "TTL_or_INV_TTL_N" LOCATE = SITE "L22" LEVEL 1;
COMP "FPGA_OE" LOCATE = SITE "R3" LEVEL 1;
COMP "INV_OUT<1>" LOCATE = SITE "J3" LEVEL 1;
COMP "INV_OUT<2>" LOCATE = SITE "L3" LEVEL 1;
COMP "INV_OUT<3>" LOCATE = SITE "M3" LEVEL 1;
COMP "INV_OUT<4>" LOCATE = SITE "P2" LEVEL 1;
COMP "FPGA_BLO_OE" LOCATE = SITE "P5" LEVEL 1;
COMP "FPGA_TRIG_BLO<1>" LOCATE = SITE "W9" LEVEL 1;
COMP "FPGA_TRIG_BLO<2>" LOCATE = SITE "T10" LEVEL 1;
COMP "FPGA_TRIG_BLO<3>" LOCATE = SITE "V7" LEVEL 1;
COMP "FPGA_TRIG_BLO<4>" LOCATE = SITE "U9" LEVEL 1;
COMP "FPGA_TRIG_BLO<5>" LOCATE = SITE "T8" LEVEL 1;
COMP "FPGA_TRIG_BLO<6>" LOCATE = SITE "R9" LEVEL 1;
COMP "FPGA_INV_OE" LOCATE = SITE "P6" LEVEL 1;
TIMEGRP CLK20_VCXO = BEL "inst_bicolor_led_ctrl/intensity_ctrl_cnt_14" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_13" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_12" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_11" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_10" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_9" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_8" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_7" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_6" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_5" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_4" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_3" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_2" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_1" BEL
"inst_bicolor_led_ctrl/intensity_ctrl_cnt_0" BEL
"inst_bicolor_led_ctrl/refresh_rate" BEL
"inst_bicolor_led_ctrl/line_oen_cnt_0" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_14" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_11" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_9" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_10" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_4" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_3" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_1" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_0" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_2" BEL
"inst_bicolor_led_ctrl/intensity_ctrl" BEL
"inst_bicolor_led_ctrl/line_ctrl" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_12" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_13" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_8" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_6" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_5" BEL
"inst_bicolor_led_ctrl/refresh_rate_cnt_7" BEL
"CLK20_VCXO_BUFGP/BUFG";
TS_clk_i = PERIOD TIMEGRP "CLK20_VCXO" 20 MHz HIGH 50%;
SCHEMATIC END;
installation/V2/basic_trigger/project/basic_trigger_v2_top.prj deleted 100644 → 0
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vhdl work "../../../../hdl/ctdah_lib/rtl/gc_ff.vhd"
vhdl work "../../../../hdl/ctdah_lib/rtl/gc_simple_monostable.vhd"
vhdl work "../../../../hdl/ctdah_lib/rtl/gc_debouncer.vhd"
vhdl work "../../../../hdl/ctdah_lib/rtl/ctdah_pkg.vhd"
vhdl work "../../../../hdl/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"
vhdl work "../rtl/basic_trigger_v2_pkg.vhd"
vhdl work "../../../V1/basic_trigger/rtl/basic_trigger_core.vhd"
vhdl work "../../../../hdl/bicolor_led_ctrl/bicolor_led_ctrl.vhd"
vhdl work "../top/basic_trigger_v2_top.vhd"
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Release 14.2 - par P.28xd (lin)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Fri Jan 18 18:28:00 2013
All signals are completely routed.
installation/V2/basic_trigger/project/basic_trigger_v2_top.ut deleted 100644 → 0
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-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4
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set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn basic_trigger_v2_top.prj
-ofn basic_trigger_v2_top
-ofmt NGC
-p xc6slx45t-3-fgg484
-top basic_trigger_v2_top
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
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Release 14.2 Map P.28xd (lin)
Xilinx Map Application Log File for Design 'basic_trigger_v2_top'
Design Information
------------------
Command Line : map -filter
/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconf
ig/filter.filter -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high
-t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr
off -lc off -power off -o basic_trigger_v2_top_map.ncd basic_trigger_v2_top.ngd
basic_trigger_v2_top.pcf
Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Jan 18 18:27:14 2013
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 14 secs
Total CPU time at the beginning of Placer: 7 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:b89c691e) REAL time: 15 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:b89c691e) REAL time: 15 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:b89c691e) REAL time: 15 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:1de01564) REAL time: 19 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:1de01564) REAL time: 19 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:1de01564) REAL time: 19 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:1de01564) REAL time: 19 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:1de01564) REAL time: 19 secs
Phase 9.8 Global Placement
..........................
................
Phase 9.8 Global Placement (Checksum:a13484f3) REAL time: 20 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:a13484f3) REAL time: 20 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:db6c50a6) REAL time: 20 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:db6c50a6) REAL time: 20 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:9063e27e) REAL time: 20 secs
Total REAL time to Placer completion: 21 secs
Total CPU time to Placer completion: 14 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 283 out of 54,576 1%
Number used as Flip Flops: 283
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 648 out of 27,288 2%
Number used as logic: 625 out of 27,288 2%
Number using O6 output only: 341
Number using O5 output only: 181
Number using O5 and O6: 103
Number used as ROM: 0
Number used as Memory: 8 out of 6,408 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 8
Number using O6 output only: 8
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 15
Number with same-slice register load: 3
Number with same-slice carry load: 12
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 220 out of 6,822 3%
Nummber of MUXCYs used: 416 out of 13,644 3%
Number of LUT Flip Flop pairs used: 678
Number with an unused Flip Flop: 402 out of 678 59%
Number with an unused LUT: 30 out of 678 4%
Number of fully used LUT-FF pairs: 246 out of 678 36%
Number of unique control sets: 19
Number of slice register sites lost
to control set restrictions: 29 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 65 out of 296 21%
Number of LOCed IOBs: 65 out of 65 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of GTPA1_DUALs: 0 out of 2 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.83
Peak Memory Usage: 286 MB
Total REAL time to MAP completion: 22 secs
Total CPU time to MAP completion: 15 secs
Mapping completed.
See MAP report file "basic_trigger_v2_top_map.mrp" for details.
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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin" product="ISE" version="14.2">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
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</table>
<item stringID="User_EnvOs" value="OS Information">
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<table stringID="User_EnvCpu">
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<task stringID="NGDBUILD_OPTION_SUMMARY">
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installation/V2/basic_trigger/project/basic_trigger_v2_top_summary.html 0 → 100644
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>basic_trigger_v2_top Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>basic_trigger_v2.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>basic_trigger_v2_top</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/01/2013 - 16:31:48</center>
</BODY></HTML>
\ No newline at end of file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="4">
<CmdHistory>
</CmdHistory>
</DesignSummary>
installation/V2/basic_trigger/project/iseconfig/basic_trigger_v2.projectmgr
View file @ b7d1c1a8
......@@ -30,13 +30,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
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<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001a6000000010000000100000000000000000000000064ffffffff000000810000000000000001000001a60000000100000000</ViewHeaderState>
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<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
......@@ -45,7 +45,7 @@
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>basic_trigger_core.vhd</CurrentItem>
</ItemView>
......@@ -89,13 +89,13 @@
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</ClosedNodes>
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<SelectedItem>Design Summary/Reports</SelectedItem>
<SelectedItem>Configure Target Device</SelectedItem>
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......
installation/V2/basic_trigger/project/iseconfig/basic_trigger_v2_top.xreport
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<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2013-01-18T17:30:38</DateModified>
<DateModified>2013-02-01T16:31:48</DateModified>
<ModuleName>basic_trigger_v2_top</ModuleName>
<SummaryTimeStamp>2013-01-18T14:24:50</SummaryTimeStamp>
<SavedFilePath>/home/tstana/Projects/conv-ttl-blo/installation/V2/basic_trigger/project/iseconfig/basic_trigger_v2_top.xreport</SavedFilePath>
......
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Release 14.2 - WebTalk (P.28xd)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
WebTalk Summary
----------------
INFO:WebTalk:3 - WebTalk is disabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:7 - WebTalk User setting is OFF.
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