Corrected changes in start and stop detection. It works with ELMA crate :-)

e06b805e · gilsoriano · 930b94ac · e06b805e · e06b805e · e06b805e
Commit e06b805e authored Jun 13, 2012 by gilsoriano
3 changed files
--- a/hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_bit.vhd
--- a/hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
--- a/hdl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
+++ b/hdl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
@@ -78,12 +78,15 @@ ARCHITECTURE behavior OF i2c_slave_top_tb IS

   --Inputs
   signal sda_oen       : STD_LOGIC;
-   signal sda_i         : STD_LOGIC := '0';
+   signal sda_i         : STD_LOGIC := '1';
   signal sda_o         : STD_LOGIC;
   signal scl_oen       : STD_LOGIC;
-   signal scl_i         : STD_LOGIC := '0';
+   signal scl_i         : STD_LOGIC := '1';
+   signal scl_clk       : STD_LOGIC := '1';
   signal scl_o         : STD_LOGIC;

+   signal run_scl       : STD_LOGIC := '0';
+
   signal wb_clk       : STD_LOGIC := '0';
   signal wb_rst_i     : STD_LOGIC := '0';

@@ -185,12 +188,15 @@ BEGIN
 		wb_clk <= '0';
 		wait for wb_clk_period/2;
   end process;
- 
-   scl_i_process :process
+
+   scl_i <= '1' when run_scl = '0' else
+            scl_clk;
+
+   scl_clk_process :process
   begin
-      scl_i     <= '1';
+         scl_clk     <= '1';
         wait for scl_i_period/2;
-      scl_i     <= '0';
+         scl_clk     <= '0';
         wait for scl_i_period/2;
   end process;

@@ -208,21 +214,20 @@ BEGIN
 	
      procedure rst is
      begin
-            wait for wb_clk_period*2;
+            wait for wb_clk_period*10;
         wb_rst_i   <= '1';
-            wait for wb_clk_period*2;
+            wait for wb_clk_period*10;
         wb_rst_i   <= '0';
-            wait for wb_clk_period*2;
+            wait for wb_clk_period*10;
      end rst;

      procedure start is
      begin
-         wait until falling_edge(scl_i);
-         wait for scl_i_period/4;
-         sda_i  <= '1';
-         wait until rising_edge(scl_i);
+         sda_i     <= '1';
+         wait until rising_edge(scl_clk);
         wait for scl_i_period/4;
-         sda_i  <= '0';
+         sda_i     <= '0';
+         run_scl   <= '1';
      end start;


@@ -294,29 +299,14 @@ BEGIN
         sda_i <= '0';
      end read_SDA;

-      procedure read_last_SDA is
-      begin
-         for i in 0 to 7 loop
-            wait until falling_edge(scl_i);
-            wait for scl_i_period/4;
-            i2c_rcved_data(i) <= sda_o;
-         end loop;
-         wait until falling_edge(scl_i);
-         wait for scl_i_period/4;
-         sda_i <= '1';
-      end read_last_SDA;
-
-
      procedure pause is
      begin
         wait until falling_edge(scl_i);
         wait for scl_i_period/4;
-         sda_i  <= '0';
-         wait until rising_edge(scl_i);
-         wait for scl_i_period/4;
-         sda_i  <= '1';
-         wait until falling_edge(scl_i);
+         sda_i   <= '0';
+         run_scl <= '0';
         wait for scl_i_period/4;
+         sda_i   <= '1';
      end pause;

      -------------------------------------------------------------------------
@@ -598,7 +588,7 @@ begin
   -- Indirect i2c write    BAD ADDRESSING, IT MUST REPORT ONLY ERRORS
   -------------------------------------------------------------------------------   
   start;
-   addr_send("1011111");  -- MSB first
+   addr_send("1011101");  -- MSB first
   rd_wrn_send('0');
       read_NACK("NACK@01: ACK received. Bad I2C address found", "PASS -> Instruction byte NACKED");
   write_SDA(X"21"); -- inverted MSB
@@ -614,7 +604,6 @@ begin
   write_SDA("10000000"); -- inverted
      read_NACK("NACK@04:  ACK received. Wrong state in fsm", "PASS -> NACKed");
   pause;
-
   wait for 1000*wb_clk_period;


@@ -639,7 +628,7 @@ begin
   read_SDA;
   read_SDA;
   read_SDA;
-   read_last_SDA;
+   read_SDA;
   pause;

 wait;