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Theodor-Adrian Stana authored
Apart from this, a watchdog counter has been integrated into the i2c_slave VHDL module; it resets the slave FSM after one second if the master does not cycle the SCL line.
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Manifest.py | ||
clk_info_wb_slave.vhd | ||
incr_counter.vhd | ||
pts_regs.vhd | ||
pts_regs.wb | ||
pulse_cnt_wb.vhd | ||
pulse_cnt_wb.wb |