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Theodor-Adrian Stana authored
Apart from this, a watchdog counter has been integrated into the i2c_slave VHDL module; it resets the slave FSM after one second if the master does not cycle the SCL line.
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Makefile | ||
Manifest.py | ||
conv_ttl_blo_v2.bit | ||
conv_ttl_blo_v2.gise | ||
conv_ttl_blo_v2.xise | ||
run.tcl |