-
Theodor-Adrian Stana authored
Apart from this, a watchdog counter has been integrated into the i2c_slave VHDL module; it resets the slave FSM after one second if the master does not cycle the SCL line.
00387791
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
Manifest.py | ||
i2c_slave.vhd | ||
vme64x_i2c.vhd |