HDL roadmap
The development of HDL code has been divided into functional blocks. Each functional block consist of a /rtl folder, a /test one and a documentation explaining its behaviour.
HDL Specifications
The following document establish the HDL Specifications to be followed.
User Guide
We're working in the user guide that can be found in our repo.
HDL Blocks Status
HDL Block | HDL name | Tested | Synthesizable | Documented |
I2C Slave to Wishbone Master | i2c_slave_wb_master | YES | YES | YES |
Pulse Trigger Control | trigger | YES | YES | YES |
Multiboot manager | multiboot | Developing | YES | YES |
EEPROM manager | m25p32 | Developing | YES | NO |
SPI for block transfers | spi_master_multifield | YES | YES | YES |
White Rabbit | wr-core | YES | YES | NO |
Bitstreams Status
Version | Functionality | Mapped | Status | Test performed |
image0 | Basic pulse repetition | YES | Working | image 0 tests |
image1 | Complete but time-tagging | YES | Under development | image 1 tests |
image2 | Basic + Firmware upgradeable via I2C + I2C reports + WR time-tagging | NO | On the way |
Carlos Gil Soriano - August 22, 2012