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Conv TTL RS485
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Conv TTL RS485
Commits
c9e5c388
Commit
c9e5c388
authored
Dec 13, 2012
by
Carlos Gil Soriano
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Added bicolor LEDs to rs485 image 1
parent
06886f17
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4 changed files
with
746 additions
and
183 deletions
+746
-183
RS485.txt
RS485.txt
+122
-0
rs485.ucf
hdl/IMAGES/image1/constraints/V1/rs485.ucf
+194
-183
rs485_pkg.vhd
hdl/IMAGES/image1/rtl/rs485_pkg.vhd
+217
-0
rs485_top.vhd
hdl/IMAGES/image1/top/rs485_top.vhd
+213
-0
No files found.
RS485.txt
0 → 100644
View file @
c9e5c388
-------------------------------------------------------------------------------
SVEC schematics review 25.04.2012
-------------------------------------------------------------------------------
MEETING SUMMARY
+ DATE 18-07-2012
+ PLACE CERN Prevessin, Building 864, Room 1-A15
+ SUBJECT CONV-TTL-RS485 Review
+ SVN http://www.ohwr.org/projects/conv-ttl-rs485
+ REVISION 3
+ PARTICIPANTS:
Van der Bij, Erik EVB Erik.van.der.Bij@cern.ch
Cattin, Matthieu MC matthieu.cattin@cern.ch
Gil Soriano, Carlos CGS carlos.gil.soriano@cern.ch
+ SUMMARY
It is need to replace the front array of leds for the Dialight 568 ones.
===============================================================================
| ! : fatal |
| + : important |
| - : minor |
| ? : question |
| * : note |
| A : already |
===============================================================================
===============================================================================
SCHEMATICS
+ convTTLrs485_TOP.SchDoc
--+ PowerSupply.SchDoc
--+ FPGAbank.SchDoc
--+ Clocks&Monitor.SchDoc
--+ VME64xConn.SchDoc
--+ Communication.SchDoc
--+ FrontTTL.SchDoc
--+ FrontPanelLeds.SchDoc
--+ Input RS485.SchDoc
--+ Input Unit RS485.SchDoc
--+ Output RS485.SchDoc
--+ Output Unit RS485.SchDoc
--+ JTAG&Button.SchDoc
--> BOM
===============================================================================
--------------------------------------
PowerSupply.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
FPGAbank.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
Clocks&Monitor.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
VME64xConn.SchDoc
--------------------------------------
[CGS] - Blue text "P12V_VME" in P1D must be removed.
--------------------------------------
--------------------------------------
Communication.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
FrontTTL.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
FrontPanelLeds.SchDoc
--------------------------------------
[CGS] ! All the three arrays of red leds should be replaced by Dialigth 568.
--------------------------------------
--------------------------------------
Input RS485.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
Input Unit RS485.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
Output RS485.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
Output Unit RS485.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
JTAG&Button.SchDoc
--------------------------------------
--------------------------------------
--------------------------------------
BOM
--------------------------------------
--------------------------------------
===============================================================================
LAYOUT
===============================================================================
[CGS] + SW1 is not readable. It must include "TTL/INV_TTL_N"
[CGS] + SW2 should be moved away from SW1. Improve readability
[CGS] + Space up the fuses F1 and F2 for ease of replacement.
[CGS] - Move logo and webpage to the huge empty room in the lower part of the
board.
hdl/IMAGES/image1/constraints/V1/rs485.ucf
View file @
c9e5c388
This diff is collapsed.
Click to expand it.
hdl/IMAGES/image1/rtl/rs485_pkg.vhd
0 → 100644
View file @
c9e5c388
library
IEEE
;
library
work
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
IEEE
.
NUMERIC_STD
.
ALL
;
use
work
.
bicolor_led_ctrl_pkg
.
ALL
;
package
rs485_pkg
is
constant
c_NUMBER_OF_CHANNELS
:
NATURAL
:
=
6
;
constant
c_NB_ARRAY_LEDS
:
NATURAL
:
=
12
;
constant
c_LED_INTENSITY
:
STD_LOGIC_VECTOR
(
6
downto
0
)
:
=
"0011111"
;
--! Front array LEDs individual assignment
--! Pairings:
--! COLUMN t_led_state
--! 0 0 - 6
--! 1 1 - 7
--! 2 2 - 8
--! 3 3 - 9
--! 4 4 - 10
--! 5 5 - 11
constant
c_LED_NB_WR_ADDR
:
NATURAL
:
=
0
;
constant
c_LED_NB_WR_GMT
:
NATURAL
:
=
1
;
constant
c_LED_NB_WR_LINK
:
NATURAL
:
=
2
;
constant
c_LED_NB_WR_OK
:
NATURAL
:
=
3
;
constant
c_LED_NB_MULTICAST0
:
NATURAL
:
=
4
;
constant
c_LED_NB_MULTICAST1
:
NATURAL
:
=
5
;
constant
c_LED_NB_I2C
:
NATURAL
:
=
6
;
constant
c_LED_NB_TTL_N
:
NATURAL
:
=
7
;
constant
c_LED_NB_ERR
:
NATURAL
:
=
8
;
constant
c_LED_NB_PWR
:
NATURAL
:
=
9
;
constant
c_LED_NB_MULTICAST2
:
NATURAL
:
=
10
;
constant
c_LED_NB_MULTICAST3
:
NATURAL
:
=
11
;
constant
c_LED_COLOR_PWR
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_ERR
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_RED
;
constant
c_LED_COLOR_TTL_N
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_I2C
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_WR_OK
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_WR_LINK
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_WR_GMT
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_WR_ADDR
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_MULTICAST3
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_MULTICAST2
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_MULTICAST1
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
constant
c_LED_COLOR_MULTICAST0
:
STD_LOGIC_VECTOR
(
1
downto
0
)
:
=
c_LED_GREEN
;
type
t_leds_array_top
is
record
PWR
:
STD_LOGIC
;
ERR
:
STD_LOGIC
;
TTL_N
:
STD_LOGIC
;
I2C
:
STD_LOGIC
;
end
record
;
type
t_leds_array_middle
is
record
WR_OK
:
STD_LOGIC
;
WR_LINK
:
STD_LOGIC
;
WR_GMT
:
STD_LOGIC
;
WR_ADDR
:
STD_LOGIC
;
end
record
;
type
t_leds_array_bottom
is
record
MULTICAST
:
UNSIGNED
(
3
downto
0
);
end
record
;
type
t_leds_array
is
record
top
:
t_leds_array_top
;
middle
:
t_leds_array_middle
;
bottom
:
t_leds_array_bottom
;
end
record
;
type
t_led_state
is
record
STATE
:
STD_LOGIC_VECTOR
(
1
downto
0
);
end
record
;
type
t_led_state_array
is
array
(
natural
range
<>
)
of
t_led_state
;
-- constant c_leds_array_top_default : t_leds_array_top := (PWR => '0',
-- ERR => '0',
-- TTL_N => '0',
-- I2C => '0');
--
-- constant c_leds_array_middle_default : t_leds_array_middle := (WR_OK => '0',
-- WR_LINK => '0',
-- WR_GMT => '0',
-- WR_ADDR => '0');
--
-- constant c_leds_array_bottom_default : t_leds_array_bottom := (MULTICAST
-- => (others => '0'));
constant
c_NB_COLUMN
:
NATURAL
:
=
6
;
constant
c_NB_LINE
:
NATURAL
:
=
6
;
component
bicolor_led_ctrl
is
generic
(
g_NB_COLUMN
:
NATURAL
:
=
c_NB_COLUMN
;
g_NB_LINE
:
NATURAL
:
=
c_NB_LINE
;
g_CLK_FREQ
:
NATURAL
:
=
20000000
;
-- in Hz
g_REFRESH_RATE
:
NATURAL
:
=
250
);
-- in Hz
port
(
rst_n_i
:
in
STD_LOGIC
;
clk_i
:
in
STD_LOGIC
;
led_intensity_i
:
in
STD_LOGIC_VECTOR
(
6
downto
0
);
led_state_i
:
in
STD_LOGIC_VECTOR
(
(
g_NB_LINE
*
g_NB_COLUMN
*
2
)
-
1
downto
0
);
column_o
:
out
STD_LOGIC_VECTOR
(
g_NB_COLUMN
-
1
downto
0
);
line_o
:
out
STD_LOGIC_VECTOR
(
g_NB_LINE
-
1
downto
0
);
line_oen_o
:
out
STD_LOGIC_VECTOR
(
g_NB_LINE
-
1
downto
0
));
end
component
;
component
image1_top
is
generic
(
g_NUMBER_OF_CHANNELS
:
NATURAL
:
=
6
);
port
(
FPGA_CLK_P
:
in
STD_LOGIC
;
--Using the 125MHz clock
FPGA_CLK_N
:
in
STD_LOGIC
;
led_pw_o
:
out
STD_LOGIC
;
led_err_o
:
out
STD_LOGIC
;
led_ttl_o
:
out
STD_LOGIC
;
led_o_front
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
led_o_rear
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
pulse_i_front
:
in
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
pulse_o_front
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
pulse_i_rear
:
in
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
pulse_o_rear
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
inv_i
:
in
STD_LOGIC_VECTOR
(
4
downto
1
);
inv_o
:
out
STD_LOGIC_VECTOR
(
4
downto
1
);
--! Lines for the i2c_slave
SCL_I
:
in
STD_LOGIC
;
SCL_O
:
out
STD_LOGIC
;
SCL_OE
:
out
STD_LOGIC
;
SDA_I
:
in
STD_LOGIC
;
SDA_O
:
out
STD_LOGIC
;
SDA_OE
:
out
STD_LOGIC
;
FPGA_GA
:
in
STD_LOGIC_VECTOR
(
4
downto
0
);
FPGA_GAP
:
in
STD_LOGIC
;
--! Pins of the SPI interface to write into the Flash memory
FPGA_PROM_CCLK
:
out
STD_LOGIC
;
FPGA_PROM_CSO_B_N
:
out
STD_LOGIC
;
FPGA_PROM_DIN
:
in
STD_LOGIC
;
FPGA_PROM_MOSI
:
out
STD_LOGIC
;
--! This LED will show the status of the PLL
led_link_up_o
:
out
STD_LOGIC
;
led_pps_o
:
out
STD_LOGIC
;
led_wr_ok_o
:
out
STD_LOGIC
;
--! RTM identifiers, should match with the expected values
--! TODO: add matching
fpga_o_en
:
out
STD_LOGIC
;
fpga_o_blo_en
:
out
STD_LOGIC
;
fpga_o_ttl_en
:
out
STD_LOGIC
;
fpga_o_inv_en
:
out
STD_LOGIC
;
level
:
in
STD_LOGIC
;
switch_i
:
in
STD_LOGIC
;
--! General enable
manual_rst_n_o
:
out
STD_LOGIC
;
--! It allows power sequencing of the
--! 24V rail after a security given
--! delay
FPGA_RTMM
:
in
STD_LOGIC_VECTOR
(
2
downto
0
);
FPGA_RTMP
:
in
STD_LOGIC_VECTOR
(
2
downto
0
));
end
component
;
function
f_LED_STATE
(
state
:
STD_LOGIC_VECTOR
(
1
downto
0
))
return
t_led_state
;
function
f_STD_LOGIC_VECTOR
(
led_state
:
t_led_state
)
return
STD_LOGIC_VECTOR
;
function
f_STD_LOGIC_VECTOR
(
led_state_array
:
t_led_state_array
)
return
STD_LOGIC_VECTOR
;
end
rs485_pkg
;
package
body
rs485_pkg
is
--! @brief Translation function from STD_LOGIC_VECTOR to t_led_state
--! @param state LED state in STD_LOGIC_VECTOR format
function
f_LED_STATE
(
state
:
STD_LOGIC_VECTOR
(
1
downto
0
))
return
t_led_state
is
variable
v_return
:
t_led_state
;
begin
v_return
.
STATE
(
0
)
:
=
state
(
0
);
v_return
.
STATE
(
1
)
:
=
state
(
1
);
return
v_return
;
end
f_LED_STATE
;
--! @brief Translation function from STD_LOGIC_VECTOR to
--! t_led_state
--! @param led_state_array LED state in STD_LOGIC_VECTOR format
function
f_STD_LOGIC_VECTOR
(
led_state
:
t_led_state
)
return
STD_LOGIC_VECTOR
is
variable
v_return
:
STD_LOGIC_VECTOR
(
1
downto
0
);
begin
v_return
(
0
)
:
=
led_state
.
STATE
(
0
);
v_return
(
1
)
:
=
led_state
.
STATE
(
1
);
return
v_return
;
end
f_STD_LOGIC_VECTOR
;
--! @brief Translation function from STD_LOGIC_VECTOR to
--! t_led_state_array
--! @param led_state_array LED array state in STD_LOGIC_VECTOR format
function
f_STD_LOGIC_VECTOR
(
led_state_array
:
t_led_state_array
)
return
STD_LOGIC_VECTOR
is
variable
v_return
:
STD_LOGIC_VECTOR
(
c_NB_COLUMN
*
c_NB_LINE
-
1
downto
0
);
variable
v_led_state_tmp
:
t_led_state
;
variable
v_led_state_slv_tmp
:
STD_LOGIC_VECTOR
(
1
downto
0
);
begin
for
i
in
0
to
c_NB_COLUMN
*
c_NB_LINE
-
1
loop
v_led_state_tmp
:
=
led_state_array
(
i
);
v_led_state_slv_tmp
:
=
f_STD_LOGIC_VECTOR
(
v_led_state_tmp
);
v_return
(
2
*
i
+
1
downto
2
*
i
)
:
=
v_led_state_slv_tmp
;
end
loop
;
return
v_return
;
end
f_STD_LOGIC_VECTOR
;
end
rs485_pkg
;
hdl/IMAGES/image1/top/rs485_top.vhd
0 → 100644
View file @
c9e5c388
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description:
--
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library
IEEE
;
library
work
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
IEEE
.
NUMERIC_STD
.
ALL
;
use
work
.
image1_pkg
.
ALL
;
use
work
.
rs485_pkg
.
ALL
;
use
work
.
bicolor_led_ctrl_pkg
.
ALL
;
entity
rs485_top
is
generic
(
g_NUMBER_OF_CHANNELS
:
NATURAL
:
=
work
.
rs485_pkg
.
c_NUMBER_OF_CHANNELS
);
port
(
FPGA_CLK_P
:
in
STD_LOGIC
;
FPGA_CLK_N
:
in
STD_LOGIC
;
CLK20_VCXO
:
in
STD_LOGIC
;
LED_CTRL0
:
out
STD_LOGIC
;
LED_CTRL0_OEN
:
out
STD_LOGIC
;
LED_CTRL1
:
out
STD_LOGIC
;
LED_CTRL1_OEN
:
out
STD_LOGIC
;
LED_MULTICAST_2_0
:
out
STD_LOGIC
;
LED_MULTICAST_3_1
:
out
STD_LOGIC
;
LED_WR_GMT_TTL_TTLN
:
out
STD_LOGIC
;
LED_WR_LINK_SYSERROR
:
out
STD_LOGIC
;
LED_WR_OK_SYSPW
:
out
STD_LOGIC
;
LED_WR_OWNADDR_I2C
:
out
STD_LOGIC
;
PULSE_FRONT_LED_N
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
PULSE_REAR_LED
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
FPGA_INPUT_TTL_N
:
in
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
FPGA_OUT_TTL
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
FPGA_RS485_INA_TTL
:
in
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
FPGA_RS485_INB_TTL
:
in
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
FPGA_TRIG_RTM
:
out
STD_LOGIC_VECTOR
(
g_NUMBER_OF_CHANNELS
downto
1
);
INV_IN_N
:
in
STD_LOGIC_VECTOR
(
4
downto
1
);
INV_OUT
:
out
STD_LOGIC_VECTOR
(
4
downto
1
);
SCL_I
:
in
STD_LOGIC
;
SCL_O
:
out
STD_LOGIC
;
SCL_OE
:
out
STD_LOGIC
;
SDA_I
:
in
STD_LOGIC
;
SDA_O
:
out
STD_LOGIC
;
SDA_OE
:
out
STD_LOGIC
;
FPGA_GA
:
in
STD_LOGIC_VECTOR
(
4
downto
0
);
FPGA_GAP
:
in
STD_LOGIC
;
FPGA_PROM_CCLK
:
out
STD_LOGIC
;
FPGA_PROM_CSO_B_N
:
out
STD_LOGIC
;
FPGA_PROM_DIN
:
in
STD_LOGIC
;
FPGA_PROM_MOSI
:
out
STD_LOGIC
;
FPGA_OE
:
out
STD_LOGIC
;
FPGA_RS485_OE
:
out
STD_LOGIC
;
FPGA_TRIG_TTL_OE
:
out
STD_LOGIC
;
FPGA_INV_OE
:
out
STD_LOGIC
;
TTL_or_INV_TTL_N
:
in
STD_LOGIC
;
RST
:
in
STD_LOGIC
;
FPGA_RTMM
:
in
STD_LOGIC_VECTOR
(
2
downto
0
);
FPGA_RTMP
:
in
STD_LOGIC_VECTOR
(
2
downto
0
));
end
rs485_top
;
architecture
Behavioral
of
rs485_top
is
--! TODO: connect to Matthieu's LEDs IP core
signal
s_leds_array_image1
:
t_leds_array
;
signal
s_led_state_array
:
t_led_state_array
(
c_NB_ARRAY_LEDS
-
1
downto
0
);
signal
s_pulse_i_rear
:
STD_LOGIC_VECTOR
(
6
downto
1
);
signal
s_rst_n
:
STD_LOGIC
:
=
'0'
;
begin
-- g_rs485_inputs: for i in 1 to 6 generate
-- begin
-- inst_125m_IBUFDS : IBUFDS
-- generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => TRUE)
-- port map (O => s_pulse_i_rear(i), I => FPGA_RS485_INA_TTL(i),
-- IB => FPGA_RS485_INB_TTL(i));
-- end generate;
inst_image1_top
:
image1_top
generic
map
(
g_NUMBER_OF_CHANNELS
=>
g_NUMBER_OF_CHANNELS
)
port
map
(
FPGA_CLK_P
=>
FPGA_CLK_P
,
FPGA_CLK_N
=>
FPGA_CLK_N
,
led_pw_o
=>
s_leds_array_image1
.
top
.
PWR
,
led_err_o
=>
s_leds_array_image1
.
top
.
ERR
,
led_ttl_o
=>
s_leds_array_image1
.
top
.
TTL_N
,
led_o_front
=>
PULSE_FRONT_LED_N
,
led_o_rear
=>
PULSE_REAR_LED
,
pulse_i_front
=>
FPGA_INPUT_TTL_N
,
pulse_o_front
=>
FPGA_OUT_TTL
,
pulse_i_rear
=>
FPGA_RS485_INA_TTL
,
pulse_o_rear
=>
FPGA_TRIG_RTM
,
inv_i
=>
INV_IN_N
,
inv_o
=>
INV_OUT
,
SCL_I
=>
SCL_I
,
SCL_O
=>
SCL_O
,
SCL_OE
=>
SCL_OE
,
SDA_I
=>
SDA_I
,
SDA_O
=>
SDA_O
,
SDA_OE
=>
SDA_OE
,
FPGA_GA
=>
FPGA_GA
,
FPGA_GAP
=>
FPGA_GAP
,
FPGA_PROM_CCLK
=>
FPGA_PROM_CCLK
,
FPGA_PROM_CSO_B_N
=>
FPGA_PROM_CSO_B_N
,
FPGA_PROM_DIN
=>
FPGA_PROM_DIN
,
FPGA_PROM_MOSI
=>
FPGA_PROM_MOSI
,
led_link_up_o
=>
s_leds_array_image1
.
middle
.
WR_LINK
,
led_pps_o
=>
s_leds_array_image1
.
middle
.
WR_GMT
,
led_wr_ok_o
=>
s_leds_array_image1
.
middle
.
WR_OK
,
fpga_o_en
=>
FPGA_OE
,
fpga_o_blo_en
=>
FPGA_RS485_OE
,
fpga_o_ttl_en
=>
FPGA_TRIG_TTL_OE
,
fpga_o_inv_en
=>
FPGA_INV_OE
,
level
=>
TTL_or_INV_TTL_N
,
switch_i
=>
RST
,
manual_rst_n_o
=>
open
,
--! We don't have MR_N in RS485
FPGA_RTMM
=>
FPGA_RTMM
,
FPGA_RTMP
=>
FPGA_RTMP
);
--! Here are organized in the same disposition as in the front panel.
--! Take a look to rs485_pkg.vhd for the correct order for
--! bicolor_led_ctrl
s_led_state_array
(
c_LED_NB_PWR
)
<=
f_LED_STATE
(
c_LED_COLOR_PWR
)
when
s_leds_array_image1
.
top
.
PWR
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_ERR
)
<=
f_LED_STATE
(
c_LED_COLOR_ERR
)
when
s_leds_array_image1
.
top
.
ERR
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_TTL_N
)
<=
f_LED_STATE
(
c_LED_COLOR_TTL_N
)
when
s_leds_array_image1
.
top
.
TTL_N
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_I2C
)
<=
f_LED_STATE
(
c_LED_COLOR_I2C
)
when
s_leds_array_image1
.
top
.
I2C
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_WR_OK
)
<=
f_LED_STATE
(
c_LED_COLOR_WR_OK
)
when
s_leds_array_image1
.
middle
.
WR_OK
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_WR_LINK
)
<=
f_LED_STATE
(
c_LED_COLOR_WR_LINK
)
when
s_leds_array_image1
.
middle
.
WR_LINK
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_WR_GMT
)
<=
f_LED_STATE
(
c_LED_COLOR_WR_GMT
)
when
s_leds_array_image1
.
middle
.
WR_GMT
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_WR_ADDR
)
<=
f_LED_STATE
(
c_LED_COLOR_WR_ADDR
)
when
s_leds_array_image1
.
middle
.
WR_ADDR
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_MULTICAST3
)
<=
f_LED_STATE
(
c_LED_COLOR_MULTICAST3
)
when
s_leds_array_image1
.
bottom
.
MULTICAST
(
3
)
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_MULTICAST2
)
<=
f_LED_STATE
(
c_LED_COLOR_MULTICAST2
)
when
s_leds_array_image1
.
bottom
.
MULTICAST
(
2
)
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_MULTICAST1
)
<=
f_LED_STATE
(
c_LED_COLOR_MULTICAST1
)
when
s_leds_array_image1
.
bottom
.
MULTICAST
(
1
)
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_led_state_array
(
c_LED_NB_MULTICAST0
)
<=
f_LED_STATE
(
c_LED_COLOR_MULTICAST0
)
when
s_leds_array_image1
.
bottom
.
MULTICAST
(
0
)
=
'1'
else
f_LED_STATE
(
c_LED_OFF
);
s_rst_n
<=
not
(
RST
);
inst_bicolor_led_ctrl
:
bicolor_led_ctrl
port
map
(
rst_n_i
=>
s_rst_n
,
clk_i
=>
CLK20_VCXO
,
led_intensity_i
=>
c_LED_INTENSITY
,
led_state_i
=>
f_STD_LOGIC_VECTOR
(
s_led_state_array
),
column_o
(
0
)
=>
LED_WR_OWNADDR_I2C
,
column_o
(
1
)
=>
LED_WR_GMT_TTL_TTLN
,
column_o
(
2
)
=>
LED_WR_LINK_SYSERROR
,
column_o
(
3
)
=>
LED_WR_OK_SYSPW
,
column_o
(
4
)
=>
LED_MULTICAST_2_0
,
column_o
(
5
)
=>
LED_MULTICAST_3_1
,
line_o
(
0
)
=>
LED_CTRL0
,
line_o
(
1
)
=>
LED_CTRL1
,
line_oen_o
(
0
)
=>
LED_CTRL0_OEN
,
line_oen_o
(
1
)
=>
LED_CTRL1_OEN
);
end
Behavioral
;
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