Add Manifest files in generated cores directories.

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@96 739e5516-d4a2-47df-ba96-5610c1fa693f

Add Manifest files in generated cores directories.
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@96 739e5516-d4a2-47df-ba96-5610c1fa693f
12cfb76f · mcattin · d7839242 · 12cfb76f · 12cfb76f · 12cfb76f
Commit 12cfb76f authored Jul 09, 2012 by mcattin
5 changed files
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
@@ -3,5 +3,9 @@ files = ["ddr3_ctrl.vhd",
         "ddr3_ctrl_wrapper.vhd",
         "ddr3_ctrl_pkg.vhd"]

-modules = {"local" : ["../ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl",
-                      "../ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl"]}
+modules = {"local" : ["../spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl",
+                      "../spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl",
+                      "../svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl",
+                      "../svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl",
+                      "../svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl",
+                      "../svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl"]}
--- a/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/Manifest.py
+++ b/hdl/spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl/Manifest.py
+files = ["ddr3_ctrl_bank3_32b_32b.vhd",
+         "iodrp_controller.vhd",
+         "iodrp_mcb_controller.vhd",
+         "mcb_raw_wrapper.vhd",
+         "mcb_soft_calibration_top.vhd",
+         "mcb_soft_calibration.vhd",
+         "memc3_infrastructure.vhd",
+         "memc3_wrapper.vhd"]
--- a/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/Manifest.py
+++ b/hdl/spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl/Manifest.py
+files = ["ddr3_ctrl_bank3_64b_32b.vhd",
+         "iodrp_controller.vhd",
+         "iodrp_mcb_controller.vhd",
+         "mcb_raw_wrapper.vhd",
+         "mcb_soft_calibration_top.vhd",
+         "mcb_soft_calibration.vhd",
+         "memc3_infrastructure.vhd",
+         "memc3_wrapper.vhd"]
--- a/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/Manifest.py
+++ b/hdl/svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl/Manifest.py
+files = ["ddr3_ctrl_bank4_64b_32b.vhd",
+         "iodrp_controller.vhd",
+         "iodrp_mcb_controller.vhd",
+         "mcb_raw_wrapper.vhd",
+         "mcb_soft_calibration_top.vhd",
+         "mcb_soft_calibration.vhd",
+         "memc4_infrastructure.vhd",
+         "memc4_wrapper.vhd"]
--- a/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/Manifest.py
+++ b/hdl/svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl/Manifest.py
+files = ["ddr3_ctrl_bank5_64b_32b.vhd",
+         "iodrp_controller.vhd",
+         "iodrp_mcb_controller.vhd",
+         "mcb_raw_wrapper.vhd",
+         "mcb_soft_calibration_top.vhd",
+         "mcb_soft_calibration.vhd",
+         "memc5_infrastructure.vhd",
+         "memc5_wrapper.vhd"]