Fix bug in wishbone interface.

Was not porperly generating the command strobe to ddr interface in case of wishbone block transfers.

Fix bug in wishbone interface.
Was not porperly generating the command strobe to ddr interface in case of wishbone block transfers.
26d0d907 · Matthieu Cattin · 46df8a79 · 26d0d907
Commit 26d0d907 authored Nov 30, 2012 by Matthieu Cattin
Hide whitespace changes
Inline Side-by-side

Showing with 2 additions and 2 deletions

ddr3_ctrl_wb.vhd hdl/rtl/ddr3_ctrl_wb.vhd +2 -2

No files found.
--- a/hdl/rtl/ddr3_ctrl_wb.vhd
+++ b/hdl/rtl/ddr3_ctrl_wb.vhd
@@ -261,8 +261,8 @@ begin
      else
        ddr_cmd_en_d <= ddr_cmd_en;
        if (((ddr_burst_cnt = c_DDR_BURST_LENGTH) or
-             --(wb_we_f_edge = '1') or
-             (wb_stb_f_edge = '1' and wb_cyc_d = '1')) and ddr_cmd_full_i = '0') and (ddr_cmd_en = '0')then
+             (wb_cyc_f_edge = '1' and wb_we_d = '1') or
+             (wb_stb_f_edge = '1' and wb_we_d = '0')) and ddr_cmd_full_i = '0') and (ddr_cmd_en = '0') then
          ddr_cmd_en <= '1';            -- might have problem if burst_cnt = BURST_LENGTH for more than 2 clk cycles
        else
          ddr_cmd_en <= '0';