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DDR3 controller for Spartan6
Commit 7496ea02 authored by Matthieu Cattin's avatar Matthieu Cattin
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Modify top Manifest for spec_bank3_64b_32b branch.

parent 8de0e83e
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hdl/rtl/Manifest.py
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......@@ -4,12 +4,5 @@ files = ["ddr3_ctrl.vhd",
"ddr3_ctrl_wrapper_pkg.vhd",
"ddr3_ctrl_pkg.vhd"]
modules = {"local" : ["../common/ip_cores/rtl",
"../spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl",
"../spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl",
"../vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl",
"../vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl"]}
modules = {"local" : ["../spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl"]}
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