ddr3_ctrl_wb: improve style.

adaeb417 · Tristan Gingold · edfed0ea · adaeb417
Commit adaeb417 authored Jul 25, 2019 by Tristan Gingold
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Showing with 4 additions and 2 deletions

ddr3_ctrl_wb.vhd hdl/rtl/ddr3_ctrl_wb.vhd +4 -2

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--- a/hdl/rtl/ddr3_ctrl_wb.vhd
+++ b/hdl/rtl/ddr3_ctrl_wb.vhd
@@ -224,7 +224,8 @@ begin
      else
        wb_addr_d <= wb_addr_i;
        if ((ddr_burst_cnt = 0 and wb_cyc_r_edge = '1' and wb_stb_valid = '1') or
-            (ddr_burst_cnt = to_unsigned(1, ddr_burst_cnt'length))) then
+            (ddr_burst_cnt = 1))
+        then
          ddr_cmd_byte_addr <= wb_addr_d(g_BYTE_ADDR_WIDTH-c_ADDR_SHIFT-1 downto 0) & addr_shift;
          ddr_cmd_instr     <= "00" & not(wb_we_d);
        end if;
@@ -244,7 +245,8 @@ begin
      else
        if (((ddr_burst_cnt = c_DDR_BURST_LENGTH) or
             (wb_cyc_f_edge = '1' and wb_we_d = '1') or
-             (wb_stb_f_edge = '1' and wb_we_d = '0')) and ddr_cmd_full_i = '0') then
+             (wb_stb_f_edge = '1' and wb_we_d = '0')) and ddr_cmd_full_i = '0')
+        then
          ddr_cmd_en <= '1';  -- might have problem if burst_cnt = BURST_LENGTH for more than 2 clk cycles
        else
          ddr_cmd_en <= '0';