Commit d1ab2bbb authored by mcattin's avatar mcattin

Fix port name mismatch after core upgrade.

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@98 739e5516-d4a2-47df-ba96-5610c1fa693f
parent 17dc26bb
......@@ -240,7 +240,7 @@ begin
)
port map (
c3_sys_clk => clk_i,
c3_sys_rst_n => rst_n_i,
c3_sys_rst_i => rst_n_i,
c3_clk0 => open,
c3_rst0 => open,
c3_calib_done => calib_done_o,
......@@ -335,7 +335,7 @@ begin
)
port map (
c3_sys_clk => clk_i,
c3_sys_rst_n => rst_n_i,
c3_sys_rst_i => rst_n_i,
c3_clk0 => open,
c3_rst0 => open,
c3_calib_done => calib_done_o,
......
......@@ -83,7 +83,7 @@ package ddr3_ctrl_wrapper_pkg is
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
......@@ -175,7 +175,7 @@ package ddr3_ctrl_wrapper_pkg is
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
......
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