ddr3_ctrl_wb: remove unused signals.

d78b2b5c · Tristan Gingold · bb5b8f75 · d78b2b5c
Commit d78b2b5c authored Jul 25, 2019 by Tristan Gingold
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ddr3_ctrl_wb.vhd hdl/rtl/ddr3_ctrl_wb.vhd +0 -16

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--- a/hdl/rtl/ddr3_ctrl_wb.vhd
+++ b/hdl/rtl/ddr3_ctrl_wb.vhd
@@ -132,8 +132,6 @@ end entity ddr3_ctrl_wb;
 --! Architecure declaration for ddr3_ctrl_wb
 --==============================================================================
 architecture rtl of ddr3_ctrl_wb is
-
-
  ------------------------------------------------------------------------------
  -- Constants declaration
  ------------------------------------------------------------------------------
@@ -143,12 +141,6 @@ architecture rtl of ddr3_ctrl_wb is

  constant c_ADDR_SHIFT : integer := log2_ceil(g_DATA_PORT_SIZE/8);

-  ------------------------------------------------------------------------------
-  -- Types declaration
-  ------------------------------------------------------------------------------
-  --type t_wb_fsm_states is (WB_IDLE, WB_WRITE, WB_READ_REQ, WB_READ_WAIT,
-  --                         WB_READ_ACK, WB_READ_REQ_ACK);
-
  ------------------------------------------------------------------------------
  -- Signals declaration
  ------------------------------------------------------------------------------
@@ -160,13 +152,11 @@ architecture rtl of ddr3_ctrl_wb is
  signal wb_stb_d      : std_logic;
  signal wb_stb_f_edge : std_logic;
  signal wb_we_d       : std_logic;
-  signal wb_we_f_edge  : std_logic;
  signal wb_addr_d     : std_logic_vector(31 downto 0);

  signal ddr_burst_cnt     : unsigned(5 downto 0);
  signal ddr_cmd_en        : std_logic;
  signal ddr_cmd_en_d      : std_logic;
-  signal ddr_cmd_en_r_edge : std_logic;
  signal ddr_cmd_instr     : std_logic_vector(2 downto 0);
  signal ddr_cmd_bl        : std_logic_vector(5 downto 0);
  signal ddr_cmd_byte_addr : std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
@@ -181,8 +171,6 @@ architecture rtl of ddr3_ctrl_wb is
 --! Architecure begin
 --==============================================================================
 begin
-
-
  ------------------------------------------------------------------------------
  -- Wishbone interface
  ------------------------------------------------------------------------------
@@ -214,7 +202,6 @@ begin
  wb_cyc_f_edge <= not(wb_cyc_i) and wb_cyc_d;
  wb_cyc_r_edge <= wb_cyc_i and not(wb_cyc_d);
  wb_stb_f_edge <= not(wb_stb_valid) and wb_stb_d;
-  wb_we_f_edge  <= not(wb_we_i) and wb_we_d;

  -- Data inputs
  p_ddr_inputs : process (wb_clk_i)
@@ -278,9 +265,6 @@ begin
    end if;
  end process p_ddr_cmd_en;

-  -- Command enable rising edge detection
-  ddr_cmd_en_r_edge <= ddr_cmd_en and not(ddr_cmd_en_d);
-
  -- Burst counter
  p_ddr_burst_cnt : process (wb_clk_i)
  begin