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DDR3 controller for Spartan6
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DDR3 controller for Spartan6
Commits
f2c4142a
Commit
f2c4142a
authored
Nov 23, 2018
by
Dimitris Lampridis
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hdl: introduce option for active high reset to simplify reset logic
parent
94a664ed
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3 changed files
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17 additions
and
10 deletions
+17
-10
ddr3_ctrl.vhd
hdl/rtl/ddr3_ctrl.vhd
+4
-1
ddr3_ctrl_pkg.vhd
hdl/rtl/ddr3_ctrl_pkg.vhd
+3
-1
ddr3_ctrl_wrapper.vhd
hdl/rtl/ddr3_ctrl_wrapper.vhd
+10
-8
No files found.
hdl/rtl/ddr3_ctrl.vhd
View file @
f2c4142a
...
...
@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-07-13
-- Last update: 201
6-05-19
-- Last update: 201
8-11-12
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Wishbone to DDR3 interface for Xilinx FPGA with MCB (Memory
...
...
@@ -66,6 +66,8 @@ use IEEE.NUMERIC_STD.all;
entity
ddr3_ctrl
is
generic
(
--! Select between active-low (1) and active-high (0) reset
g_RST_ACT_LOW
:
integer
:
=
1
;
--! Bank and port size selection
g_BANK_PORT_SELECT
:
string
:
=
"SPEC_BANK3_32B_32B"
;
--! Core's clock period in ps
...
...
@@ -565,6 +567,7 @@ begin
------------------------------------------------------------------------------
cmp_ddr3_ctrl_wrapper
:
ddr3_ctrl_wrapper
generic
map
(
g_RST_ACT_LOW
=>
g_RST_ACT_LOW
,
g_BANK_PORT_SELECT
=>
g_BANK_PORT_SELECT
,
g_MEMCLK_PERIOD
=>
g_MEMCLK_PERIOD
,
g_CALIB_SOFT_IP
=>
g_CALIB_SOFT_IP
,
...
...
hdl/rtl/ddr3_ctrl_pkg.vhd
View file @
f2c4142a
...
...
@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-08-12
-- Last update: 201
6-05-19
-- Last update: 201
8-11-12
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Contains DDR3 controller core top level component declaration.
...
...
@@ -70,6 +70,8 @@ package ddr3_ctrl_pkg is
--==============================================================================
component
ddr3_ctrl
generic
(
--! Select between active-low (1) and active-high (0) reset
g_RST_ACT_LOW
:
integer
:
=
1
;
--! Bank and port size selection
g_BANK_PORT_SELECT
:
string
:
=
"BANK3_32B_32B"
;
--! Core's clock period in ps
...
...
hdl/rtl/ddr3_ctrl_wrapper.vhd
View file @
f2c4142a
...
...
@@ -51,6 +51,8 @@ use work.ddr3_ctrl_wrapper_pkg.all;
entity
ddr3_ctrl_wrapper
is
generic
(
--! Select between active-low (1) and active-high (0) reset
g_RST_ACT_LOW
:
integer
:
=
1
;
--! Bank and port size selection
g_BANK_PORT_SELECT
:
string
:
=
"SPEC_BANK3_32B_32B"
;
--! Core's clock period in ps
...
...
@@ -238,7 +240,7 @@ begin
C3_P1_MASK_SIZE
=>
4
,
C3_P1_DATA_PORT_SIZE
=>
32
,
C3_MEMCLK_PERIOD
=>
g_MEMCLK_PERIOD
,
C3_RST_ACT_LOW
=>
1
,
-- Active low
C3_RST_ACT_LOW
=>
g_RST_ACT_LOW
,
C3_CALIB_SOFT_IP
=>
g_CALIB_SOFT_IP
,
C3_MEM_ADDR_ORDER
=>
g_MEM_ADDR_ORDER
,
C3_NUM_DQ_PINS
=>
g_NUM_DQ_PINS
,
...
...
@@ -333,7 +335,7 @@ begin
C3_P1_MASK_SIZE
=>
4
,
C3_P1_DATA_PORT_SIZE
=>
32
,
C3_MEMCLK_PERIOD
=>
g_MEMCLK_PERIOD
,
C3_RST_ACT_LOW
=>
1
,
-- Active low
C3_RST_ACT_LOW
=>
g_RST_ACT_LOW
,
C3_CALIB_SOFT_IP
=>
g_CALIB_SOFT_IP
,
C3_MEM_ADDR_ORDER
=>
g_MEM_ADDR_ORDER
,
C3_NUM_DQ_PINS
=>
g_NUM_DQ_PINS
,
...
...
@@ -432,7 +434,7 @@ begin
C4_P1_MASK_SIZE
=>
4
,
C4_P1_DATA_PORT_SIZE
=>
32
,
C4_MEMCLK_PERIOD
=>
g_MEMCLK_PERIOD
,
C4_RST_ACT_LOW
=>
1
,
-- Active low
C4_RST_ACT_LOW
=>
g_RST_ACT_LOW
,
C4_CALIB_SOFT_IP
=>
g_CALIB_SOFT_IP
,
C4_MEM_ADDR_ORDER
=>
g_MEM_ADDR_ORDER
,
C4_NUM_DQ_PINS
=>
g_NUM_DQ_PINS
,
...
...
@@ -527,7 +529,7 @@ begin
C4_P1_MASK_SIZE
=>
4
,
C4_P1_DATA_PORT_SIZE
=>
32
,
C4_MEMCLK_PERIOD
=>
g_MEMCLK_PERIOD
,
C4_RST_ACT_LOW
=>
1
,
-- Active low
C4_RST_ACT_LOW
=>
g_RST_ACT_LOW
,
C4_CALIB_SOFT_IP
=>
g_CALIB_SOFT_IP
,
C4_MEM_ADDR_ORDER
=>
g_MEM_ADDR_ORDER
,
C4_NUM_DQ_PINS
=>
g_NUM_DQ_PINS
,
...
...
@@ -622,7 +624,7 @@ begin
C5_P1_MASK_SIZE
=>
4
,
C5_P1_DATA_PORT_SIZE
=>
32
,
C5_MEMCLK_PERIOD
=>
g_MEMCLK_PERIOD
,
C5_RST_ACT_LOW
=>
1
,
-- Active low
C5_RST_ACT_LOW
=>
g_RST_ACT_LOW
,
C5_CALIB_SOFT_IP
=>
g_CALIB_SOFT_IP
,
C5_MEM_ADDR_ORDER
=>
g_MEM_ADDR_ORDER
,
C5_NUM_DQ_PINS
=>
g_NUM_DQ_PINS
,
...
...
@@ -717,7 +719,7 @@ begin
C5_P1_MASK_SIZE
=>
4
,
C5_P1_DATA_PORT_SIZE
=>
32
,
C5_MEMCLK_PERIOD
=>
g_MEMCLK_PERIOD
,
C5_RST_ACT_LOW
=>
1
,
-- Active low
C5_RST_ACT_LOW
=>
g_RST_ACT_LOW
,
C5_CALIB_SOFT_IP
=>
g_CALIB_SOFT_IP
,
C5_MEM_ADDR_ORDER
=>
g_MEM_ADDR_ORDER
,
C5_NUM_DQ_PINS
=>
g_NUM_DQ_PINS
,
...
...
@@ -816,7 +818,7 @@ begin
C1_P1_MASK_SIZE
=>
4
,
C1_P1_DATA_PORT_SIZE
=>
32
,
C1_MEMCLK_PERIOD
=>
g_MEMCLK_PERIOD
,
C1_RST_ACT_LOW
=>
1
,
-- Active low
C1_RST_ACT_LOW
=>
g_RST_ACT_LOW
,
C1_CALIB_SOFT_IP
=>
g_CALIB_SOFT_IP
,
C1_MEM_ADDR_ORDER
=>
g_MEM_ADDR_ORDER
,
C1_NUM_DQ_PINS
=>
g_NUM_DQ_PINS
,
...
...
@@ -911,7 +913,7 @@ begin
C1_P1_MASK_SIZE
=>
4
,
C1_P1_DATA_PORT_SIZE
=>
32
,
C1_MEMCLK_PERIOD
=>
g_MEMCLK_PERIOD
,
C1_RST_ACT_LOW
=>
1
,
-- Active low
C1_RST_ACT_LOW
=>
g_RST_ACT_LOW
,
C1_CALIB_SOFT_IP
=>
g_CALIB_SOFT_IP
,
C1_MEM_ADDR_ORDER
=>
g_MEM_ADDR_ORDER
,
C1_NUM_DQ_PINS
=>
g_NUM_DQ_PINS
,
...
...
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