Skip to content

D
DDR3 controller for Spartan6
Commit f903f80f authored by mcattin's avatar mcattin
Browse files
Options

Add local directory structure to repo. 


git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@2 739e5516-d4a2-47df-ba96-5610c1fa693f
parent f09f0c28
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 15451 additions and 0 deletions
doc/ug388.pdf 0 → 100644
View file @ f903f80f
File added
doc/ug416.pdf 0 → 100644
View file @ f903f80f
File added
hdl/ise/_xmsgs/pn_parser.xmsgs 0 → 100755
View file @ f903f80f
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/core-gen/ddr_controller_sp605.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/core-gen/iodrp_controller.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/core-gen/iodrp_mcb_controller.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/core-gen/mcb_raw_wrapper.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/core-gen/mcb_soft_calibration.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/core-gen/mcb_soft_calibration_top.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/core-gen/memc3_infrastructure.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/core-gen/memc3_wrapper.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/ddr3_ctrl.vhd&quot; into library work</arg>
</msg>
</messages>
hdl/ise/_xmsgs/xst.xmsgs 0 → 100755
View file @ f903f80f
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
hdl/ise/ddr3_ctrl.prj 0 → 100755
View file @ f903f80f
vhdl work "../rtl/core-gen/iodrp_mcb_controller.vhd"
vhdl work "../rtl/core-gen/iodrp_controller.vhd"
vhdl work "../rtl/core-gen/mcb_soft_calibration.vhd"
vhdl work "../rtl/core-gen/mcb_soft_calibration_top.vhd"
vhdl work "../rtl/core-gen/mcb_raw_wrapper.vhd"
vhdl work "../rtl/core-gen/memc3_wrapper.vhd"
vhdl work "../rtl/core-gen/memc3_infrastructure.vhd"
vhdl work "../rtl/core-gen/ddr_controller_sp605.vhd"
vhdl work "../rtl/ddr3_ctrl.vhd"
hdl/ise/ddr3_ctrl.stx 0 → 100755
View file @ f903f80f
Release 12.1 - xst M.53d (nt)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to C:/mcattin/ohwr_projects/ddr3_ctrl_core/trunk/hdl/ise/xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.43 secs
--> Parameter xsthdpdir set to C:/mcattin/ohwr_projects/ddr3_ctrl_core/trunk/hdl/ise/xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.45 secs
--> Reading design: ddr3_ctrl.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "C:\mcattin\ohwr_projects\ddr3_ctrl_core\trunk\hdl\rtl\core-gen\iodrp_mcb_controller.vhd" into library work
Parsing entity <iodrp_mcb_controller>.
Parsing architecture <trans> of entity <iodrp_mcb_controller>.
Parsing VHDL file "C:\mcattin\ohwr_projects\ddr3_ctrl_core\trunk\hdl\rtl\core-gen\iodrp_controller.vhd" into library work
Parsing entity <iodrp_controller>.
Parsing architecture <trans> of entity <iodrp_controller>.
Parsing VHDL file "C:\mcattin\ohwr_projects\ddr3_ctrl_core\trunk\hdl\rtl\core-gen\mcb_soft_calibration.vhd" into library work
Parsing entity <mcb_soft_calibration>.
Parsing architecture <trans> of entity <mcb_soft_calibration>.
Parsing VHDL file "C:\mcattin\ohwr_projects\ddr3_ctrl_core\trunk\hdl\rtl\core-gen\mcb_soft_calibration_top.vhd" into library work
Parsing entity <mcb_soft_calibration_top>.
Parsing architecture <trans> of entity <mcb_soft_calibration_top>.
Parsing VHDL file "C:\mcattin\ohwr_projects\ddr3_ctrl_core\trunk\hdl\rtl\core-gen\mcb_raw_wrapper.vhd" into library work
Parsing entity <mcb_raw_wrapper>.
Parsing architecture <aarch> of entity <mcb_raw_wrapper>.
Parsing VHDL file "C:\mcattin\ohwr_projects\ddr3_ctrl_core\trunk\hdl\rtl\core-gen\memc3_wrapper.vhd" into library work
Parsing entity <memc3_wrapper>.
Parsing architecture <acch> of entity <memc3_wrapper>.
Parsing VHDL file "C:\mcattin\ohwr_projects\ddr3_ctrl_core\trunk\hdl\rtl\core-gen\memc3_infrastructure.vhd" into library work
Parsing entity <memc3_infrastructure>.
Parsing architecture <syn> of entity <memc3_infrastructure>.
Parsing VHDL file "C:\mcattin\ohwr_projects\ddr3_ctrl_core\trunk\hdl\rtl\core-gen\ddr_controller_sp605.vhd" into library work
Parsing entity <ddr_controller_sp605>.
Parsing architecture <arc> of entity <ddr_controller_sp605>.
Parsing VHDL file "C:\mcattin\ohwr_projects\ddr3_ctrl_core\trunk\hdl\rtl\ddr3_ctrl.vhd" into library work
Parsing entity <ddr3_ctrl>.
Parsing architecture <rtl> of entity <ddr3_ctrl>.
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.28 secs
-->
Total memory usage is 114196 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
hdl/ise/ddr3_ctrl.xst 0 → 100755
View file @ f903f80f
set -tmpdir "C:/mcattin/ohwr_projects/ddr3_ctrl_core/trunk/hdl/ise/xst/projnav.tmp"
set -xsthdpdir "C:/mcattin/ohwr_projects/ddr3_ctrl_core/trunk/hdl/ise/xst"
run -compileonly yes
-p xc6slx45t-3-fgg484
-top ddr3_ctrl
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso ddr3_ctrl.lso
-keep_hierarchy NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc auto
-reduce_control_sets auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
-ifn ddr3_ctrl.prj
-ifmt mixed
hdl/ise/ddr3_ctrl_core.gise 0 → 100755
View file @ f903f80f
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ddr3_ctrl_core.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_LSO" xil_pn:name="ddr3_ctrl.lso"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ddr3_ctrl.prj"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="ddr3_ctrl.stx"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="ddr3_ctrl.xst"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/ise/ddr3_ctrl_core.xise 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/ise/ddr3_ctrl_summary.html 0 → 100755
View file @ f903f80f
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>ddr3_ctrl Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>ddr3_ctrl_core.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>ddr3_ctrl</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 08/19/2010 - 11:50:24</center>
</BODY></HTML>
\ No newline at end of file
hdl/ise/ddr_controller_summary.html 0 → 100755
View file @ f903f80f
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>ddr_controller Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>ddr3_ctrl_core.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>ddr_controller</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.1</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 08/11/2010 - 17:33:30</center>
</BODY></HTML>
\ No newline at end of file
hdl/ise/iseconfig/ddr3_ctrl.xreport 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/ise/iseconfig/ddr3_ctrl_core.projectmgr 0 → 100755
View file @ f903f80f
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="1" owner="projectmgr" name="ddr3_ctrl_core" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes/>
<SelectedItems>
<SelectedItem>ddr3_ctrl - rtl (/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/ddr3_ctrl.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000164000000020000000000000000000000000000000064ffffffff000000810000000000000002000001640000000100000000000000000000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>ddr3_ctrl - rtl (/home/mcattin/projects/ddr3_ctrl_core/hdl/rtl/ddr3_ctrl.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Add Existing Source</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000164000000010000000100000000000000000000000064ffffffff000000810000000000000001000001640000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes/>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000025f000000040101000100000000000000000000000064ffffffff0000008100000000000000040000010c0000000100000000000000240000000100000000000000660000000100000000000000c90000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>ddr3_ctrl.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes/>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Check Syntax</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000207000000010000000100000000000000000000000064ffffffff000000810000000000000001000002070000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Check Syntax</CurrentItem>
</ItemView>
</Project>
hdl/ise/iseconfig/ddr_controller.xreport 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/par/ddr3_ctlr_core_sp605.ucf 0 → 100755
View file @ f903f80f
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Wed Aug 11 16:32:12 2010
## Generated by MIG Version 3.4
##
############################################################################
## File name : ddr_controller_sp605.ucf
##
## Details : Constraints file
## FPGA family: spartan6
## FPGA: xc6slx45t-fgg484
## Speedgrade: -3
## Design Entry: VHDL
## Design: without Test bench
## DCM Used: Enable
## No.Of Memory Controllers: 1
##
############################################################################
############################################################################
# VCC AUX VOLTAGE
############################################################################
CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
NET "memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c3_pll_lock" TIG;
############################################################################
## Memory Controller 3
## Memory Device: DDR3_SDRAM->MT41J64M16XX-187E
## Frequency: 333.333 MHz
## Time Period: 3000 ps
## Supported Part Numbers: MT41J64M16LA-187E
############################################################################
############################################################################
## Clock constraints
############################################################################
NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3 ns HIGH 50 %;
############################################################################
############################################################################
## I/O TERMINATION
############################################################################
NET "ddr3_dq_b[*]" IN_TERM = NONE;
NET "ddr3_dqs_p_b" IN_TERM = NONE;
NET "ddr3_dqs_n_b" IN_TERM = NONE;
NET "ddr3_udqs_p_b" IN_TERM = NONE;
NET "ddr3_udqs_n_b" IN_TERM = NONE;
############################################################################
# I/O STANDARDS
############################################################################
NET "ddr3_dq_b[*]" IOSTANDARD = SSTL15_II;
NET "ddr3_a_o[*]" IOSTANDARD = SSTL15_II;
NET "ddr3_ba_o[*]" IOSTANDARD = SSTL15_II;
NET "ddr3_dqs_p_b" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_udqs_p_b" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_dqs_n_b" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_udqs_n_b" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_clk_p_o" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_clk_n_o" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_cke_o" IOSTANDARD = SSTL15_II;
NET "ddr3_ras_n_o" IOSTANDARD = SSTL15_II;
NET "ddr3_cas_n_o" IOSTANDARD = SSTL15_II;
NET "ddr3_we_n_o" IOSTANDARD = SSTL15_II;
NET "ddr3_odt_o" IOSTANDARD = SSTL15_II;
NET "ddr3_rst_n_o" IOSTANDARD = SSTL15_II;
NET "ddr3_dm_o" IOSTANDARD = SSTL15_II;
NET "ddr3_udm_o" IOSTANDARD = SSTL15_II;
NET "ddr3_rzq_b" IOSTANDARD = SSTL15_II;
NET "ddr3_zio_b" IOSTANDARD = SSTL15_II;
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################
NET "ddr3_a_o[0]" LOC = "K2" ;
NET "ddr3_a_o[10]" LOC = "J4" ;
NET "ddr3_a_o[11]" LOC = "E1" ;
NET "ddr3_a_o[12]" LOC = "F1" ;
NET "ddr3_a_o[1]" LOC = "K1" ;
NET "ddr3_a_o[2]" LOC = "K5" ;
NET "ddr3_a_o[3]" LOC = "M6" ;
NET "ddr3_a_o[4]" LOC = "H3" ;
NET "ddr3_a_o[5]" LOC = "M3" ;
NET "ddr3_a_o[6]" LOC = "L4" ;
NET "ddr3_a_o[7]" LOC = "K6" ;
NET "ddr3_a_o[8]" LOC = "G3" ;
NET "ddr3_a_o[9]" LOC = "G1" ;
NET "ddr3_ba_o[0]" LOC = "J3" ;
NET "ddr3_ba_o[1]" LOC = "J1" ;
NET "ddr3_ba_o[2]" LOC = "H1" ;
NET "ddr3_cas_n_o" LOC = "M4" ;
NET "ddr3_clk_p_o" LOC = "K4" ;
NET "ddr3_clk_n_o" LOC = "K3" ;
NET "ddr3_cke_o" LOC = "F2" ;
NET "ddr3_dm_o" LOC = "N4" ;
NET "ddr3_dq_b[0]" LOC = "R3" ;
NET "ddr3_dq_b[10]" LOC = "U3" ;
NET "ddr3_dq_b[11]" LOC = "U1" ;
NET "ddr3_dq_b[12]" LOC = "W3" ;
NET "ddr3_dq_b[13]" LOC = "W1" ;
NET "ddr3_dq_b[14]" LOC = "Y2" ;
NET "ddr3_dq_b[15]" LOC = "Y1" ;
NET "ddr3_dq_b[1]" LOC = "R1" ;
NET "ddr3_dq_b[2]" LOC = "P2" ;
NET "ddr3_dq_b[3]" LOC = "P1" ;
NET "ddr3_dq_b[4]" LOC = "L3" ;
NET "ddr3_dq_b[5]" LOC = "L1" ;
NET "ddr3_dq_b[6]" LOC = "M2" ;
NET "ddr3_dq_b[7]" LOC = "M1" ;
NET "ddr3_dq_b[8]" LOC = "T2" ;
NET "ddr3_dq_b[9]" LOC = "T1" ;
NET "ddr3_dqs_p_b" LOC = "N3" ;
NET "ddr3_dqs_n_b" LOC = "N1" ;
NET "ddr3_odt_o" LOC = "L6" ;
NET "ddr3_ras_n_o" LOC = "M5" ;
NET "ddr3_rst_n_o" LOC = "E3" ;
NET "ddr3_udm_o" LOC = "P3" ;
NET "ddr3_udqs_p_b" LOC = "V2" ;
NET "ddr3_udqs_n_b" LOC = "V1" ;
NET "ddr3_we_n_o" LOC = "H2" ;
##################################################################################
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "ddr3_rzq_b" LOC = "K7" ;
##################################################################################
#ZIO is only required for MCB designs using Calibrated Input Termination.#
#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
#MCB bank but must be left as a no-connect (NC) pin.#
##################################################################################
NET "ddr3_zio_b" LOC = "R7" ;
hdl/par/ddr3_ctrl_core.ucf 0 → 100755
View file @ f903f80f
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Thu Aug 5 13:48:23 2010
## Generated by MIG Version 3.4
##
############################################################################
## File name : example_top.ucf
##
## Details : Constraints file
## FPGA family: spartan6
## FPGA: xc6slx150t-fgg676
## Speedgrade: -2
## Design Entry: VHDL
## Design: with Test bench
## DCM Used: Enable
## No.Of Memory Controllers: 1
##
############################################################################
############################################################################
# VCC AUX VOLTAGE
############################################################################
CONFIG VCCAUX=3.3; # Valid values are 2.5 and 3.3
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
NET "memc5_wrapper_inst/memc5_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c5_pll_lock" TIG;
############################################################################
## Memory Controller 5
## Memory Device: DDR3_SDRAM->MT41J128M16HA-15E
## Frequency: 333.333 MHz
## Time Period: 3000 ps
############################################################################
############################################################################
## Clock constraints
############################################################################
NET "memc5_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3 ns HIGH 50 %;
############################################################################
############################################################################
## I/O TERMINATION
############################################################################
NET "ddr3_dq_b[*]" IN_TERM = NONE;
NET "ddr3_dqs_p_o" IN_TERM = NONE;
NET "ddr3_dqs_n_o" IN_TERM = NONE;
NET "ddr3_udqs_p_o" IN_TERM = NONE;
NET "ddr3_udqs_n_o" IN_TERM = NONE;
############################################################################
# I/O STANDARDS
############################################################################
NET "ddr3_dq_b[*]" IOSTANDARD = SSTL15_II;
NET "ddr3_a_o[*]" IOSTANDARD = SSTL15_II;
NET "ddr3_ba_o[*]" IOSTANDARD = SSTL15_II;
NET "ddr3_dqs_p_o" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_udqs_p_o" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_dqs_n_o" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_udqs_n_o" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_clk_p_o" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_clk_n_o" IOSTANDARD = DIFF_SSTL15_II;
NET "ddr3_cke_o" IOSTANDARD = SSTL15_II;
NET "ddr3_ras_n_o" IOSTANDARD = SSTL15_II;
NET "ddr3_cas_n_o" IOSTANDARD = SSTL15_II;
NET "ddr3_we_n_o" IOSTANDARD = SSTL15_II;
NET "ddr3_odt_o" IOSTANDARD = SSTL15_II;
NET "ddr3_rst_n_o" IOSTANDARD = SSTL15_II;
NET "ddr3_dm_o" IOSTANDARD = SSTL15_II;
NET "ddr3_udm_o" IOSTANDARD = SSTL15_II;
NET "ddr3_rzq_b" IOSTANDARD = SSTL15_II;
############################################################################
# MCB 5
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################
NET "ddr3_a_o[0]" LOC = "C25" ;
NET "ddr3_a_o[10]" LOC = "F22" ;
NET "ddr3_a_o[11]" LOC = "K19" ;
NET "ddr3_a_o[12]" LOC = "C24" ;
NET "ddr3_a_o[13]" LOC = "B24" ;
NET "ddr3_a_o[1]" LOC = "C26" ;
NET "ddr3_a_o[2]" LOC = "E24" ;
NET "ddr3_a_o[3]" LOC = "K21" ;
NET "ddr3_a_o[4]" LOC = "G23" ;
NET "ddr3_a_o[5]" LOC = "M18" ;
NET "ddr3_a_o[6]" LOC = "M19" ;
NET "ddr3_a_o[7]" LOC = "E23" ;
NET "ddr3_a_o[8]" LOC = "H21" ;
NET "ddr3_a_o[9]" LOC = "H22" ;
NET "ddr3_ba_o[0]" LOC = "L19" ;
NET "ddr3_ba_o[1]" LOC = "K20" ;
NET "ddr3_ba_o[2]" LOC = "J22" ;
NET "ddr3_cas_n_o" LOC = "G24" ;
NET "ddr3_clk_p_o" LOC = "B25" ;
NET "ddr3_clk_n_o" LOC = "B26" ;
NET "ddr3_cke_o" LOC = "D23" ;
NET "ddr3_dm_o" LOC = "J24" ;
NET "ddr3_dq_b[0]" LOC = "G25" ;
NET "ddr3_dq_b[10]" LOC = "J25" ;
NET "ddr3_dq_b[11]" LOC = "J26" ;
NET "ddr3_dq_b[12]" LOC = "L25" ;
NET "ddr3_dq_b[13]" LOC = "L26" ;
NET "ddr3_dq_b[14]" LOC = "N25" ;
NET "ddr3_dq_b[15]" LOC = "N26" ;
NET "ddr3_dq_b[1]" LOC = "G26" ;
NET "ddr3_dq_b[2]" LOC = "H24" ;
NET "ddr3_dq_b[3]" LOC = "H26" ;
NET "ddr3_dq_b[4]" LOC = "E25" ;
NET "ddr3_dq_b[5]" LOC = "E26" ;
NET "ddr3_dq_b[6]" LOC = "D24" ;
NET "ddr3_dq_b[7]" LOC = "D26" ;
NET "ddr3_dq_b[8]" LOC = "K24" ;
NET "ddr3_dq_b[9]" LOC = "K26" ;
NET "ddr3_dqs_p_o" LOC = "F24" ;
NET "ddr3_dqs_n_o" LOC = "F26" ;
NET "ddr3_odt_o" LOC = "K22" ;
NET "ddr3_ras_n_o" LOC = "F23" ;
NET "ddr3_rst_n_o" LOC = "K18" ;
NET "ddr3_udm_o" LOC = "J23" ;
NET "ddr3_udqs_p_o" LOC = "M24" ;
NET "ddr3_udqs_n_o" LOC = "M26" ;
NET "ddr3_we_n_o" LOC = "J20" ;
##################################################################################
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "ddr3_rzq_b" LOC = "M21" ;
hdl/rtl/core-gen/ddr_controller.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/ddr_controller_sp605.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/iodrp_controller.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/iodrp_mcb_controller.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/mcb_raw_wrapper.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/mcb_soft_calibration.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/mcb_soft_calibration_top.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/memc3_infrastructure.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/memc3_wrapper.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/memc5_infrastructure.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/core-gen/memc5_wrapper.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
hdl/rtl/ddr3_ctrl.vhd 0 → 100755
View file @ f903f80f
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment