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DIOT Zynq Ultrascale-based System Board
Issues
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349
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[Cpcis_connectors_P1_P2_P3] Mark LVDS that are connected to clock-capable FPGA I/Os (LVDS0, LVDS8 for every slot)
#24
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
2
updated
Mar 09, 2020
[Cpcis_connectors_P1_P2_P3] J14E: connector labels overlaping with the symbol
#23
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
1
updated
Mar 09, 2020
[Cpcis_connectors_P1_P2_P3] PS_ON# note
#21
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
1
updated
Mar 09, 2020
[Cpcis_connectors_P1_P2_P3] align symbols of connectors
#20
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
2
updated
Mar 09, 2020
[Cpcis_connectors_P1_P2_P3] CPCIS I2C pull-ups
#19
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 09, 2020
[Cpcis_connectors_P1_P2_P3] P1 rows messed up
#14
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
3
updated
Mar 09, 2020
[DIOT_Controller] rename UART_TXD/UART_RXD to UART-PS_TXD/UART-PS_RXD to clearly distinguish from UART-PL
#13
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
1
updated
Mar 09, 2020
[DIOT_Controller] "no ERC" directive placed on OVERTHERM signal
#12
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 09, 2020
[General] update Copyright to 2019-2020
#10
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
2
updated
Mar 09, 2020
[General] use "_N" suffix for all negative signals (instead of "#")
#7
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Minor
sch-v1
CLOSED
1
updated
Mar 06, 2020
[General] Double SFP cage
#3
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
2
updated
Mar 06, 2020
[General] PRTR5V0U2X has designator D* in most places except for IC4.
#2
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 06, 2020
[General] swapped sheets with FPGA banks 63/64
#1
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Done
Major
sch-v1
CLOSED
1
updated
Mar 06, 2020
[fpga-pl-mgts] FMC MGT Tx/Rx lines are missing 100nF AC coupling caps
#84
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Major
sch-v1
CLOSED
6
updated
Mar 03, 2020
[power-supply-1] R37 sense resistor value
#120
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Major
sch-v1
CLOSED
2
updated
Feb 27, 2020
[i2c_mux] SDA/SCL pull-ups
#66
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Minor
sch-v1
CLOSED
2
updated
Feb 17, 2020
[fmc-connector] PG_C2M shall have 10k pull-up to P3V3.
#33
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Major
sch-v1
CLOSED
2
updated
Feb 03, 2020
[fmc-connector] Double "Matched Net Lengths" rule for FMC.LA, one says 8mm, the other says 0.15mm
#38
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Major
sch-v1
CLOSED
1
updated
Jan 31, 2020
[Cpcis_connectors_P4_P5_P6] Remove "<n>_PE_TX_P/N" labels, they are not used anywhere else
#29
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Minor
sch-v1
CLOSED
1
updated
Jan 31, 2020
[Cpcis_connectors_P1_P2_P3] Remove "<n>_PE_TX_P/N" labels, they are not used anywhere else
#22
· opened
Jan 27, 2020
by
Grzegorz Daniluk
Minor
sch-v1
CLOSED
1
updated
Jan 31, 2020
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