Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FPGA and ARM SoC FMC Carrier FASEC
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FPGA and ARM SoC FMC Carrier FASEC
Repository
953715ab8c4ad153d73719aff35c4e26af21da06
Switch branch/tag
fasec
FASEC_prototype.srcs
tcl
set_registers.tcl
Find file
Blame
History
Permalink
after synthesis, I should really start putting timing constraints..
· 953715ab
Pieter Van Trappen
authored
May 11, 2017
953715ab
set_registers.tcl
2.27 KB
Edit
Web IDE
Replace set_registers.tcl
×
Attach a file by drag & drop or
click to upload
Commit message
Replace set_registers.tcl
Replace file
Cancel
A new branch will be created in your fork and a new merge request will be started.
