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FPGA and ARM SoC FMC Carrier FASEC
Commit 08ab5dcf authored by Pieter Van Trappen's avatar Pieter Van Trappen
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output products generated

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FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd
View file @ 08ab5dcf
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Thu Apr 13 09:57:53 2017
--Date : Thu May 11 16:53:06 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target system_design.bd
--Design : system_design
......@@ -4009,70 +4009,6 @@ architecture STRUCTURE of system_design is
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_design_rst_wrc_1p_kintex7_0_62M_0;
component system_design_fasec_hwtest_0_0 is
port (
ps_clk_i : in STD_LOGIC;
osc100_clk_i : in STD_LOGIC;
FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC2_PRSNTM2C_n_i : in STD_LOGIC;
FMC2_CLK0M2C_P_i : in STD_LOGIC;
FMC2_CLK0M2C_N_i : in STD_LOGIC;
FMC2_CLK0C2M_P_o : out STD_LOGIC;
FMC2_CLK0C2M_N_o : out STD_LOGIC;
FMC2_GP0_i : in STD_LOGIC;
FMC2_GP1_i : in STD_LOGIC;
FMC2_GP2_i : in STD_LOGIC;
FMC2_GP3_b : inout STD_LOGIC;
FMC1_PRSNTM2C_n_i : in STD_LOGIC;
FMC1_CLK0M2C_P_i : in STD_LOGIC;
FMC1_CLK0M2C_N_i : in STD_LOGIC;
FMC1_CLK0C2M_P_o : out STD_LOGIC;
FMC1_CLK0C2M_N_o : out STD_LOGIC;
FMC1_GP0_i : in STD_LOGIC;
FMC1_GP1_i : in STD_LOGIC;
FMC1_GP2_i : in STD_LOGIC;
FMC1_GP3_b : inout STD_LOGIC;
pb_gp_n_i : in STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
led_line_pl_o : out STD_LOGIC;
watchdog_pl_o : out STD_LOGIC;
dig_in1_i : in STD_LOGIC;
dig_in2_i : in STD_LOGIC;
dig_in3_n_i : in STD_LOGIC;
dig_in4_n_i : in STD_LOGIC;
dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
dig_out5_n : out STD_LOGIC;
dig_out6_n : out STD_LOGIC;
gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
intr_o : out STD_LOGIC;
intr_led_o : out STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component system_design_fasec_hwtest_0_0;
component system_design_axi_wb_i2c_master_0_1 is
port (
i2c_scl_io : inout STD_LOGIC;
......@@ -4191,6 +4127,70 @@ architecture STRUCTURE of system_design is
s00_axi_rready : in STD_LOGIC
);
end component system_design_wrc_1p_kintex7_0_0;
component system_design_fasec_hwtest_0_0 is
port (
ps_clk_i : in STD_LOGIC;
osc100_clk_i : in STD_LOGIC;
FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC2_PRSNTM2C_n_i : in STD_LOGIC;
FMC2_CLK0M2C_P_i : in STD_LOGIC;
FMC2_CLK0M2C_N_i : in STD_LOGIC;
FMC2_CLK0C2M_P_o : out STD_LOGIC;
FMC2_CLK0C2M_N_o : out STD_LOGIC;
FMC2_GP0_i : in STD_LOGIC;
FMC2_GP1_i : in STD_LOGIC;
FMC2_GP2_i : in STD_LOGIC;
FMC2_GP3_b : inout STD_LOGIC;
FMC1_PRSNTM2C_n_i : in STD_LOGIC;
FMC1_CLK0M2C_P_i : in STD_LOGIC;
FMC1_CLK0M2C_N_i : in STD_LOGIC;
FMC1_CLK0C2M_P_o : out STD_LOGIC;
FMC1_CLK0C2M_N_o : out STD_LOGIC;
FMC1_GP0_i : in STD_LOGIC;
FMC1_GP1_i : in STD_LOGIC;
FMC1_GP2_i : in STD_LOGIC;
FMC1_GP3_b : inout STD_LOGIC;
pb_gp_n_i : in STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
led_line_pl_o : out STD_LOGIC;
watchdog_pl_o : out STD_LOGIC;
dig_in1_i : in STD_LOGIC;
dig_in2_i : in STD_LOGIC;
dig_in3_n_i : in STD_LOGIC;
dig_in4_n_i : in STD_LOGIC;
dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
dig_out5_n : out STD_LOGIC;
dig_out6_n : out STD_LOGIC;
gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
intr_o : out STD_LOGIC;
intr_led_o : out STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component system_design_fasec_hwtest_0_0;
signal FMC1_CLK0M2C_N_i_1 : STD_LOGIC;
signal FMC1_CLK0M2C_P_i_1 : STD_LOGIC;
signal FMC1_PRSNTM2C_n_i_1 : STD_LOGIC;
......
FASEC_prototype.ip_user_files/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
View file @ 08ab5dcf
......@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:fasec_hwtest:3.2.0
-- IP Revision: 27
-- IP VLNV: user.org:user:fasec_hwtest:3.2.1
-- IP Revision: 29
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
......
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd → FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
View file @ 08ab5dcf
......@@ -6,7 +6,7 @@
-- Author : Pieter Van Trappen <pvantrap@cern.ch>
-- Company : CERN
-- Created : 2016-11-22
-- Last update: 2017-04-12
-- Last update: 2017-05-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
......@@ -112,6 +112,7 @@ architecture rtl of general_fmc is
type t_cmplengths is array (0 to c_COMP-1) of std_logic_vector(c_COUNTERWIDTH-1 downto 0);
signal s_cmp_lengths : t_cmplengths;
signal s_diffouts_o : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outleds : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outsfeedbak_i : std_logic_vector(c_OUTFBD-1 downto 0);
signal s_spi_sclk : std_logic;
signal s_spi_mosi : std_logic;
......@@ -201,6 +202,7 @@ begin
-- outputs loop
fmc_03287_obufds : for I in 0 to c_DOUTS-1 generate
gen_outs : if g_FMC = "EDA-03287" generate
-- output LVDS buffers
cmp_OBUFDS_fmc : OBUFDS
generic map (
-- IOSTANDARD => "LVDS_25", -- Specify the output I/O standard
......@@ -209,6 +211,24 @@ begin
O => FMC_LA_P_b(c_COMP+I), -- Diff_p output (connect directly to top-level port)
OB => FMC_LA_N_b(c_COMP+I), -- Diff_n output (connect directly to top-level port)
I => s_diffouts_o(I)); -- Buffer input
-- pulse extenders for LEDs
cmp_outs_pulseMeasure : pulseMeasure
generic map (
g_COUNTERWIDTH => c_COUNTERWIDTH,
g_LEDCOUNTERWIDTH => c_LEDCOUNTERWIDTH,
g_LEDWAIT => 10000000, -- 100ms when 10ns clock
g_MISSINGCDC => false)
port map (
clk_dsp_i => clk_i, -- for now no clock domain crossing
reset_n_i => s_reset_n,
pulse_i => s_diffouts_o(I),
missingWindow_i => to_unsigned(0, c_LEDCOUNTERWIDTH),
pulse_o => open,
edgeDetected_o => open,
usrLed_o => s_outleds(I),
window_o => open,
pulseLength_o => open,
LedCount_o => open);
end generate gen_outs;
end generate fmc_03287_obufds;
-- SPI DAC for comparator reference
......@@ -270,6 +290,7 @@ begin
variable v_cmpled : std_logic_vector(c_COMP-1 downto 0);
variable v_dout : std_logic_vector(c_DOUTS-1 downto 0);
variable v_fbd : std_logic_vector(c_OUTFBD-1 downto 0);
variable v_outleds : std_logic_vector(c_DOUTS-1 downto 0);
begin
if g_FMC = "EDA-03287" and rising_edge(clk_i) then
-- in/outputs
......@@ -284,7 +305,7 @@ begin
else
intr_o <= '0';
end if;
if (v_cmpled /= s_compleds) then
if (v_cmpled /= s_compleds) or (v_outleds /= s_outleds) then
intr_led_o <= '1';
else
intr_led_o <= '0';
......@@ -292,6 +313,7 @@ begin
-- clocking in data for above interrupt generation
v_cmpled := s_compleds(c_COMP-1 downto 0);
v_cmp := s_cmp_pulse(c_COMP-1 downto 0);
v_outleds := s_outleds(c_DOUTS-1 downto 0);
end if;
end process p_fmc_03287_io;
-- no additional clocking of comparators & LEDs
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/README.txt
View file @ 08ab5dcf
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/compile.do
View file @ 08ab5dcf
......@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -93 \
......@@ -576,6 +576,7 @@ vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
"../../../bd/system_design/hdl/system_design.vhd" \
vlog -work axi_protocol_converter_v2_1_9 -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
"../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
......@@ -603,8 +604,5 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
"../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
"../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/hdl/system_design.vhd" \
vlog -work xil_defaultlib "glbl.v"
FASEC_prototype.ip_user_files/sim_scripts/system_design/activehdl/system_design.sh
View file @ 08ab5dcf
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/README.txt
View file @ 08ab5dcf
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/run.f
View file @ 08ab5dcf
......@@ -40,22 +40,22 @@
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
-endlib
-makelib ies/hdl_lib \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
-endlib
-makelib ies/xil_defaultlib \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
-endlib
-makelib ies/hdl_lib \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
-endlib
-makelib ies/xil_defaultlib \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
-endlib
-makelib ies/lib_cdc_v1_0_2 \
......@@ -525,6 +525,7 @@
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
"../../../bd/system_design/hdl/system_design.vhd" \
-endlib
-makelib ies/axi_protocol_converter_v2_1_9 \
"../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
......@@ -552,9 +553,6 @@
"../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
"../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
-endlib
-makelib ies/xil_defaultlib \
"../../../bd/system_design/hdl/system_design.vhd" \
-endlib
-makelib ies/xil_defaultlib \
glbl.v
-endlib
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/ies/system_design.sh
View file @ 08ab5dcf
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/README.txt
View file @ 08ab5dcf
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/compile.do
View file @ 08ab5dcf
......@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructur
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -64 -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -64 -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -64 -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -64 -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -64 -93 \
......@@ -576,6 +576,7 @@ vcom -work xil_defaultlib -64 -93 \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
"../../../bd/system_design/hdl/system_design.vhd" \
vlog -work axi_protocol_converter_v2_1_9 -64 -incr "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
"../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
......@@ -603,8 +604,5 @@ vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic/axi_infrastructur
"../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
"../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
vcom -work xil_defaultlib -64 -93 \
"../../../bd/system_design/hdl/system_design.vhd" \
vlog -work xil_defaultlib "glbl.v"
FASEC_prototype.ip_user_files/sim_scripts/system_design/modelsim/system_design.sh
View file @ 08ab5dcf
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/README.txt
View file @ 08ab5dcf
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/compile.do
View file @ 08ab5dcf
......@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -64 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -64 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -64 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -64 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -64 \
......@@ -576,6 +576,7 @@ vcom -work xil_defaultlib -64 \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
"../../../bd/system_design/hdl/system_design.vhd" \
vlog -work axi_protocol_converter_v2_1_9 -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
"../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
......@@ -603,8 +604,5 @@ vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic/axi_infrastructure_v1_1
"../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
"../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
vcom -work xil_defaultlib -64 \
"../../../bd/system_design/hdl/system_design.vhd" \
vlog -work xil_defaultlib "glbl.v"
FASEC_prototype.ip_user_files/sim_scripts/system_design/questa/system_design.sh
View file @ 08ab5dcf
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/README.txt
View file @ 08ab5dcf
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/compile.do
View file @ 08ab5dcf
......@@ -91,22 +91,22 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
"../../../bd/system_design/ip/system_design_processing_system7_0_0/sim/system_design_processing_system7_0_0.v" \
vcom -work hdl_lib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
vcom -work hdl_lib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
vcom -work lib_cdc_v1_0_2 -93 \
......@@ -576,6 +576,7 @@ vcom -work xil_defaultlib -93 \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
"../../../bd/system_design/hdl/system_design.vhd" \
vlog -work axi_protocol_converter_v2_1_9 -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" "+incdir+../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" "+incdir+../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
"../../../ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_a_axi3_conv.v" \
......@@ -603,8 +604,5 @@ vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic/axi_infrastructure_v1
"../../../bd/system_design/ip/system_design_auto_pc_1/sim/system_design_auto_pc_1.v" \
"../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
vcom -work xil_defaultlib -93 \
"../../../bd/system_design/hdl/system_design.vhd" \
vlog -work xil_defaultlib "glbl.v"
FASEC_prototype.ip_user_files/sim_scripts/system_design/riviera/system_design.sh
View file @ 08ab5dcf
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/README.txt
View file @ 08ab5dcf
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/vcs/system_design.sh
View file @ 08ab5dcf
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......@@ -113,25 +113,25 @@ compile()
2>&1 | tee -a vlogan.log
vhdlan -work hdl_lib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work xil_defaultlib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work hdl_lib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd" \
2>&1 | tee -a vhdlan.log
vhdlan -work xil_defaultlib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd" \
"$ref_dir/../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd" \
"$ref_dir/../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd" \
2>&1 | tee -a vhdlan.log
......@@ -656,6 +656,7 @@ compile()
"$ref_dir/../../../bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/sim/system_design_axi_wb_i2c_master_2_0.vhd" \
"$ref_dir/../../../bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/sim/system_design_axi_wb_i2c_master_0_1.vhd" \
"$ref_dir/../../../bd/system_design/ip/system_design_rst_wrc_1p_kintex7_0_62M_0/sim/system_design_rst_wrc_1p_kintex7_0_62M_0.vhd" \
"$ref_dir/../../../bd/system_design/hdl/system_design.vhd" \
2>&1 | tee -a vhdlan.log
vlogan -work axi_protocol_converter_v2_1_9 $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic/axi_infrastructure_v1_1/hdl/verilog" +incdir+"$ref_dir/../../../ipstatic/processing_system7_bfm_v2_0/hdl" \
......@@ -686,10 +687,6 @@ compile()
"$ref_dir/../../../bd/system_design/ip/system_design_auto_pc_2/sim/system_design_auto_pc_2.v" \
2>&1 | tee -a vlogan.log
vhdlan -work xil_defaultlib $vhdlan_opts \
"$ref_dir/../../../bd/system_design/hdl/system_design.vhd" \
2>&1 | tee -a vhdlan.log
vlogan -work xil_defaultlib $vlogan_opts +v2k \
glbl.v \
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/README.txt
View file @ 08ab5dcf
......@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Thu Apr 13 09:58:27 CEST 2017
# Generated by export_simulation on Thu May 11 16:53:13 CEST 2017
#
################################################################################
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/system_design.sh
View file @ 08ab5dcf
......@@ -8,7 +8,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Thu Apr 13 09:58:27 CEST 2017
# Generated by Vivado on Thu May 11 16:53:13 CEST 2017
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
#
# usage: system_design.sh [-help]
......
FASEC_prototype.ip_user_files/sim_scripts/system_design/xsim/vhdl.prj
View file @ 08ab5dcf
vhdl xpm "/local/EDA/Xilinx/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/counterUpDown.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/main_pkg.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/ip_cores/hdl_lib/modules/general/clockDivider.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/spi_transceiver.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/doubleBufferEdge.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/counterUpDown.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/main_pkg.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/pulseMeasure.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/dac7716_spi.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/axi4/axi4lite_slave.vhd"
vhdl hdl_lib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/ip_cores/hdl_lib/modules/general/clockDivider.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd"
vhdl xil_defaultlib "../../../bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd"
vhdl lib_cdc_v1_0_2 "../../../ipstatic/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd"
vhdl proc_sys_reset_v5_0_9 "../../../ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd"
......
FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design.vhd
View file @ 08ab5dcf
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Thu Apr 13 09:57:53 2017
--Date : Thu May 11 16:53:06 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target system_design.bd
--Design : system_design
......@@ -4009,70 +4009,6 @@ architecture STRUCTURE of system_design is
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_design_rst_wrc_1p_kintex7_0_62M_0;
component system_design_fasec_hwtest_0_0 is
port (
ps_clk_i : in STD_LOGIC;
osc100_clk_i : in STD_LOGIC;
FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC2_PRSNTM2C_n_i : in STD_LOGIC;
FMC2_CLK0M2C_P_i : in STD_LOGIC;
FMC2_CLK0M2C_N_i : in STD_LOGIC;
FMC2_CLK0C2M_P_o : out STD_LOGIC;
FMC2_CLK0C2M_N_o : out STD_LOGIC;
FMC2_GP0_i : in STD_LOGIC;
FMC2_GP1_i : in STD_LOGIC;
FMC2_GP2_i : in STD_LOGIC;
FMC2_GP3_b : inout STD_LOGIC;
FMC1_PRSNTM2C_n_i : in STD_LOGIC;
FMC1_CLK0M2C_P_i : in STD_LOGIC;
FMC1_CLK0M2C_N_i : in STD_LOGIC;
FMC1_CLK0C2M_P_o : out STD_LOGIC;
FMC1_CLK0C2M_N_o : out STD_LOGIC;
FMC1_GP0_i : in STD_LOGIC;
FMC1_GP1_i : in STD_LOGIC;
FMC1_GP2_i : in STD_LOGIC;
FMC1_GP3_b : inout STD_LOGIC;
pb_gp_n_i : in STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
led_line_pl_o : out STD_LOGIC;
watchdog_pl_o : out STD_LOGIC;
dig_in1_i : in STD_LOGIC;
dig_in2_i : in STD_LOGIC;
dig_in3_n_i : in STD_LOGIC;
dig_in4_n_i : in STD_LOGIC;
dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
dig_out5_n : out STD_LOGIC;
dig_out6_n : out STD_LOGIC;
gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
intr_o : out STD_LOGIC;
intr_led_o : out STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component system_design_fasec_hwtest_0_0;
component system_design_axi_wb_i2c_master_0_1 is
port (
i2c_scl_io : inout STD_LOGIC;
......@@ -4191,6 +4127,70 @@ architecture STRUCTURE of system_design is
s00_axi_rready : in STD_LOGIC
);
end component system_design_wrc_1p_kintex7_0_0;
component system_design_fasec_hwtest_0_0 is
port (
ps_clk_i : in STD_LOGIC;
osc100_clk_i : in STD_LOGIC;
FMC2_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC2_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC1_LA_P_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC1_LA_N_b : inout STD_LOGIC_VECTOR ( 33 downto 0 );
FMC2_PRSNTM2C_n_i : in STD_LOGIC;
FMC2_CLK0M2C_P_i : in STD_LOGIC;
FMC2_CLK0M2C_N_i : in STD_LOGIC;
FMC2_CLK0C2M_P_o : out STD_LOGIC;
FMC2_CLK0C2M_N_o : out STD_LOGIC;
FMC2_GP0_i : in STD_LOGIC;
FMC2_GP1_i : in STD_LOGIC;
FMC2_GP2_i : in STD_LOGIC;
FMC2_GP3_b : inout STD_LOGIC;
FMC1_PRSNTM2C_n_i : in STD_LOGIC;
FMC1_CLK0M2C_P_i : in STD_LOGIC;
FMC1_CLK0M2C_N_i : in STD_LOGIC;
FMC1_CLK0C2M_P_o : out STD_LOGIC;
FMC1_CLK0C2M_N_o : out STD_LOGIC;
FMC1_GP0_i : in STD_LOGIC;
FMC1_GP1_i : in STD_LOGIC;
FMC1_GP2_i : in STD_LOGIC;
FMC1_GP3_b : inout STD_LOGIC;
pb_gp_n_i : in STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
led_line_pl_o : out STD_LOGIC;
watchdog_pl_o : out STD_LOGIC;
dig_in1_i : in STD_LOGIC;
dig_in2_i : in STD_LOGIC;
dig_in3_n_i : in STD_LOGIC;
dig_in4_n_i : in STD_LOGIC;
dig_outs_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
dig_out5_n : out STD_LOGIC;
dig_out6_n : out STD_LOGIC;
gem_status_vector_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
intr_o : out STD_LOGIC;
intr_led_o : out STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end component system_design_fasec_hwtest_0_0;
signal FMC1_CLK0M2C_N_i_1 : STD_LOGIC;
signal FMC1_CLK0M2C_P_i_1 : STD_LOGIC;
signal FMC1_PRSNTM2C_n_i_1 : STD_LOGIC;
......
FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
View file @ 08ab5dcf
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Thu Apr 13 09:57:53 2017
--Date : Thu May 11 16:53:07 2017
--Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
--Command : generate_target system_design_wrapper.bd
--Design : system_design_wrapper
......
FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design.hwh
View file @ 08ab5dcf
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu Apr 13 09:58:22 2017" VIVADOVERSION="2016.2">
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Thu May 11 16:53:08 2017" VIVADOVERSION="2016.2">
<SYSTEMINFO ARCH="zynq" DEVICE="7z030" NAME="system_design" PACKAGE="ffg676" SPEEDGRADE="-2"/>
......@@ -51,8 +51,8 @@
<PORT DIR="IO" NAME="gtp_wr_scl" SIGIS="undef"/>
<PORT DIR="I" NAME="pb_gp_i" SIGIS="undef" SIGNAME="External_Ports_pb_gp_i">
<CONNECTIONS>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="pb_gp_n_i"/>
<CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="button_rst_n_i"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="pb_gp_n_i"/>
</CONNECTIONS>
</PORT>
<PORT DIR="O" LEFT="3" NAME="led_col_pl_o" RIGHT="0" SIGIS="undef" SIGNAME="fasec_hwtest_0_led_col_pl_o">
......@@ -3685,7 +3685,7 @@
</BUSINTERFACE>
</BUSINTERFACES>
</MODULE>
<MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.2.0" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.2.0">
<MODULE FULLNAME="/fasec_hwtest_0" HWVERSION="3.2.1" INSTANCE="fasec_hwtest_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="fasec_hwtest" VLNV="user.org:user:fasec_hwtest:3.2.1">
<DOCUMENTS/>
<ADDRESSBLOCKS>
<ADDRESSBLOCK ACCESS="" INTERFACE="S00_AXI" NAME="S00_AXI_reg" RANGE="4096" USAGE=""/>
......@@ -5585,8 +5585,8 @@
<CONNECTION INSTANCE="axi_dma_0" PORT="m_axi_s2mm_aclk"/>
<CONNECTION INSTANCE="xadc_wiz_0" PORT="s_axis_aclk"/>
<CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aclk"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="ps_clk_i"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aclk"/>
<CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
<CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="ACLK"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="ACLK"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ACLK"/>
......@@ -5600,8 +5600,8 @@
<CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ACLK"/>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="M00_ACLK"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ACLK"/>
<CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aclk"/>
<CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aclk"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="ps_clk_i"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aclk"/>
</CONNECTIONS>
</PORT>
<PORT CLKFREQUENCY="10000000" DIR="O" NAME="FCLK_CLK1" SIGIS="clk"/>
......@@ -7423,7 +7423,8 @@
<CONNECTION INSTANCE="axi_dma_0" PORT="axi_resetn"/>
<CONNECTION INSTANCE="xadc_axis_fifo_adapter_0" PORT="AXIS_RESET_N"/>
<CONNECTION INSTANCE="axi_uartlite_0" PORT="s_axi_aresetn"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aresetn"/>
<CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
<CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="S00_ARESETN"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M06_ARESETN"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M05_ARESETN"/>
......@@ -7436,8 +7437,7 @@
<CONNECTION INSTANCE="axi_interconnect_0" PORT="ARESETN"/>
<CONNECTION INSTANCE="axi_interconnect_0" PORT="S00_ARESETN"/>
<CONNECTION INSTANCE="processing_system7_0_axi_periph" PORT="M07_ARESETN"/>
<CONNECTION INSTANCE="axi_wb_i2c_master_0" PORT="s00_axi_aresetn"/>
<CONNECTION INSTANCE="axi_wb_i2c_master_2" PORT="s00_axi_aresetn"/>
<CONNECTION INSTANCE="fasec_hwtest_0" PORT="s00_axi_aresetn"/>
</CONNECTIONS>
</PORT>
</PORTS>
......@@ -7486,9 +7486,9 @@
</PORT>
<PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" RIGHT="0" SIGIS="rst" SIGNAME="rst_wrc_1p_kintex7_0_62M_peripheral_aresetn">
<CONNECTIONS>
<CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="s00_axi_aresetn"/>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="M00_ARESETN"/>
<CONNECTION INSTANCE="axi_interconnect_1" PORT="S00_ARESETN"/>
<CONNECTION INSTANCE="wrc_1p_kintex7_0" PORT="s00_axi_aresetn"/>
</CONNECTIONS>
</PORT>
</PORTS>
......
FASEC_prototype.srcs/sources_1/bd/system_design/hw_handoff/system_design_bd.tcl
View file @ 08ab5dcf
......@@ -247,7 +247,7 @@ CONFIG.C_S_AXI_ACLK_FREQ_HZ.VALUE_SRC {DEFAULT} \
set axi_wb_i2c_master_2 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.1.1 axi_wb_i2c_master_2 ]
# Create instance: fasec_hwtest_0, and set properties
set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.0 fasec_hwtest_0 ]
set fasec_hwtest_0 [ create_bd_cell -type ip -vlnv user.org:user:fasec_hwtest:3.2.1 fasec_hwtest_0 ]
set_property -dict [ list \
CONFIG.g_FMC1 {EDA-03287} \
CONFIG.g_FMC2 {EDA-03287} \
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_0/system_design_auto_pc_0.xml
View file @ 08ab5dcf
......@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_1/system_design_auto_pc_1.xml
View file @ 08ab5dcf
......@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_auto_pc_2/system_design_auto_pc_2.xml
View file @ 08ab5dcf
......@@ -1055,7 +1055,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1085,7 +1085,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1116,7 +1116,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1162,7 +1162,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......@@ -1193,7 +1193,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Thu Apr 13 07:58:22 UTC 2017</spirit:value>
<spirit:value>Thu May 11 14:53:08 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/sim/system_design_fasec_hwtest_0_0.vhd
View file @ 08ab5dcf
......@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:fasec_hwtest:3.2.0
-- IP Revision: 27
-- IP VLNV: user.org:user:fasec_hwtest:3.2.1
-- IP Revision: 29
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/synth/system_design_fasec_hwtest_0_0.vhd
View file @ 08ab5dcf
......@@ -46,8 +46,8 @@
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:fasec_hwtest:3.2.0
-- IP Revision: 27
-- IP VLNV: user.org:user:fasec_hwtest:3.2.1
-- IP Revision: 29
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
View file @ 08ab5dcf
......@@ -7,7 +7,7 @@
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>system_design_fasec_hwtest_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.0"/>
<spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
......@@ -61,7 +61,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">27</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
......
FASEC_prototype.ip_user_files/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd → FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/general_fmc.vhd
View file @ 08ab5dcf
......@@ -6,7 +6,7 @@
-- Author : Pieter Van Trappen <pvantrap@cern.ch>
-- Company : CERN
-- Created : 2016-11-22
-- Last update: 2017-04-12
-- Last update: 2017-05-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
......@@ -112,6 +112,7 @@ architecture rtl of general_fmc is
type t_cmplengths is array (0 to c_COMP-1) of std_logic_vector(c_COUNTERWIDTH-1 downto 0);
signal s_cmp_lengths : t_cmplengths;
signal s_diffouts_o : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outleds : std_logic_vector(c_DOUTS-1 downto 0);
signal s_outsfeedbak_i : std_logic_vector(c_OUTFBD-1 downto 0);
signal s_spi_sclk : std_logic;
signal s_spi_mosi : std_logic;
......@@ -201,6 +202,7 @@ begin
-- outputs loop
fmc_03287_obufds : for I in 0 to c_DOUTS-1 generate
gen_outs : if g_FMC = "EDA-03287" generate
-- output LVDS buffers
cmp_OBUFDS_fmc : OBUFDS
generic map (
-- IOSTANDARD => "LVDS_25", -- Specify the output I/O standard
......@@ -209,6 +211,24 @@ begin
O => FMC_LA_P_b(c_COMP+I), -- Diff_p output (connect directly to top-level port)
OB => FMC_LA_N_b(c_COMP+I), -- Diff_n output (connect directly to top-level port)
I => s_diffouts_o(I)); -- Buffer input
-- pulse extenders for LEDs
cmp_outs_pulseMeasure : pulseMeasure
generic map (
g_COUNTERWIDTH => c_COUNTERWIDTH,
g_LEDCOUNTERWIDTH => c_LEDCOUNTERWIDTH,
g_LEDWAIT => 10000000, -- 100ms when 10ns clock
g_MISSINGCDC => false)
port map (
clk_dsp_i => clk_i, -- for now no clock domain crossing
reset_n_i => s_reset_n,
pulse_i => s_diffouts_o(I),
missingWindow_i => to_unsigned(0, c_LEDCOUNTERWIDTH),
pulse_o => open,
edgeDetected_o => open,
usrLed_o => s_outleds(I),
window_o => open,
pulseLength_o => open,
LedCount_o => open);
end generate gen_outs;
end generate fmc_03287_obufds;
-- SPI DAC for comparator reference
......@@ -270,6 +290,7 @@ begin
variable v_cmpled : std_logic_vector(c_COMP-1 downto 0);
variable v_dout : std_logic_vector(c_DOUTS-1 downto 0);
variable v_fbd : std_logic_vector(c_OUTFBD-1 downto 0);
variable v_outleds : std_logic_vector(c_DOUTS-1 downto 0);
begin
if g_FMC = "EDA-03287" and rising_edge(clk_i) then
-- in/outputs
......@@ -284,7 +305,7 @@ begin
else
intr_o <= '0';
end if;
if (v_cmpled /= s_compleds) then
if (v_cmpled /= s_compleds) or (v_outleds /= s_outleds) then
intr_led_o <= '1';
else
intr_led_o <= '0';
......@@ -292,6 +313,7 @@ begin
-- clocking in data for above interrupt generation
v_cmpled := s_compleds(c_COMP-1 downto 0);
v_cmp := s_cmp_pulse(c_COMP-1 downto 0);
v_outleds := s_outleds(c_DOUTS-1 downto 0);
end if;
end process p_fmc_03287_io;
-- no additional clocking of comparators & LEDs
......
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd → FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_1/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
View file @ 08ab5dcf
......@@ -294,8 +294,8 @@ begin
s_data(c_FASEC_BASE+1) <= resize(unsigned(s_ins), g_S00_AXI_DATA_WIDTH);
s_data(c_FASEC_BASE+2) <= resize(unsigned(gem_status_vector_i), g_S00_AXI_DATA_WIDTH);
-- s_data(c_FASEC_BASE+3).data used in p_fasec_dio
s_data(c_FASEC_BASE+6) <= x"58EF3049"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"fbf1ca09"; -- tcl-script will put git commit id
s_data(c_FASEC_BASE+6) <= x"DEADBEE1"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"DEADBEE2"; -- tcl-script will put git commit id
-- copy in rw data, 'for generate' only possible with constants!
gen_data_readwrite : for i in 0 to c_MEMMAX-1 generate
gen_fasec : if c_FASECMEM(i).ro = '0' generate
......@@ -452,4 +452,3 @@ begin
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready);
end rtl;
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
View file @ 08ab5dcf
......@@ -704,15 +704,6 @@
<spirit:configurableElementValue spirit:referenceId="appcore">xilinx.com:ip:axi_interconnect:2.1</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>fasec_hwtest_0</spirit:instanceName>
<spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_fasec_hwtest_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="g_FMC1">EDA-03287</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="g_FMC2">EDA-03287</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>axi_wb_i2c_master_0</spirit:instanceName>
<spirit:componentRef spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:vendor="cern.ch" spirit:version="3.1.1"/>
......@@ -734,6 +725,15 @@
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_wrc_1p_kintex7_0_0</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>fasec_hwtest_0</spirit:instanceName>
<spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_fasec_hwtest_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="g_FMC1">EDA-03287</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="g_FMC2">EDA-03287</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
<spirit:interconnections>
<spirit:interconnection>
......@@ -811,8 +811,8 @@
<spirit:adHocConnection>
<spirit:name>pb_gp_i_1</spirit:name>
<spirit:externalPortReference spirit:portRef="pb_gp_i"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="pb_gp_n_i"/>
<spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="button_rst_n_i"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="pb_gp_n_i"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>fasec_hwtest_0_led_col_pl_o</spirit:name>
......@@ -843,8 +843,8 @@
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="m_axi_s2mm_aclk"/>
<spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axis_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="ps_clk_i"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ACLK"/>
......@@ -858,8 +858,8 @@
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="M00_ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="ps_clk_i"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aclk"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>processing_system7_0_FCLK_RESET0_N</spirit:name>
......@@ -875,7 +875,8 @@
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="axi_resetn"/>
<spirit:internalPortReference spirit:componentRef="xadc_axis_fifo_adapter_0" spirit:portRef="AXIS_RESET_N"/>
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="S00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M05_ARESETN"/>
......@@ -888,8 +889,7 @@
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ARESETN"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aresetn"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>Net</spirit:name>
......@@ -1134,9 +1134,9 @@
<spirit:adHocConnection>
<spirit:name>rst_wrc_1p_kintex7_0_62M_peripheral_aresetn</spirit:name>
<spirit:internalPortReference spirit:componentRef="rst_wrc_1p_kintex7_0_62M" spirit:portRef="peripheral_aresetn"/>
<spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="M00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="S00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="s00_axi_aresetn"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>rst_wrc_1p_kintex7_0_62M_interconnect_aresetn</spirit:name>
......@@ -4992,12 +4992,6 @@
<spirit:addressOffset>0x40400000</spirit:addressOffset>
<spirit:range>64K</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>SEG_fasec_hwtest_0_S00_AXI_reg</spirit:name>
<spirit:displayName>/fasec_hwtest_0/S00_AXI/S00_AXI_reg</spirit:displayName>
<spirit:addressOffset>0x43C30000</spirit:addressOffset>
<spirit:range>64K</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>SEG_axi_wb_i2c_master_0_Reg</spirit:name>
<spirit:displayName>/axi_wb_i2c_master_0/s00_axi/Reg</spirit:displayName>
......@@ -5016,6 +5010,12 @@
<spirit:addressOffset>0x80000000</spirit:addressOffset>
<spirit:range>64K</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>SEG_fasec_hwtest_0_S00_AXI_reg</spirit:name>
<spirit:displayName>/fasec_hwtest_0/S00_AXI/S00_AXI_reg</spirit:displayName>
<spirit:addressOffset>0x43C30000</spirit:addressOffset>
<spirit:range>64K</spirit:range>
</spirit:segment>
</spirit:segments>
</spirit:addressSpace>
</spirit:addressSpaces>
......
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
View file @ 08ab5dcf
......@@ -2,9 +2,9 @@
<Root MajorVersion="0" MinorVersion="33">
<CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="true" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1492070306"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1492070306"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1492070306"/>
<Generation Name="SYNTHESIS" State="GENERATED" Timestamp="1494514392"/>
<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1494514392"/>
<Generation Name="SIMULATION" State="GENERATED" Timestamp="1494514392"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
......@@ -23,7 +23,6 @@
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0_axi_periph"/>
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
......@@ -79,7 +78,6 @@
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci" Type="IP">
<Instance HierarchyPath="axi_interconnect_0"/>
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
......@@ -143,13 +141,18 @@
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci" Type="IP">
<Instance HierarchyPath="axi_interconnect_1"/>
<Properties IsEditable="false" IsVisible="false" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="hdl/system_design.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci" Type="IP">
<Instance HierarchyPath="axi_interconnect_0/s00_couplers/auto_pc"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
......@@ -174,12 +177,6 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="hdl/system_design.vhd" Type="VHDL">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="system_design_ooc.xdc" Type="XDC">
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
<Library Name="xil_defaultlib"/>
......
FASEC_prototype.xpr
View file @ 08ab5dcf
......@@ -10,12 +10,12 @@
<Option Name="Part" Val="xc7z030ffg676-2"/>
<Option Name="CompiledLibDir" Val="$PPRDIR/../../../../../../local/EDA/xilinx_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="CompiledLibDirModelSim" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/ies"/>
<Option Name="CompiledLibDirVCS" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="/home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.cache/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
......@@ -36,13 +36,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="76"/>
<Option Name="WTModelSimExportSim" Val="76"/>
<Option Name="WTQuestaExportSim" Val="76"/>
<Option Name="WTIesExportSim" Val="76"/>
<Option Name="WTVcsExportSim" Val="76"/>
<Option Name="WTRivieraExportSim" Val="76"/>
<Option Name="WTActivehdlExportSim" Val="76"/>
<Option Name="WTXSimExportSim" Val="77"/>
<Option Name="WTModelSimExportSim" Val="77"/>
<Option Name="WTQuestaExportSim" Val="77"/>
<Option Name="WTIesExportSim" Val="77"/>
<Option Name="WTVcsExportSim" Val="77"/>
<Option Name="WTRivieraExportSim" Val="77"/>
<Option Name="WTActivehdlExportSim" Val="77"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
......@@ -53,6 +53,25 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_processing_system7_0_100M_2/system_design_rst_processing_system7_0_100M_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_6_0/system_design_xlconstant_6_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_processing_system7_0_axi_periph_3/system_design_processing_system7_0_axi_periph_3.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.vhd"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_1_0/system_design_axi_interconnect_1_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_rst_wrc_1p_kintex7_0_62M_0/system_design_rst_wrc_1p_kintex7_0_62M_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci"/>
</File>
<File Path="$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd">
<FileInfo>
......
ip_upgrade.log
View file @ 08ab5dcf
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
| Date : Thu May 11 16:52:53 2017
| Host : lapte24154 running 64-bit openSUSE Leap 42.1 (x86_64)
| Command : upgrade_ip
| Device : xc7z030ffg676-2
------------------------------------------------------------------------------------
Upgrade Log for IP 'system_design_fasec_hwtest_0_0'
1. Summary
----------
SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.0 (Rev. 27) to user.org:user:fasec_hwtest:3.2.1 (Rev. 29)
Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
......
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