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FPGA and ARM SoC FMC Carrier FASEC
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FPGA and ARM SoC FMC Carrier FASEC
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231d69ec
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231d69ec
authored
Apr 09, 2019
by
Pieter Van Trappen
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readme updated ref. wrpc
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@@ -10,17 +10,27 @@ The following has been tested so far:
*
DDR3 full range
*
FMCs I2C bus
*
PL output LEDs
*
White Rabbit PTP Core
[
https://www.ohwr.org/project/wr-cores/wikis/wrpc-core
]
*
White Rabbit PTP Core
*
(much more, lost track of updating this document)
The project itself is not uploaded, to recreate it after cloning the repo:
$ git submodule update --init --recursive
$ vivado -mode batch -source syn/fasec_prototype_project-generation.tcl
```
git submodule update --init --recursive
vivado -mode batch -source syn/fasec_prototype_project-generation.tcl
```
Now the project can be openend with Vivado. There's a hacky script to update
some fasec_hwtest AXI4-Lite registers to include build time and commit
number. To use, run bitstream generation as follows from the Tcl Console:
> cd [get_property DIRECTORY [current_project]]; source FASEC_prototype.srcs/tcl/set_registers.tcl
```
cd [get_property DIRECTORY [current_project]]; source FASEC_prototype.srcs/tcl/set_registers.tcl
```
### White Rabbit PTP Core
The PTPC submodule used is an obsolete design, ported from sevensols wrc-2p, and hosted in bitbucket.org. This
was done cause at that time there was no official Xilinx Zynq/Artix support at the wrpc-core. Even though the gateware
has been tested and works fine, one should really use the design from the official repository.
https://www.ohwr.org/project/wr-cores/wikis/wrpc-core
## Petalinux
Petalinux 2018.1 (OE/Yocto based) is used for the software-side of the project. To facilitate integration
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