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F
FPGA and ARM SoC FMC Carrier FASEC
Commit 2a3066fe authored by Pieter Van Trappen's avatar Pieter Van Trappen
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after synthesis with new lm32 ws

parent 0fd272b3
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Showing with 9 additions and 2 deletions
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_4/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
View file @ 2a3066fe
......@@ -294,8 +294,8 @@ begin
s_data(c_FASEC_BASE+1) <= resize(unsigned(s_ins), g_S00_AXI_DATA_WIDTH);
s_data(c_FASEC_BASE+2) <= resize(unsigned(gem_status_vector_i), g_S00_AXI_DATA_WIDTH);
-- s_data(c_FASEC_BASE+3).data used in p_fasec_dio
s_data(c_FASEC_BASE+6) <= x"5919B0E0"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"d5590770"; -- tcl-script will put git commit id
s_data(c_FASEC_BASE+6) <= x"59252712"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"0fd272b3"; -- tcl-script will put git commit id
-- copy in rw data, 'for generate' only possible with constants!
gen_data_readwrite : for i in 0 to c_MEMMAX-1 generate
gen_fasec : if c_FASECMEM(i).ro = '0' generate
......
FASEC_prototype.xpr
View file @ 2a3066fe
......@@ -62,6 +62,8 @@
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_uartlite_0_0/system_design_axi_uartlite_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_wrc_1p_kintex7_0_0/system_design_wrc_1p_kintex7_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconcat_0_0/system_design_xlconcat_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hdl/system_design.hwdef"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design.hwh"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_axis_fifo_adapter_0_0/system_design_xadc_axis_fifo_adapter_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_dma_0_0/system_design_axi_dma_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_axi_interconnect_0_0/system_design_axi_interconnect_0_0.xci"/>
......@@ -72,6 +74,11 @@
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xbar_0/system_design_xbar_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xlconstant_3_2/system_design_xlconstant_3_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_0/system_design_auto_pc_0.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_1/system_design_auto_pc_1.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="ip/system_design_auto_pc_2/system_design_auto_pc_2.xci"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="system_design_ooc.xdc"/>
<CompFileExtendedInfo CompFileName="system_design.bd" FileRelPathName="hw_handoff/system_design_bd.tcl"/>
</File>
<File Path="$PSRCDIR/sources_1/bd/system_design/hdl/system_design_wrapper.vhd">
<FileInfo>
......
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