Skip to content

F
FPGA and ARM SoC FMC Carrier FASEC
Commit 7775770f authored by Pieter Van Trappen's avatar Pieter Van Trappen
Browse files
Options

block-design modified for testing FMC1 external i2c connection (to patch-panel): 

* axi_wb_i2c_master_1 removed
* mdio_spi now connected to an utility buffer instead of i2c_master
* external i2c connection at axi_wb_i2c_master_0
* tcl script modified to run all unfinished OOC runs, however not in parallel
* bitstream and hdf generated; tcl build script updated
parent b2a8f4f0
Hide whitespace changes
Inline Side-by-side
Showing with 2518 additions and 319 deletions
.gitignore
View file @ 7775770f
......@@ -4,3 +4,4 @@ RemoteSystemsTempFiles/**
*.o
*.elf
*.tmp/
vivado*
FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc
View file @ 7775770f
set_property ASYNC_REG true [get_cells {system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d0_reg}]
set_property ASYNC_REG true [get_cells {system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d3_reg}]
set_property ASYNC_REG true [get_cells {system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d0_reg}]
set_property ASYNC_REG true [get_cells {system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d3_reg}]
set_property PACKAGE_PIN Y16 [get_ports {led_col_pl_o[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led_col_pl_o[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {led_col_pl_o[1]}]
......@@ -30,8 +34,6 @@ set_property PACKAGE_PIN Y12 [get_ports {FMC1_LA_P_b[2]}]
set_property PACKAGE_PIN AB12 [get_ports {FMC1_LA_P_b[3]}]
set_property PACKAGE_PIN Y10 [get_ports {FMC1_LA_P_b[4]}]
set_property PACKAGE_PIN W13 [get_ports {FMC1_LA_P_b[5]}]
set_property PACKAGE_PIN AF19 [get_ports {FMC1_LA_P_b[22]}]
set_property PACKAGE_PIN AD18 [get_ports {FMC1_LA_P_b[23]}]
set_property PACKAGE_PIN AE13 [get_ports {FMC1_LA_P_b[7]}]
set_property PACKAGE_PIN AE10 [get_ports {FMC1_LA_P_b[8]}]
set_property PACKAGE_PIN AE11 [get_ports {FMC1_LA_P_b[9]}]
......@@ -41,20 +43,13 @@ set_property PACKAGE_PIN AF15 [get_ports {FMC1_LA_P_b[13]}]
set_property PACKAGE_PIN AD23 [get_ports {FMC1_LA_P_b[17]}]
set_property PACKAGE_PIN AC21 [get_ports {FMC1_LA_P_b[18]}]
set_property PACKAGE_PIN AE18 [get_ports {FMC1_LA_P_b[19]}]
set_property PACKAGE_PIN W18 [get_ports {FMC1_LA_P_b[20]}]
set_property PACKAGE_PIN AE22 [get_ports {FMC1_LA_P_b[21]}]
set_property PACKAGE_PIN AD25 [get_ports {FMC1_LA_P_b[24]}]
set_property PACKAGE_PIN AF24 [get_ports {FMC1_LA_P_b[26]}]
set_property PACKAGE_PIN AC18 [get_ports {FMC1_LA_P_b[29]}]
set_property PACKAGE_PIN AB21 [get_ports {FMC1_LA_P_b[30]}]
set_property PACKAGE_PIN AA20 [get_ports {FMC1_LA_P_b[31]}]
set_property PACKAGE_PIN AB11 [get_ports {FMC1_LA_P_b[6]}]
set_property PACKAGE_PIN AE12 [get_ports {FMC1_LA_P_b[10]}]
set_property PACKAGE_PIN AE16 [get_ports {FMC1_LA_P_b[14]}]
set_property PACKAGE_PIN AE17 [get_ports {FMC1_LA_P_b[15]}]
set_property PACKAGE_PIN AD16 [get_ports {FMC1_LA_P_b[16]}]
set_property PACKAGE_PIN AE25 [get_ports {FMC1_LA_P_b[25]}]
set_property PACKAGE_PIN AE23 [get_ports {FMC1_LA_P_b[27]}]
set_property PACKAGE_PIN AB26 [get_ports {FMC1_LA_P_b[28]}]
set_property PACKAGE_PIN AA22 [get_ports {FMC1_LA_P_b[32]}]
set_property PACKAGE_PIN AA25 [get_ports {FMC1_LA_P_b[33]}]
......@@ -65,7 +60,6 @@ set_property PACKAGE_PIN AA25 [get_ports {FMC1_LA_P_b[33]}]
## FMC1 single-ended
set_property PACKAGE_PIN AC26 [get_ports {FMC1_LA_N_b[28]}]
set_property PACKAGE_PIN AC19 [get_ports {FMC1_LA_N_b[29]}]
set_property PACKAGE_PIN AB22 [get_ports {FMC1_LA_N_b[30]}]
set_property PACKAGE_PIN AB20 [get_ports {FMC1_LA_N_b[31]}]
set_property PACKAGE_PIN AA23 [get_ports {FMC1_LA_N_b[32]}]
set_property PACKAGE_PIN AB25 [get_ports {FMC1_LA_N_b[33]}]
......@@ -77,7 +71,6 @@ set_property PACKAGE_PIN AB25 [get_ports {FMC1_LA_N_b[33]}]
set_property PACKAGE_PIN M6 [get_ports {FMC2_LA_P_b[0]}]
set_property PACKAGE_PIN L5 [get_ports {FMC2_LA_P_b[1]}]
set_property PACKAGE_PIN G4 [get_ports {FMC2_LA_P_b[3]}]
set_property PACKAGE_PIN G6 [get_ports {FMC2_LA_P_b[23]}]
set_property PACKAGE_PIN G2 [get_ports {FMC2_LA_P_b[5]}]
set_property PACKAGE_PIN E2 [get_ports {FMC2_LA_P_b[6]}]
set_property PACKAGE_PIN H4 [get_ports {FMC2_LA_P_b[8]}]
......@@ -88,17 +81,11 @@ set_property PACKAGE_PIN M8 [get_ports {FMC2_LA_P_b[15]}]
set_property PACKAGE_PIN N1 [get_ports {FMC2_LA_P_b[16]}]
set_property PACKAGE_PIN F8 [get_ports {FMC2_LA_P_b[17]}]
set_property PACKAGE_PIN D6 [get_ports {FMC2_LA_P_b[18]}]
set_property PACKAGE_PIN A4 [get_ports {FMC2_LA_P_b[21]}]
set_property PACKAGE_PIN E6 [get_ports {FMC2_LA_P_b[24]}]
set_property PACKAGE_PIN F9 [get_ports {FMC2_LA_P_b[29]}]
set_property PACKAGE_PIN B5 [get_ports {FMC2_LA_P_b[31]}]
set_property PACKAGE_PIN B10 [get_ports {FMC2_LA_P_b[32]}]
set_property PACKAGE_PIN A9 [get_ports {FMC2_LA_P_b[33]}]
set_property PACKAGE_PIN B6 [get_ports {FMC2_LA_P_b[30]}]
set_property PACKAGE_PIN J10 [get_ports {FMC2_LA_P_b[26]}]
set_property PACKAGE_PIN J11 [get_ports {FMC2_LA_P_b[25]}]
set_property PACKAGE_PIN H7 [get_ports {FMC2_LA_P_b[22]}]
set_property PACKAGE_PIN C2 [get_ports {FMC2_LA_P_b[20]}]
set_property PACKAGE_PIN B2 [get_ports {FMC2_LA_P_b[19]}]
set_property PACKAGE_PIN M2 [get_ports {FMC2_LA_P_b[13]}]
set_property PACKAGE_PIN N4 [get_ports {FMC2_LA_P_b[11]}]
......@@ -117,18 +104,25 @@ set_property IOSTANDARD LVDS [get_ports {FMC2_LA_N_b[27]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[27]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[26]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_N_b[26]}]
set_property PACKAGE_PIN J10 [get_ports {FMC2_LA_P_b[26]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[25]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_N_b[25]}]
set_property PACKAGE_PIN J11 [get_ports {FMC2_LA_P_b[25]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[24]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_N_b[24]}]
set_property PACKAGE_PIN E6 [get_ports {FMC2_LA_P_b[24]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[23]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_N_b[23]}]
set_property PACKAGE_PIN G6 [get_ports {FMC2_LA_P_b[23]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[22]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_N_b[22]}]
set_property PACKAGE_PIN H7 [get_ports {FMC2_LA_P_b[22]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[21]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_N_b[21]}]
set_property PACKAGE_PIN A4 [get_ports {FMC2_LA_P_b[21]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[20]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_N_b[20]}]
set_property PACKAGE_PIN C2 [get_ports {FMC2_LA_P_b[20]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[19]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_N_b[19]}]
set_property IOSTANDARD LVDS [get_ports {FMC2_LA_P_b[17]}]
......@@ -228,13 +222,21 @@ set_property IOSTANDARD LVCMOS25 [get_ports {FMC1_LA_P_b[30]}]
set_property IOSTANDARD LVCMOS25 [get_ports {FMC1_LA_P_b[29]}]
set_property IOSTANDARD LVCMOS25 [get_ports {FMC1_LA_P_b[28]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[27]}]
set_property PACKAGE_PIN AE23 [get_ports {FMC1_LA_P_b[27]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[26]}]
set_property PACKAGE_PIN AF24 [get_ports {FMC1_LA_P_b[26]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[25]}]
set_property PACKAGE_PIN AE25 [get_ports {FMC1_LA_P_b[25]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[24]}]
set_property PACKAGE_PIN AD25 [get_ports {FMC1_LA_P_b[24]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[23]}]
set_property PACKAGE_PIN AD18 [get_ports {FMC1_LA_P_b[23]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[22]}]
set_property PACKAGE_PIN AF19 [get_ports {FMC1_LA_P_b[22]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[21]}]
set_property PACKAGE_PIN AE22 [get_ports {FMC1_LA_P_b[21]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[20]}]
set_property PACKAGE_PIN W18 [get_ports {FMC1_LA_P_b[20]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[19]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[18]}]
set_property IOSTANDARD LVDS_25 [get_ports {FMC1_LA_P_b[16]}]
......@@ -280,8 +282,6 @@ set_property IOSTANDARD LVCMOS25 [get_ports dig_in4_n_i]
set_property PACKAGE_PIN AA19 [get_ports watchdog_pl_o]
set_property IOSTANDARD LVCMOS25 [get_ports watchdog_pl_o]
set_clock_groups -name FCLKCLK0 -logically_exclusive -group [get_clocks axi_aclk] -group [get_clocks clk_fpga_0] -group [get_clocks clock_axi]
set_property PACKAGE_PIN P13 [get_ports Vp_Vn_v_n]
set_property IOSTANDARD LVCMOS18 [get_ports Vaux0_v_n]
set_property IOSTANDARD LVCMOS18 [get_ports Vaux1_v_n]
......@@ -325,35 +325,15 @@ set_property IOSTANDARD LVCMOS18 [get_ports gtp_wr_tx_disable]
set_property IOSTANDARD LVCMOS18 [get_ports gtp_wr_tx_fault]
set_property IOSTANDARD LVCMOS18 [get_ports gtp_wr_rx_los]
set_property IOSTANDARD LVCMOS18 [get_ports gtp_wr_mod_abs]
create_clock -period 50.000 -name wr_25m -waveform {0.000 25.000} [get_ports clk_25m_vcxo_i]
create_clock -period 8.000 -name wr_125M_sfp -waveform {0.000 4.000} [get_ports gtp_dedicated_clk_p_i]
create_clock -period 8.000 -name system_design_i/wrc_1p_kintex7_0/U0/U_GTP/U_GTX_INST/I -waveform {0.000 4.000} [get_pins system_design_i/wrc_1p_kintex7_0/U0/U_GTP/U_GTX_INST/gtxe2_i/TXOUTCLK]
create_clock -period 8.000 -name system_design_i/wrc_1p_kintex7_0/U0/U_GTP/U_GTX_INST/rx_rec_clk_bufin -waveform {0.000 4.000} [get_pins system_design_i/wrc_1p_kintex7_0/U0/U_GTP/U_GTX_INST/gtxe2_i/RXOUTCLK]
set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks I_1]
set_clock_groups -asynchronous -group [get_clocks clock_ps] -group [get_clocks clock_axi]
set_property ASYNC_REG true [get_cells system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/gen_straight.clk_i_d3_reg]
set_property ASYNC_REG true [get_cells system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/gen_straight.clk_i_d0_reg]
set_clock_groups -asynchronous -group [get_clocks I] -group [get_clocks cmp_dmtd_clk_pll_n_4]
set_property ASYNC_REG true [get_cells {system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d3_reg}]
set_property ASYNC_REG true [get_cells {system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/gen_straight.clk_i_d0_reg}]
set_clock_groups -asynchronous -group [get_clocks system_design_i/wrc_1p_kintex7_0/U0/U_GTP/U_GTX_INST/I] -group [get_clocks cmp_dmtd_clk_pll_n_4]
set_property ASYNC_REG true [get_cells {system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d3_reg}]
set_property ASYNC_REG true [get_cells {system_design_i/wrc_1p_kintex7_0/U0/U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_straight.clk_i_d0_reg}]
set_clock_groups -asynchronous -group [get_clocks system_design_i/wrc_1p_kintex7_0/U0/U_GTP/U_GTX_INST/rx_rec_clk_bufin] -group [get_clocks cmp_dmtd_clk_pll_n_4]
set_property ASYNC_REG true [get_cells system_design_i/wrc_1p_kintex7_0/U0/U_GTP/U_EdgeDet_rst_i/sync_posedge.sync1_reg]
set_property ASYNC_REG true [get_cells system_design_i/wrc_1p_kintex7_0/U0/U_GTP/U_EdgeDet_rst_i/sync_posedge.sync0_reg]
set_clock_groups -asynchronous -group [get_clocks I_1] -group [get_clocks wr_125M_sfp]
set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks I_1]
set_false_path -from [get_clocks cmp_dmtd_clk_pll_n_4] -to [get_clocks I_1]
set_property PACKAGE_PIN AD20 [get_ports i2c_master_fmcx_scl_io]
set_property PACKAGE_PIN AD21 [get_ports i2c_master_fmcx_sda_io]
set_property IOSTANDARD LVCMOS25 [get_ports i2c_master_fmcx_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports i2c_master_fmcx_sda_io]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_master_mdio_scl_io]
set_property PACKAGE_PIN B16 [get_ports i2c_master_mdio_scl_io]
set_property PACKAGE_PIN B15 [get_ports i2c_master_mdio_sda_io]
set_property IOSTANDARD LVCMOS18 [get_ports i2c_master_mdio_sda_io]
set_property IOSTANDARD LVCMOS25 [get_ports i2c_master_fmc_fp_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports i2c_master_fmc_fp_sda_io]
set_property PACKAGE_PIN AB21 [get_ports i2c_master_fmc_fp_scl_io]
set_property PACKAGE_PIN AB22 [get_ports i2c_master_fmc_fp_sda_io]
set_property IOSTANDARD LVDS [get_ports {mdio_spi_P[0]}]
set_property PACKAGE_PIN B16 [get_ports {mdio_spi_P[0]}]
FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
View file @ 7775770f
--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
--Date : Tue Jun 26 20:45:41 2018
--Date : Wed Jul 25 07:58:48 2018
--Host : lapte24154 running 64-bit openSUSE Leap 42.3
--Command : generate_target system_design_wrapper.bd
--Design : system_design_wrapper
......@@ -89,13 +89,15 @@ entity system_design_wrapper is
gtp_wr_tx_fault : in STD_LOGIC;
gtp_wr_txn : out STD_LOGIC;
gtp_wr_txp : out STD_LOGIC;
i2c_master_fmc_fp_scl_io : inout STD_LOGIC;
i2c_master_fmc_fp_sda_io : inout STD_LOGIC;
i2c_master_fmcx_scl_io : inout STD_LOGIC;
i2c_master_fmcx_sda_io : inout STD_LOGIC;
i2c_master_mdio_scl_io : inout STD_LOGIC;
i2c_master_mdio_sda_io : inout STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
led_line_pl_o : out STD_LOGIC;
mdio_spi_N : inout STD_LOGIC_VECTOR ( 0 to 0 );
mdio_spi_P : inout STD_LOGIC_VECTOR ( 0 to 0 );
osc100_clk_i : in STD_LOGIC;
pb_gp_i : in STD_LOGIC;
thermo_id : inout STD_LOGIC;
......@@ -157,12 +159,6 @@ architecture STRUCTURE of system_design_wrapper is
i2c_master_fmcx_sda_o : out STD_LOGIC;
i2c_master_fmcx_sda_i : in STD_LOGIC;
i2c_master_fmcx_sda_t : out STD_LOGIC;
i2c_master_mdio_scl_i : in STD_LOGIC;
i2c_master_mdio_scl_o : out STD_LOGIC;
i2c_master_mdio_scl_t : out STD_LOGIC;
i2c_master_mdio_sda_o : out STD_LOGIC;
i2c_master_mdio_sda_i : in STD_LOGIC;
i2c_master_mdio_sda_t : out STD_LOGIC;
pb_gp_i : in STD_LOGIC;
led_col_pl_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_line_en_pl_o : out STD_LOGIC;
......@@ -200,7 +196,15 @@ architecture STRUCTURE of system_design_wrapper is
eeprom_sda : inout STD_LOGIC;
gtp_dedicated_clk_p_i : in STD_LOGIC;
gtp_dedicated_clk_n_i : in STD_LOGIC;
dig_out6_n : out STD_LOGIC_VECTOR ( 0 to 0 )
dig_out6_n : out STD_LOGIC_VECTOR ( 0 to 0 );
mdio_spi_P : inout STD_LOGIC_VECTOR ( 0 to 0 );
mdio_spi_N : inout STD_LOGIC_VECTOR ( 0 to 0 );
i2c_master_fmc_fp_scl_i : in STD_LOGIC;
i2c_master_fmc_fp_scl_o : out STD_LOGIC;
i2c_master_fmc_fp_scl_t : out STD_LOGIC;
i2c_master_fmc_fp_sda_o : out STD_LOGIC;
i2c_master_fmc_fp_sda_i : in STD_LOGIC;
i2c_master_fmc_fp_sda_t : out STD_LOGIC
);
end component system_design;
component IOBUF is
......@@ -211,19 +215,33 @@ architecture STRUCTURE of system_design_wrapper is
IO : inout STD_LOGIC
);
end component IOBUF;
signal i2c_master_fmc_fp_scl_i : STD_LOGIC;
signal i2c_master_fmc_fp_scl_o : STD_LOGIC;
signal i2c_master_fmc_fp_scl_t : STD_LOGIC;
signal i2c_master_fmc_fp_sda_i : STD_LOGIC;
signal i2c_master_fmc_fp_sda_o : STD_LOGIC;
signal i2c_master_fmc_fp_sda_t : STD_LOGIC;
signal i2c_master_fmcx_scl_i : STD_LOGIC;
signal i2c_master_fmcx_scl_o : STD_LOGIC;
signal i2c_master_fmcx_scl_t : STD_LOGIC;
signal i2c_master_fmcx_sda_i : STD_LOGIC;
signal i2c_master_fmcx_sda_o : STD_LOGIC;
signal i2c_master_fmcx_sda_t : STD_LOGIC;
signal i2c_master_mdio_scl_i : STD_LOGIC;
signal i2c_master_mdio_scl_o : STD_LOGIC;
signal i2c_master_mdio_scl_t : STD_LOGIC;
signal i2c_master_mdio_sda_i : STD_LOGIC;
signal i2c_master_mdio_sda_o : STD_LOGIC;
signal i2c_master_mdio_sda_t : STD_LOGIC;
begin
i2c_master_fmc_fp_scl_iobuf: component IOBUF
port map (
I => i2c_master_fmc_fp_scl_o,
IO => i2c_master_fmc_fp_scl_io,
O => i2c_master_fmc_fp_scl_i,
T => i2c_master_fmc_fp_scl_t
);
i2c_master_fmc_fp_sda_iobuf: component IOBUF
port map (
I => i2c_master_fmc_fp_sda_o,
IO => i2c_master_fmc_fp_sda_io,
O => i2c_master_fmc_fp_sda_i,
T => i2c_master_fmc_fp_sda_t
);
i2c_master_fmcx_scl_iobuf: component IOBUF
port map (
I => i2c_master_fmcx_scl_o,
......@@ -238,20 +256,6 @@ i2c_master_fmcx_sda_iobuf: component IOBUF
O => i2c_master_fmcx_sda_i,
T => i2c_master_fmcx_sda_t
);
i2c_master_mdio_scl_iobuf: component IOBUF
port map (
I => i2c_master_mdio_scl_o,
IO => i2c_master_mdio_scl_io,
O => i2c_master_mdio_scl_i,
T => i2c_master_mdio_scl_t
);
i2c_master_mdio_sda_iobuf: component IOBUF
port map (
I => i2c_master_mdio_sda_o,
IO => i2c_master_mdio_sda_io,
O => i2c_master_mdio_sda_i,
T => i2c_master_mdio_sda_t
);
system_design_i: component system_design
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
......@@ -330,21 +334,23 @@ system_design_i: component system_design
gtp_wr_tx_fault => gtp_wr_tx_fault,
gtp_wr_txn => gtp_wr_txn,
gtp_wr_txp => gtp_wr_txp,
i2c_master_fmc_fp_scl_i => i2c_master_fmc_fp_scl_i,
i2c_master_fmc_fp_scl_o => i2c_master_fmc_fp_scl_o,
i2c_master_fmc_fp_scl_t => i2c_master_fmc_fp_scl_t,
i2c_master_fmc_fp_sda_i => i2c_master_fmc_fp_sda_i,
i2c_master_fmc_fp_sda_o => i2c_master_fmc_fp_sda_o,
i2c_master_fmc_fp_sda_t => i2c_master_fmc_fp_sda_t,
i2c_master_fmcx_scl_i => i2c_master_fmcx_scl_i,
i2c_master_fmcx_scl_o => i2c_master_fmcx_scl_o,
i2c_master_fmcx_scl_t => i2c_master_fmcx_scl_t,
i2c_master_fmcx_sda_i => i2c_master_fmcx_sda_i,
i2c_master_fmcx_sda_o => i2c_master_fmcx_sda_o,
i2c_master_fmcx_sda_t => i2c_master_fmcx_sda_t,
i2c_master_mdio_scl_i => i2c_master_mdio_scl_i,
i2c_master_mdio_scl_o => i2c_master_mdio_scl_o,
i2c_master_mdio_scl_t => i2c_master_mdio_scl_t,
i2c_master_mdio_sda_i => i2c_master_mdio_sda_i,
i2c_master_mdio_sda_o => i2c_master_mdio_sda_o,
i2c_master_mdio_sda_t => i2c_master_mdio_sda_t,
led_col_pl_o(3 downto 0) => led_col_pl_o(3 downto 0),
led_line_en_pl_o => led_line_en_pl_o,
led_line_pl_o => led_line_pl_o,
mdio_spi_N(0) => mdio_spi_N(0),
mdio_spi_P(0) => mdio_spi_P(0),
osc100_clk_i => osc100_clk_i,
pb_gp_i => pb_gp_i,
thermo_id => thermo_id,
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci
View file @ 7775770f
......@@ -96,7 +96,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml
View file @ 7775770f
......@@ -1052,7 +1052,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci
View file @ 7775770f
......@@ -96,7 +96,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml
View file @ 7775770f
......@@ -1052,7 +1052,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
View file @ 7775770f
......@@ -102,7 +102,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.g_FMC1" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.g_FMC2" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
View file @ 7775770f
......@@ -1462,7 +1462,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.g_FMC1" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.g_FMC2" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_1_0/system_design_axi_wb_i2c_master_1_0.xci → FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_util_ds_buf_0_0/system_design_util_ds_buf_0_0.xci
View file @ 7775770f
......@@ -6,47 +6,73 @@
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>system_design_axi_wb_i2c_master_1_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="cern.ch" spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:version="3.2.0"/>
<spirit:instanceName>system_design_util_ds_buf_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="util_ds_buf" spirit:version="2.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN">system_design_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN">system_design_processing_system7_0_0_FCLK_CLK0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S00_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_design_axi_wb_i2c_master_1_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_I.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_O.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_O.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_O.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_O.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFGCE_O.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_I.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_O.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_O.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_O.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_O.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_GT_O.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_I.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_O.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_O.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_O.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_O.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUFG_O.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN_D.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN_D.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_DS_ODIV2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_DS_ODIV2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_DS_ODIV2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_DS_ODIV2.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_DS_ODIV2.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_OUT.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_OUT.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_OUT.CLK_DOMAIN">system_design_util_ds_buf_0_0_IBUF_OUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_OUT.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IBUF_OUT.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_N.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_N.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_N.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_N.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_N.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_P.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_P.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_P.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_P.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_DS_P.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_IN.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_IN.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_IN.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_IN.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.OBUF_IN.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BUF_TYPE">IOBUFDS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BUF_TYPE">IOBUFDS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SIZE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_design_util_ds_buf_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z030</spirit:configurableElementValue>
......@@ -70,33 +96,9 @@
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.MAX_BURST_LENGTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.IBUF_OUT.CLK_DOMAIN" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BUF_TYPE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SIZE" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci
View file @ 7775770f
......@@ -341,9 +341,9 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
......@@ -351,15 +351,15 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xml
View file @ 7775770f
......@@ -4694,9 +4694,9 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
......@@ -4704,15 +4704,15 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xbar_0/system_design_xbar_0.xci
View file @ 7775770f
......@@ -988,8 +988,8 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONNECTIVITY_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_ADDR_WIDTH">0x0000001000000010000000100000001000000010000000100000001000000010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_BASE_ADDR">0x0000000042c0000000000000404000000000000043c400000000000043c500000000000043c200000000000043c300000000000043c100000000000043c00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_ADDR_WIDTH">0x0000001000000010000000100000001000000000000000100000001000000010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_BASE_ADDR">0x0000000042c0000000000000404000000000000043c400000000000043c50000ffffffffffffffff0000000043c300000000000043c100000000000043c00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_READ_CONNECTIVITY">0x0000000100000001000000010000000100000001000000010000000100000001</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_READ_ISSUING">0x0000000100000001000000010000000100000001000000010000000100000001</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_SECURE">0x0000000000000000000000000000000000000000000000000000000000000000</spirit:configurableElementValue>
......@@ -1218,8 +1218,8 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M02_S15_WRITE_CONNECTIVITY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M02_SECURE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M02_WRITE_ISSUING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M03_A00_ADDR_WIDTH">16</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M03_A00_BASE_ADDR">0x0000000043C20000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M03_A00_ADDR_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M03_A00_BASE_ADDR">0xffffffffffffffff</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M03_A01_ADDR_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M03_A01_BASE_ADDR">0xffffffffffffffff</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M03_A02_ADDR_WIDTH">0</spirit:configurableElementValue>
......@@ -2308,7 +2308,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.RUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.BUSER_WIDTH" xilinx:valuePermission="bd"/>
......@@ -2316,18 +2316,18 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_LOCK" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_BURST" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_LOCK" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_QOS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_REGION" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_QOS" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.RUSER_WIDTH" xilinx:valuePermission="bd"/>
......@@ -2568,8 +2568,8 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M02_S15_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A00_ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A00_BASE_ADDR" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_READ_CONNECTIVITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_WRITE_CONNECTIVITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S01_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S01_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S02_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xbar_0/system_design_xbar_0.xml
View file @ 7775770f
......@@ -28235,11 +28235,11 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector">
<spirit:name>C_M_AXI_BASE_ADDR</spirit:name>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_BASE_ADDR" spirit:bitStringLength="512">0x0000000042c0000000000000404000000000000043c400000000000043c500000000000043c200000000000043c300000000000043c100000000000043c00000</spirit:value>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_BASE_ADDR" spirit:bitStringLength="512">0x0000000042c0000000000000404000000000000043c400000000000043c50000ffffffffffffffff0000000043c300000000000043c100000000000043c00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector">
<spirit:name>C_M_AXI_ADDR_WIDTH</spirit:name>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_ADDR_WIDTH" spirit:bitStringLength="256">0x0000001000000010000000100000001000000010000000100000001000000010</spirit:value>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_AXI_ADDR_WIDTH" spirit:bitStringLength="256">0x0000001000000010000000100000001000000000000000100000001000000010</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S_AXI_BASE_ID</spirit:name>
......@@ -37209,7 +37209,7 @@
<spirit:parameter>
<spirit:name>M03_A00_BASE_ADDR</spirit:name>
<spirit:displayName>My M03_A00_BASE_ADDR</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.M03_A00_BASE_ADDR" spirit:order="741" spirit:bitStringLength="64">0x0000000043C20000</spirit:value>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.M03_A00_BASE_ADDR" spirit:order="741" spirit:bitStringLength="64">0xffffffffffffffff</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
......@@ -40281,7 +40281,7 @@
<spirit:parameter>
<spirit:name>M03_A00_ADDR_WIDTH</spirit:name>
<spirit:displayName>My M03_A00_ADDR_WIDTH</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M03_A00_ADDR_WIDTH" spirit:order="997" spirit:minimum="0" spirit:maximum="64" spirit:rangeType="long">16</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.M03_A00_ADDR_WIDTH" spirit:order="997" spirit:minimum="0" spirit:maximum="64" spirit:rangeType="long">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
......@@ -42868,7 +42868,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.RUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M02_AXI.WUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ADDR_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ARUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.AWUSER_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.BUSER_WIDTH" xilinx:valuePermission="bd"/>
......@@ -42876,18 +42876,18 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.DATA_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_LOCK" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_BURST" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_CACHE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_LOCK" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_QOS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_REGION" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_QOS" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_REGION" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.ID_WIDTH" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_READ_OUTSTANDING" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.NUM_WRITE_OUTSTANDING" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.PROTOCOL" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M03_AXI.RUSER_WIDTH" xilinx:valuePermission="bd"/>
......@@ -43128,8 +43128,8 @@
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M02_S15_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A00_ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_A00_BASE_ADDR" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_READ_CONNECTIVITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_WRITE_CONNECTIVITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S00_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S01_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S01_WRITE_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.M03_S02_READ_CONNECTIVITY" xilinx:valuePermission="bd_and_user"/>
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_2_0/system_design_xlconstant_2_0.xci 0 → 100644
View file @ 7775770f
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>system_design_xlconstant_2_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconstant" spirit:version="1.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_VAL">0x1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_VAL">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CONST_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_design_xlconstant_2_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z030</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg676</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_2_0/system_design_xlconstant_2_0.xml 0 → 100644
View file @ 7775770f
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>system_design_xlconstant_2_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:model>
<spirit:ports>
<spirit:port>
<spirit:name>dout</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.CONST_WIDTH&apos;)) - 1)">0</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>dummy_view</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
<spirit:name>CONST_WIDTH</spirit:name>
<spirit:displayName>Const Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_WIDTH">1</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>CONST_VAL</spirit:name>
<spirit:displayName>Const Val</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CONST_VAL" spirit:bitStringLength="1">0x1</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
<spirit:description>Gives a constant signed value.</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="2">system_design_xlconstant_2_0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CONST_WIDTH</spirit:name>
<spirit:displayName>Const Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_WIDTH" spirit:order="3" spirit:minimum="1" spirit:maximum="4096" spirit:rangeType="long">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CONST_VAL</spirit:name>
<spirit:displayName>Const Val</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CONST_VAL" spirit:order="4">1</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>Constant</xilinx:displayName>
<xilinx:coreRevision>4</xilinx:coreRevision>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2018.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3d4b8a9c"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="905deaa3"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0fa77f35"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="f74432fe"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
View file @ 7775770f
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:BoundaryCRC="0xBABF783818D3DF1E" bd:device="xc7z030ffg676-2" bd:isValidated="true" bd:synthFlowMode="Hierarchical" bd:tool_version="2018.1" bd:top="system_design" bd:version="1.00.a">
<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:BoundaryCRC="0x6DD0A7ABE6C1D28A" bd:device="xc7z030ffg676-2" bd:isValidated="true" bd:synthFlowMode="Hierarchical" bd:tool_version="2018.1" bd:top="system_design" bd:version="1.00.a">
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>xilinx.com</spirit:vendor>
......@@ -201,7 +201,7 @@
<spirit:abstractionType spirit:library="interface" spirit:name="iic_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>i2c_master_mdio</spirit:name>
<spirit:name>i2c_master_fmc_fp</spirit:name>
<spirit:master/>
<spirit:busType spirit:library="interface" spirit:name="iic" spirit:vendor="xilinx.com" spirit:version="1.0"/>
<spirit:abstractionType spirit:library="interface" spirit:name="iic_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
......@@ -472,6 +472,26 @@
</spirit:vector>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>mdio_spi_P</spirit:name>
<spirit:wire>
<spirit:direction>inout</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>mdio_spi_N</spirit:name>
<spirit:wire>
<spirit:direction>inout</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
</spirit:port>
</spirit:ports>
</spirit:model>
</spirit:component>
......@@ -1201,13 +1221,6 @@
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_axi_wb_i2c_master_0_1</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>axi_wb_i2c_master_1</spirit:instanceName>
<spirit:componentRef spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:vendor="cern.ch" spirit:version="3.2.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_axi_wb_i2c_master_1_0</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>axi_wb_i2c_master_2</spirit:instanceName>
<spirit:componentRef spirit:library="ip" spirit:name="axi_wb_i2c_master" spirit:vendor="cern.ch" spirit:version="3.2.0"/>
......@@ -1224,6 +1237,22 @@
<spirit:configurableElementValue spirit:referenceId="g_FMC2">EDA-03287</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>util_ds_buf_0</spirit:instanceName>
<spirit:componentRef spirit:library="ip" spirit:name="util_ds_buf" spirit:vendor="xilinx.com" spirit:version="2.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_util_ds_buf_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="C_SIZE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="C_BUF_TYPE">IOBUFDS</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>xlconstant_2</spirit:instanceName>
<spirit:componentRef spirit:library="ip" spirit:name="xlconstant" spirit:vendor="xilinx.com" spirit:version="1.1"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_xlconstant_2_0</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
<spirit:interconnections>
<spirit:interconnection>
......@@ -1296,11 +1325,6 @@
<spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="axi_uartlite_0"/>
<spirit:activeInterface spirit:busRef="M07_AXI" spirit:componentRef="processing_system7_0_axi_periph"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>processing_system7_0_axi_periph_M03_AXI</spirit:name>
<spirit:activeInterface spirit:busRef="M03_AXI" spirit:componentRef="processing_system7_0_axi_periph"/>
<spirit:activeInterface spirit:busRef="s00_axi" spirit:componentRef="axi_wb_i2c_master_1"/>
</spirit:interconnection>
</spirit:interconnections>
<spirit:adHocConnections>
<spirit:adHocConnection>
......@@ -1332,13 +1356,20 @@
<spirit:internalPortReference spirit:componentRef="xadc_axis_fifo_adapter_0" spirit:portRef="M_AXIS_ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="s_axi_lite_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="m_axi_s2mm_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="M_AXI_GP0_ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="S_AXI_GP0_ACLK"/>
<spirit:internalPortReference spirit:componentRef="rst_processing_system7_0_100M" spirit:portRef="slowest_sync_clk"/>
<spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axis_aclk"/>
<spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="ps_clk_i"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="M00_ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="M01_ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="M_AXI_GP0_ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="S_AXI_GP0_ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="S00_ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M00_ACLK"/>
......@@ -1349,14 +1380,6 @@
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M05_ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ACLK"/>
<spirit:internalPortReference spirit:componentRef="rst_processing_system7_0_100M" spirit:portRef="slowest_sync_clk"/>
<spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axis_aclk"/>
<spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_1" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aclk"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="ps_clk_i"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aclk"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>processing_system7_0_FCLK_RESET0_N</spirit:name>
......@@ -1370,11 +1393,15 @@
<spirit:internalPortReference spirit:componentRef="xadc_axis_fifo_adapter_0" spirit:portRef="S_AXI_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="xadc_axis_fifo_adapter_0" spirit:portRef="AXIS_RESET_N"/>
<spirit:internalPortReference spirit:componentRef="axi_dma_0" spirit:portRef="axi_resetn"/>
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="ARESETN"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="S00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_0" spirit:portRef="M00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="M01_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="axi_uartlite_0" spirit:portRef="s_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="S00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M01_ARESETN"/>
......@@ -1384,11 +1411,6 @@
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M05_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M06_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0_axi_periph" spirit:portRef="M07_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="xadc_wiz_0" spirit:portRef="s_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_0" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_1" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_wb_i2c_master_2" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="fasec_hwtest_0" spirit:portRef="s00_axi_aresetn"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>Net4</spirit:name>
......@@ -1604,18 +1626,18 @@
<spirit:adHocConnection>
<spirit:name>wrc_1p_kintex7_0_s00_axi_aclk_o</spirit:name>
<spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="s00_axi_aclk_o"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="M_AXI_GP1_ACLK"/>
<spirit:internalPortReference spirit:componentRef="rst_wrc_1p_kintex7_0_62M" spirit:portRef="slowest_sync_clk"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="S00_ACLK"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="M00_ACLK"/>
<spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="M_AXI_GP1_ACLK"/>
<spirit:internalPortReference spirit:componentRef="rst_wrc_1p_kintex7_0_62M" spirit:portRef="slowest_sync_clk"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>rst_wrc_1p_kintex7_0_62M_peripheral_aresetn</spirit:name>
<spirit:internalPortReference spirit:componentRef="rst_wrc_1p_kintex7_0_62M" spirit:portRef="peripheral_aresetn"/>
<spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="s00_axi_aresetn"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="S00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="axi_interconnect_1" spirit:portRef="M00_ARESETN"/>
<spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="s00_axi_aresetn"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>rst_wrc_1p_kintex7_0_62M_interconnect_aresetn</spirit:name>
......@@ -1677,6 +1699,22 @@
<spirit:internalPortReference spirit:componentRef="xlconstant_1" spirit:portRef="dout"/>
<spirit:internalPortReference spirit:componentRef="wrc_1p_kintex7_0" spirit:portRef="pps_i"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>xlconstant_2_dout</spirit:name>
<spirit:internalPortReference spirit:componentRef="xlconstant_2" spirit:portRef="dout"/>
<spirit:internalPortReference spirit:componentRef="util_ds_buf_0" spirit:portRef="IOBUF_IO_I"/>
<spirit:internalPortReference spirit:componentRef="util_ds_buf_0" spirit:portRef="IOBUF_IO_T"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>Net</spirit:name>
<spirit:externalPortReference spirit:portRef="mdio_spi_P"/>
<spirit:internalPortReference spirit:componentRef="util_ds_buf_0" spirit:portRef="IOBUF_DS_P"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>Net1</spirit:name>
<spirit:externalPortReference spirit:portRef="mdio_spi_N"/>
<spirit:internalPortReference spirit:componentRef="util_ds_buf_0" spirit:portRef="IOBUF_DS_N"/>
</spirit:adHocConnection>
</spirit:adHocConnections>
<spirit:hierConnections>
<spirit:hierConnection spirit:interfaceRef="DDR/processing_system7_0_DDR">
......@@ -1712,8 +1750,8 @@
<spirit:hierConnection spirit:interfaceRef="i2c_master_fmcx/axi_wb_i2c_master_2_i2c_master">
<spirit:activeInterface spirit:busRef="i2c_master" spirit:componentRef="axi_wb_i2c_master_2"/>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="i2c_master_mdio/axi_wb_i2c_master_1_i2c_master">
<spirit:activeInterface spirit:busRef="i2c_master" spirit:componentRef="axi_wb_i2c_master_1"/>
<spirit:hierConnection spirit:interfaceRef="i2c_master_fmc_fp/axi_wb_i2c_master_0_i2c_master">
<spirit:activeInterface spirit:busRef="i2c_master" spirit:componentRef="axi_wb_i2c_master_0"/>
</spirit:hierConnection>
</spirit:hierConnections>
</spirit:design>
......@@ -5968,12 +6006,6 @@
<spirit:addressOffset>0x43C10000</spirit:addressOffset>
<spirit:range>64K</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>SEG_axi_wb_i2c_master_1_Reg</spirit:name>
<spirit:displayName>/axi_wb_i2c_master_1/s00_axi/Reg</spirit:displayName>
<spirit:addressOffset>0x43C20000</spirit:addressOffset>
<spirit:range>64K</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>SEG_axi_wb_i2c_master_2_Reg</spirit:name>
<spirit:displayName>/axi_wb_i2c_master_2/s00_axi/Reg</spirit:displayName>
......
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
View file @ 7775770f
......@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="35">
<CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1530039884"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1530039884"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1530039884"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1530039884"/>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1532500096"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1532500096"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1532500096"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1532500096"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
......@@ -127,14 +127,6 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_axi_wb_i2c_master_1_0/system_design_axi_wb_i2c_master_1_0.xci" Type="IP">
<Instance HierarchyPath="axi_wb_i2c_master_1"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_xbar_0/system_design_xbar_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0_axi_periph/xbar"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
......@@ -167,6 +159,22 @@
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_util_ds_buf_0_0/system_design_util_ds_buf_0_0.xci" Type="IP">
<Instance HierarchyPath="util_ds_buf_0"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_xlconstant_2_0/system_design_xlconstant_2_0.xci" Type="IP">
<Instance HierarchyPath="xlconstant_2"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
<Library Name="xil_defaultlib"/>
<UsedIn Val="SYNTHESIS"/>
<UsedIn Val="IMPLEMENTATION"/>
<UsedIn Val="SIMULATION"/>
</File>
<File Name="ip/system_design_auto_pc_3/system_design_auto_pc_3.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0_axi_periph/s00_couplers/auto_pc"/>
<Properties IsEditable="false" IsVisible="true" Timestamp="0" IsTrackable="true" IsStatusTracked="true"/>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ui/bd_7f01d80e.ui
View file @ 7775770f
......@@ -2,165 +2,170 @@
ExpandedHierarchyInLayout: "",
guistr: "# # String gsaved with Nlview 6.8.5 2018-01-30 bk=1.4354 VDI=40 GEI=35 GUI=JA:1.6 TLS
# -string -flagsOSRD
preplace port FMC1_CLK0M2C_N_i -pg 1 -y 1020 -defaultsOSRD
preplace port led_line_en_pl_o -pg 1 -y 980 -defaultsOSRD
preplace port DDR -pg 1 -y 310 -defaultsOSRD
preplace port clk_25m_vcxo_i -pg 1 -y 1530 -defaultsOSRD
preplace port dig_in3_n_i -pg 1 -y 1080 -defaultsOSRD
preplace port dig_in1_i -pg 1 -y 1040 -defaultsOSRD
preplace port led_line_pl_o -pg 1 -y 1000 -defaultsOSRD
preplace port FMC1_CLK0M2C_N_i -pg 1 -y 1150 -defaultsOSRD
preplace port led_line_en_pl_o -pg 1 -y 1190 -defaultsOSRD
preplace port DDR -pg 1 -y 160 -defaultsOSRD
preplace port clk_25m_vcxo_i -pg 1 -y 1920 -defaultsOSRD
preplace port dig_in3_n_i -pg 1 -y 1290 -defaultsOSRD
preplace port dig_in1_i -pg 1 -y 1250 -defaultsOSRD
preplace port led_line_pl_o -pg 1 -y 1210 -defaultsOSRD
preplace port Vp_Vn -pg 1 -y 90 -defaultsOSRD
preplace port eeprom_sda -pg 1 -y 1680 -defaultsOSRD
preplace port gtp_dedicated_clk_n_i -pg 1 -y 1570 -defaultsOSRD
preplace port osc100_clk_i -pg 1 -y 940 -defaultsOSRD
preplace port eeprom_sda -pg 1 -y 2060 -defaultsOSRD
preplace port gtp_dedicated_clk_n_i -pg 1 -y 1960 -defaultsOSRD
preplace port osc100_clk_i -pg 1 -y 970 -defaultsOSRD
preplace port Vaux0 -pg 1 -y 110 -defaultsOSRD
preplace port FMC1_CLK0M2C_P_i -pg 1 -y 1000 -defaultsOSRD
preplace port FMC1_CLK0M2C_P_i -pg 1 -y 1130 -defaultsOSRD
preplace port Vaux1 -pg 1 -y 130 -defaultsOSRD
preplace port thermo_id -pg 1 -y 1700 -defaultsOSRD
preplace port dac_cs2_n_o -pg 1 -y 1640 -defaultsOSRD
preplace port FMC2_CLK0M2C_N_i -pg 1 -y 880 -defaultsOSRD
preplace port thermo_id -pg 1 -y 2080 -defaultsOSRD
preplace port dac_cs2_n_o -pg 1 -y 2020 -defaultsOSRD
preplace port FMC2_CLK0M2C_N_i -pg 1 -y 1030 -defaultsOSRD
preplace port Vaux2 -pg 1 -y 150 -defaultsOSRD
preplace port FMC1_CLK0C2M_P_o -pg 1 -y 900 -defaultsOSRD
preplace port FMC2_CLK0M2C_P_i -pg 1 -y 900 -defaultsOSRD
preplace port FMC2_PRSNTM2C_n_i -pg 1 -y 960 -defaultsOSRD
preplace port FMC1_CLK0C2M_P_o -pg 1 -y 1110 -defaultsOSRD
preplace port FMC2_CLK0M2C_P_i -pg 1 -y 1010 -defaultsOSRD
preplace port FMC2_PRSNTM2C_n_i -pg 1 -y 990 -defaultsOSRD
preplace port i2c_master_fmc_fp -pg 1 -y 430 -defaultsOSRD
preplace port Vaux10 -pg 1 -y 210 -defaultsOSRD
preplace port dac_din_o -pg 1 -y 1600 -defaultsOSRD
preplace port FMC1_PRSNTM2C_n_i -pg 1 -y 980 -defaultsOSRD
preplace port gtp_wr -pg 1 -y 1420 -defaultsOSRD
preplace port gtp0_rate_select_b -pg 1 -y 1720 -defaultsOSRD
preplace port i2c_master_fmcx -pg 1 -y 400 -defaultsOSRD
preplace port FIXED_IO -pg 1 -y 330 -defaultsOSRD
preplace port eeprom_scl -pg 1 -y 1660 -defaultsOSRD
preplace port dac_cs1_n_o -pg 1 -y 1620 -defaultsOSRD
preplace port dig_in4_n_i -pg 1 -y 1100 -defaultsOSRD
preplace port dig_in2_i -pg 1 -y 1060 -defaultsOSRD
preplace port watchdog_pl_o -pg 1 -y 1020 -defaultsOSRD
preplace port gtp_dedicated_clk_p_i -pg 1 -y 1550 -defaultsOSRD
preplace port FMC1_CLK0C2M_N_o -pg 1 -y 920 -defaultsOSRD
preplace port pb_gp_i -pg 1 -y 1590 -defaultsOSRD
preplace port i2c_master_mdio -pg 1 -y 560 -defaultsOSRD
preplace port dig_out5_n -pg 1 -y 1060 -defaultsOSRD
preplace port dac_din_o -pg 1 -y 1980 -defaultsOSRD
preplace port FMC1_PRSNTM2C_n_i -pg 1 -y 1110 -defaultsOSRD
preplace port gtp_wr -pg 1 -y 1800 -defaultsOSRD
preplace port gtp0_rate_select_b -pg 1 -y 2100 -defaultsOSRD
preplace port i2c_master_fmcx -pg 1 -y 590 -defaultsOSRD
preplace port FIXED_IO -pg 1 -y 180 -defaultsOSRD
preplace port eeprom_scl -pg 1 -y 2040 -defaultsOSRD
preplace port dac_cs1_n_o -pg 1 -y 2000 -defaultsOSRD
preplace port dig_in4_n_i -pg 1 -y 1310 -defaultsOSRD
preplace port dig_in2_i -pg 1 -y 1270 -defaultsOSRD
preplace port watchdog_pl_o -pg 1 -y 1230 -defaultsOSRD
preplace port gtp_dedicated_clk_p_i -pg 1 -y 1940 -defaultsOSRD
preplace port FMC1_CLK0C2M_N_o -pg 1 -y 1130 -defaultsOSRD
preplace port pb_gp_i -pg 1 -y 1230 -defaultsOSRD
preplace port dig_out5_n -pg 1 -y 1270 -defaultsOSRD
preplace port Vaux8 -pg 1 -y 170 -defaultsOSRD
preplace port dac_sclk_o -pg 1 -y 1580 -defaultsOSRD
preplace port FMC2_CLK0C2M_N_o -pg 1 -y 860 -defaultsOSRD
preplace port FMC2_CLK0C2M_P_o -pg 1 -y 840 -defaultsOSRD
preplace port dac_sclk_o -pg 1 -y 1960 -defaultsOSRD
preplace port FMC2_CLK0C2M_N_o -pg 1 -y 1070 -defaultsOSRD
preplace port FMC2_CLK0C2M_P_o -pg 1 -y 1050 -defaultsOSRD
preplace port Vaux9 -pg 1 -y 190 -defaultsOSRD
preplace portBus FMC1_LA_P_b -pg 1 -y 800 -defaultsOSRD
preplace portBus FMC2_LA_N_b -pg 1 -y 780 -defaultsOSRD
preplace portBus dig_outs_i -pg 1 -y 1040 -defaultsOSRD
preplace portBus dig_out6_n -pg 1 -y 1080 -defaultsOSRD
preplace portBus FMC2_LA_P_b -pg 1 -y 760 -defaultsOSRD
preplace portBus led_col_pl_o -pg 1 -y 960 -defaultsOSRD
preplace portBus FMC1_LA_N_b -pg 1 -y 820 -defaultsOSRD
preplace inst fasec_hwtest_0 -pg 1 -lvl 9 -y 940 -defaultsOSRD
preplace inst axi_dma_0 -pg 1 -lvl 5 -y 410 -defaultsOSRD
preplace inst xlconstant_0 -pg 1 -lvl 8 -y 1160 -defaultsOSRD
preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 780 -defaultsOSRD
preplace inst xadc_axis_fifo_adapter_0 -pg 1 -lvl 4 -y 400 -defaultsOSRD
preplace inst xlconstant_1 -pg 1 -lvl 8 -y 1640 -defaultsOSRD
preplace portBus FMC1_LA_P_b -pg 1 -y 1010 -defaultsOSRD
preplace portBus FMC2_LA_N_b -pg 1 -y 990 -defaultsOSRD
preplace portBus dig_outs_i -pg 1 -y 1250 -defaultsOSRD
preplace portBus dig_out6_n -pg 1 -y 1290 -defaultsOSRD
preplace portBus FMC2_LA_P_b -pg 1 -y 970 -defaultsOSRD
preplace portBus led_col_pl_o -pg 1 -y 1170 -defaultsOSRD
preplace portBus mdio_spi_N -pg 1 -y 1550 -defaultsOSRD
preplace portBus FMC1_LA_N_b -pg 1 -y 1030 -defaultsOSRD
preplace portBus mdio_spi_P -pg 1 -y 1530 -defaultsOSRD
preplace inst fasec_hwtest_0 -pg 1 -lvl 9 -y 1150 -defaultsOSRD
preplace inst axi_dma_0 -pg 1 -lvl 5 -y 580 -defaultsOSRD
preplace inst xlconstant_0 -pg 1 -lvl 8 -y 1370 -defaultsOSRD
preplace inst rst_processing_system7_0_100M -pg 1 -lvl 1 -y 770 -defaultsOSRD
preplace inst xadc_axis_fifo_adapter_0 -pg 1 -lvl 4 -y 550 -defaultsOSRD
preplace inst xlconstant_1 -pg 1 -lvl 8 -y 2020 -defaultsOSRD
preplace inst xadc_wiz_0 -pg 1 -lvl 3 -y 170 -defaultsOSRD
preplace inst wrc_1p_kintex7_0 -pg 1 -lvl 9 -y 1590 -defaultsOSRD
preplace inst xlconcat_0 -pg 1 -lvl 6 -y 680 -defaultsOSRD
preplace inst axi_wb_i2c_master_0 -pg 1 -lvl 3 -y 620 -defaultsOSRD
preplace inst axi_wb_i2c_master_1 -pg 1 -lvl 9 -y 570 -defaultsOSRD
preplace inst axi_wb_i2c_master_2 -pg 1 -lvl 9 -y 410 -defaultsOSRD
preplace inst wrc_1p_kintex7_0 -pg 1 -lvl 9 -y 1970 -defaultsOSRD
preplace inst xlconstant_2 -pg 1 -lvl 8 -y 1540 -defaultsOSRD
preplace inst xlconcat_0 -pg 1 -lvl 6 -y 810 -defaultsOSRD
preplace inst axi_wb_i2c_master_0 -pg 1 -lvl 9 -y 440 -defaultsOSRD
preplace inst axi_wb_i2c_master_2 -pg 1 -lvl 9 -y 660 -defaultsOSRD
preplace inst axi_uartlite_0 -pg 1 -lvl 3 -y 790 -defaultsOSRD
preplace inst axi_interconnect_0 -pg 1 -lvl 6 -y 350 -defaultsOSRD
preplace inst axi_interconnect_1 -pg 1 -lvl 8 -y 820 -defaultsOSRD
preplace inst rst_wrc_1p_kintex7_0_62M -pg 1 -lvl 7 -y 760 -defaultsOSRD
preplace inst processing_system7_0_axi_periph -pg 1 -lvl 2 -y 470 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 7 -y 400 -defaultsOSRD
preplace netloc osc100_clk_i_1 1 0 9 NJ 940 NJ 940 820J 530 1120J 570 NJ 570 1840J 540 2170J 630 NJ 630 3110J
preplace inst axi_interconnect_0 -pg 1 -lvl 6 -y 540 -defaultsOSRD
preplace inst axi_interconnect_1 -pg 1 -lvl 8 -y 560 -defaultsOSRD
preplace inst util_ds_buf_0 -pg 1 -lvl 9 -y 1550 -defaultsOSRD
preplace inst rst_wrc_1p_kintex7_0_62M -pg 1 -lvl 7 -y 530 -defaultsOSRD
preplace inst processing_system7_0_axi_periph -pg 1 -lvl 2 -y 480 -defaultsOSRD
preplace inst processing_system7_0 -pg 1 -lvl 7 -y 250 -defaultsOSRD
preplace netloc osc100_clk_i_1 1 0 9 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ 970 NJ
preplace netloc axi_wb_i2c_master_0_i2c_master 1 9 1 NJ
preplace netloc fasec_hwtest_0_led_col_pl_o 1 9 1 NJ
preplace netloc dig_in4_n_i_1 1 0 9 NJ 1100 NJ 1100 NJ 1100 NJ 1100 NJ 1100 NJ 1100 NJ 1100 NJ 1100 NJ
preplace netloc processing_system7_0_FIXED_IO 1 7 3 NJ 330 NJ 330 NJ
preplace netloc dig_in4_n_i_1 1 0 9 NJ 1310 NJ 1310 NJ 1310 NJ 1310 NJ 1310 NJ 1310 NJ 1310 NJ 1310 NJ
preplace netloc processing_system7_0_FIXED_IO 1 7 3 NJ 180 NJ 180 NJ
preplace netloc fasec_hwtest_0_dig_outs_i 1 9 1 NJ
preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1570 NJ 1570 NJ 1570 NJ 1570 NJ 1570 NJ 1570 NJ 1570 NJ 1570 3040J
preplace netloc gtp_dedicated_clk_n_i_1 1 0 9 NJ 1960 NJ 1960 NJ 1960 NJ 1960 NJ 1960 NJ 1960 NJ 1960 NJ 1960 NJ
preplace netloc wrc_1p_kintex7_0_dac_din_o 1 9 1 NJ
preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 NJ 1550 3200J
preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 3220 1220 3600
preplace netloc wrc_1p_kintex7_0_pps_o 1 8 2 3210 1230 3620
preplace netloc axi_uartlite_0_tx 1 3 7 1120 580 1430J 510 NJ 510 2250J 550 2670J 490 NJ 490 3610
preplace netloc dig_in3_n_i_1 1 0 9 NJ 1080 NJ 1080 NJ 1080 NJ 1080 NJ 1080 NJ 1080 NJ 1080 NJ 1080 NJ
preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 20J 890 NJ 890 790J 520 1160J 530 NJ 530 1790J 500 2230J 590 NJ 590 3090J
preplace netloc dig_in1_i_1 1 0 9 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ 1040 NJ
preplace netloc xlconcat_0_dout 1 6 1 2220
preplace netloc gtp_dedicated_clk_p_i_1 1 0 9 NJ 1940 NJ 1940 NJ 1940 NJ 1940 NJ 1940 NJ 1940 NJ 1940 NJ 1940 NJ
preplace netloc wrc_1p_kintex7_0_clk_rx_rbclk_o 1 8 2 2900 1440 3330
preplace netloc wrc_1p_kintex7_0_pps_o 1 8 2 2870 1680 3280
preplace netloc axi_uartlite_0_tx 1 3 7 1050 1470 NJ 1470 NJ 1470 NJ 1470 NJ 1470 NJ 1470 3270
preplace netloc dig_in3_n_i_1 1 0 9 NJ 1290 NJ 1290 NJ 1290 NJ 1290 NJ 1290 NJ 1290 NJ 1290 NJ 1290 NJ
preplace netloc FMC1_PRSNTM2C_n_i_1 1 0 9 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ 1110 NJ
preplace netloc dig_in1_i_1 1 0 9 NJ 1250 NJ 1250 NJ 1250 NJ 1250 NJ 1250 NJ 1250 NJ 1250 NJ 1250 NJ
preplace netloc xlconcat_0_dout 1 6 1 2020
preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_P_o 1 9 1 NJ
preplace netloc pb_gp_i_1 1 0 9 10J 1580 NJ 1580 NJ 1580 NJ 1580 NJ 1580 NJ 1580 NJ 1580 NJ 1580 3030
preplace netloc pb_gp_i_1 1 0 9 NJ 1230 NJ 1230 NJ 1230 NJ 1230 NJ 1230 NJ 1230 NJ 1230 NJ 1230 2800
preplace netloc wrc_1p_kintex7_0_dac_sclk_o 1 9 1 NJ
preplace netloc fasec_hwtest_0_led_line_pl_o 1 9 1 NJ
preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 720J 330 1130J 280 1420
preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1860 180 NJ 180 NJ 180 NJ 180 3630
preplace netloc processing_system7_0_DDR 1 7 3 NJ 310 NJ 310 NJ
preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 NJ 1020 3020J
preplace netloc processing_system7_0_axi_periph_M06_AXI 1 2 3 720 680 NJ 680 1310J
preplace netloc axi_wb_i2c_master_2_axi_int_o 1 5 5 1700 690 NJ 690 2440J 730 2810J 530 3340
preplace netloc processing_system7_0_DDR 1 7 3 NJ 160 NJ 160 NJ
preplace netloc FMC1_CLK0M2C_N_i_1 1 0 9 NJ 1150 NJ 1150 NJ 1150 NJ 1150 NJ 1150 NJ 1150 NJ 1150 NJ 1150 NJ
preplace netloc wrc_1p_kintex7_0_dac_cs2_n_o 1 9 1 NJ
preplace netloc axi_wb_i2c_master_2_i2c_master 1 9 1 NJ
preplace netloc axi_interconnect_1_M00_AXI 1 8 1 3070
preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 0J 900 NJ 900 770J 490 1170J 540 NJ 540 1820J 490 2240J 620 NJ 620 3080J
preplace netloc axi_interconnect_1_M00_AXI 1 8 1 2790
preplace netloc FMC2_CLK0M2C_N_i_1 1 0 9 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ 1030 NJ
preplace netloc xlconstant_1_dout 1 8 1 NJ
preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 2 730J 370 1150
preplace netloc processing_system7_0_axi_periph_M05_AXI 1 2 2 750 490 NJ
preplace netloc fasec_hwtest_0_dig_out6_n 1 9 1 NJ
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 20 680 380J 730 810J 700 1140J 800 NJ 800 NJ 800 2210 860 2660
preplace netloc FMC2_PRSNTM2C_n_i_1 1 0 9 30J 920 NJ 920 830J 540 1110J 560 NJ 560 NJ 560 2190J 570 NJ 570 3140J
preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 N
preplace netloc xadc_wiz_0_M_AXIS 1 3 1 1160
preplace netloc processing_system7_0_axi_periph_M03_AXI 1 2 7 NJ 460 1140J 250 NJ 250 1800J 230 NJ 230 NJ 230 3180
preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 NJ 440 1120J 240 NJ 240 1790J 170 NJ 170 NJ 170 3170
preplace netloc xadc_axis_fifo_adapter_0_M_AXIS 1 4 1 N
preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 720
preplace netloc fasec_hwtest_0_intr_led_o 1 5 5 1850 190 NJ 190 NJ 190 NJ 190 3640
preplace netloc wrc_1p_kintex7_0_gtp0_synced_led_o 1 8 2 3210 300 3670
preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 8 30 670 390J 740 750J 690 NJ 690 NJ 690 1680J 670 2030 430 2460
preplace netloc FMC2_PRSNTM2C_n_i_1 1 0 9 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ 990 NJ
preplace netloc xadc_wiz_0_M_AXIS 1 3 1 1050
preplace netloc rst_wrc_1p_kintex7_0_62M_interconnect_aresetn 1 7 1 2440
preplace netloc processing_system7_0_axi_periph_M02_AXI 1 2 7 710 930 NJ 930 NJ 930 NJ 930 NJ 930 NJ 930 NJ
preplace netloc xadc_axis_fifo_adapter_0_M_AXIS 1 4 1 1300
preplace netloc processing_system7_0_axi_periph_M07_AXI 1 2 1 700
preplace netloc fasec_hwtest_0_intr_led_o 1 5 5 1700 1460 NJ 1460 NJ 1460 NJ 1460 3260
preplace netloc wrc_1p_kintex7_0_gtp0_synced_led_o 1 8 2 2860 1650 3300
preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_N_o 1 9 1 NJ
preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2700 680 3060J
preplace netloc clk_25m_vcxo_i_1 1 0 9 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 NJ 1530 3050
preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 1820
preplace netloc wrc_1p_kintex7_0_gtp0_link_led_o 1 8 2 3200 290 3680
preplace netloc rst_wrc_1p_kintex7_0_62M_peripheral_aresetn 1 7 2 2470 2080 2840J
preplace netloc clk_25m_vcxo_i_1 1 0 9 NJ 1920 NJ 1920 NJ 1920 NJ 1920 NJ 1920 NJ 1920 NJ 1920 NJ 1920 2790
preplace netloc axi_dma_0_M_AXI_S2MM 1 5 1 1660
preplace netloc wrc_1p_kintex7_0_gtp0_link_led_o 1 8 2 2850 1660 3290
preplace netloc fasec_hwtest_0_FMC2_CLK0C2M_P_o 1 9 1 NJ
preplace netloc xlconstant_2_dout 1 8 1 2810
preplace netloc Vaux2_1 1 0 3 NJ 150 NJ 150 NJ
preplace netloc Vp_Vn_1 1 0 3 NJ 90 NJ 90 NJ
preplace netloc fasec_hwtest_0_FMC1_CLK0C2M_N_o 1 9 1 NJ
preplace netloc fasec_hwtest_0_watchdog_pl_o 1 9 1 NJ
preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 1 780
preplace netloc processing_system7_0_axi_periph_M01_AXI 1 2 7 710J 420 NJ 420 NJ 420 NJ 420 NJ 420 NJ 420 N
preplace netloc fasec_hwtest_0_dig_out5_n 1 9 1 NJ
preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 10J 880 NJ 880 740J 500 1180J 520 NJ 520 NJ 520 2210J 580 NJ 580 3100J
preplace netloc FMC1_CLK0M2C_P_i_1 1 0 9 NJ 1130 NJ 1130 NJ 1130 NJ 1130 NJ 1130 NJ 1130 NJ 1130 NJ 1130 NJ
preplace netloc Vaux0_1 1 0 3 NJ 110 NJ 110 NJ
preplace netloc Net 1 9 1 NJ
preplace netloc Net10 1 9 1 NJ
preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 1160 640 NJ 640 1800J 530 2180J 640 NJ 640 3120J 660 3590
preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 0 650 400 200 750 380 1180 270 1430 270 1840 220 2250 250 2680 410 3160
preplace netloc Net1 1 9 1 NJ
preplace netloc wrc_1p_kintex7_0_uart_txd_o 1 3 7 1060 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 NJ 1630 3260
preplace netloc processing_system7_0_FCLK_CLK0 1 0 9 20 660 370 220 730 500 1060 430 1320 430 1690 400 2010 400 2480 700 2830
preplace netloc Net11 1 9 1 NJ
preplace netloc axi_wb_i2c_master_1_i2c_master 1 9 1 NJ
preplace netloc Net2 1 9 1 NJ
preplace netloc fasec_hwtest_0_intr_o 1 5 5 1870 200 NJ 200 NJ 200 NJ 200 3620
preplace netloc fasec_hwtest_0_intr_o 1 5 5 1690 1450 NJ 1450 NJ 1450 NJ 1450 3270
preplace netloc Net3 1 9 1 NJ
preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 390
preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 NJ 400 1110J 230 NJ 230 1780J 160 NJ 160 NJ 160 3190
preplace netloc rst_processing_system7_0_100M_interconnect_aresetn 1 1 1 380
preplace netloc processing_system7_0_axi_periph_M00_AXI 1 2 7 NJ 410 NJ 410 NJ 410 NJ 410 NJ 410 NJ 410 2820
preplace netloc fasec_hwtest_0_led_line_en_pl_o 1 9 1 NJ
preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2260 870 2720 650 NJ 650 3660
preplace netloc wrc_1p_kintex7_0_s00_axi_aclk_o 1 6 4 2040 630 2460 1670 NJ 1670 3320
preplace netloc Net4 1 9 1 NJ
preplace netloc Vaux8_1 1 0 3 NJ 170 NJ 170 NJ
preplace netloc wrc_1p_kintex7_0_gtp0_activity_led_o 1 8 2 3220 320 3650
preplace netloc wrc_1p_kintex7_0_gtp0_activity_led_o 1 8 2 2880 1640 3310
preplace netloc Net5 1 9 1 NJ
preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 1110 220 NJ 220 1810J
preplace netloc xadc_wiz_0_ip2intc_irpt 1 3 3 1040 770 NJ 770 NJ
preplace netloc Net6 1 9 1 NJ
preplace netloc Net7 1 9 1 NJ
preplace netloc dig_in2_i_1 1 0 9 NJ 1060 NJ 1060 NJ 1060 NJ 1060 NJ 1060 NJ 1060 NJ 1060 NJ 1060 NJ
preplace netloc axi_uartlite_0_interrupt 1 3 3 1170 700 NJ 700 NJ
preplace netloc dig_in2_i_1 1 0 9 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ 1270 NJ
preplace netloc axi_uartlite_0_interrupt 1 3 3 1030 830 NJ 830 NJ
preplace netloc Vaux10_1 1 0 3 NJ 210 NJ 210 NJ
preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 410 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 2660
preplace netloc wrc_1p_kintex7_0_clk_ref_o 1 8 2 3200 1290 3580
preplace netloc xlconstant_0_dout 1 8 1 3100J
preplace netloc processing_system7_0_M_AXI_GP0 1 1 7 400 10 NJ 10 NJ 10 NJ 10 NJ 10 NJ 10 2490
preplace netloc wrc_1p_kintex7_0_clk_ref_o 1 8 2 2890 1430 3340
preplace netloc xlconstant_0_dout 1 8 1 2820J
preplace netloc Vaux1_1 1 0 3 NJ 130 NJ 130 NJ
preplace netloc Vaux9_1 1 0 3 NJ 190 NJ 190 NJ
preplace netloc axi_dma_0_s2mm_introut 1 5 1 1780
preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 1 710
preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 370 180 760 390 1170 260 1440 260 1830 210 NJ 210 2690 430 3130
preplace netloc FMC2_CLK0M2C_P_i_1 1 0 9 -10J 910 NJ 910 800J 510 1140J 550 NJ 550 NJ 550 2200J 560 NJ 560 3150J
preplace netloc axi_dma_0_s2mm_introut 1 5 1 1660
preplace netloc processing_system7_0_axi_periph_M04_AXI 1 2 1 700
preplace netloc rst_processing_system7_0_100M_peripheral_aresetn 1 1 8 400 810 740 700 1030 670 1320 680 1670 660 NJ 660 2490 710 2840
preplace netloc FMC2_CLK0M2C_P_i_1 1 0 9 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ 1010 NJ
preplace netloc wrc_1p_kintex7_0_dac_cs1_n_o 1 9 1 NJ
preplace netloc wrc_1p_kintex7_0_gtp_wr 1 9 1 NJ
preplace netloc S00_AXI_1 1 7 1 2710
preplace netloc axi_interconnect_0_M00_AXI 1 6 1 2170
preplace netloc axi_wb_i2c_master_0_axi_int_o 1 3 3 N 630 NJ 630 1780J
levelinfo -pg 1 -30 200 560 970 1300 1610 2020 2460 2870 3400 3700 -top 0 -bot 1880
preplace netloc S00_AXI_1 1 7 1 2490
preplace netloc axi_interconnect_0_M00_AXI 1 6 1 2000
preplace netloc axi_wb_i2c_master_0_axi_int_o 1 5 5 1690 680 NJ 680 2450J 720 2800J 520 3340
levelinfo -pg 1 0 200 550 890 1180 1490 1850 2240 2640 3080 3360 -top 0 -bot 2260
",
}
{
......
FASEC_prototype.srcs/tcl/set_registers.tcl
View file @ 7775770f
......@@ -73,14 +73,17 @@ reset_run $runname
# it's using VHDL-2008, fileset property is not persisent
set_property vhdl_version vhdl_2008 [get_filesets $ipname]
eval launch_runs $runname -jobs 4 $_remote
# after BD IP update, the below runs also need rerunning..
foreach a [get_runs *auto_pc_?_synth_1] {
# after BD IP update, other runs might also need rerunning..
foreach a [get_runs *_synth_1] {
if {[get_property PROGRESS [get_runs $a]] != "100%"} {
reset_run $a
eval launch_runs $a -jobs 4 $_remote
wait_on_run $a
}
}
# FIXME: we should iterate over all runs to see if they have finished..
# the above 'wait_on_run $a' fixes that but does then inhibit parallel job running - acceptable only if on fast remote
wait_on_run $runname
# eval concatenates its arguments in the same fashion as concat, and hands them to the interpreter to be evaluated as a Tcl script
......
FASEC_prototype.xpr
View file @ 7775770f
......@@ -131,9 +131,7 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
......@@ -142,9 +140,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
<Step Id="opt_design">
<Option Id="Verbose">1</Option>
......
syn/fasec_prototype_project-generation.tcl
View file @ 7775770f
......@@ -3,7 +3,7 @@
#
# fasec_prototype_project-generation.tcl: Tcl script for re-creating project 'FASEC_prototype'
#
# Generated by Vivado on Tue Jun 26 20:45:25 CEST 2018
# Generated by Vivado on Wed Jul 25 07:58:14 CEST 2018
# IP Build 2185939 on Wed Apr 4 20:55:05 MDT 2018
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
......@@ -211,6 +211,7 @@ proc cr_bd_system_design { parentCell } {
user.org:user:fasec_hwtest:3.2.8\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:util_ds_buf:2.1\
CERN:wrc:wrc_1p_kintex7:3.2.1\
xilinx.com:user:xadc_axis_fifo_adapter:1.0\
xilinx.com:ip:xadc_wiz:3.3\
......@@ -278,8 +279,8 @@ proc cr_bd_system_design { parentCell } {
set Vaux10 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux10 ]
set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ]
set gtp_wr [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 gtp_wr ]
set i2c_master_fmc_fp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_master_fmc_fp ]
set i2c_master_fmcx [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_master_fmcx ]
set i2c_master_mdio [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_master_mdio ]
# Create ports
set FMC1_CLK0C2M_N_o [ create_bd_port -dir O FMC1_CLK0C2M_N_o ]
......@@ -316,6 +317,8 @@ proc cr_bd_system_design { parentCell } {
set led_col_pl_o [ create_bd_port -dir O -from 3 -to 0 led_col_pl_o ]
set led_line_en_pl_o [ create_bd_port -dir O led_line_en_pl_o ]
set led_line_pl_o [ create_bd_port -dir O led_line_pl_o ]
set mdio_spi_N [ create_bd_port -dir IO -from 0 -to 0 mdio_spi_N ]
set mdio_spi_P [ create_bd_port -dir IO -from 0 -to 0 mdio_spi_P ]
set osc100_clk_i [ create_bd_port -dir I osc100_clk_i ]
set pb_gp_i [ create_bd_port -dir I pb_gp_i ]
set thermo_id [ create_bd_port -dir IO thermo_id ]
......@@ -355,24 +358,20 @@ proc cr_bd_system_design { parentCell } {
set axi_wb_i2c_master_0 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.2.0 axi_wb_i2c_master_0 ]
set_property -dict [ list \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.NUM_READ_OUTSTANDING {1} \
CONFIG.NUM_WRITE_OUTSTANDING {1} \
CONFIG.MAX_BURST_LENGTH {1} \
] [get_bd_intf_pins /axi_wb_i2c_master_0/s00_axi]
# Create instance: axi_wb_i2c_master_1, and set properties
set axi_wb_i2c_master_1 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.2.0 axi_wb_i2c_master_1 ]
set_property -dict [ list \
CONFIG.NUM_READ_OUTSTANDING {1} \
CONFIG.NUM_WRITE_OUTSTANDING {1} \
] [get_bd_intf_pins /axi_wb_i2c_master_1/s00_axi]
# Create instance: axi_wb_i2c_master_2, and set properties
set axi_wb_i2c_master_2 [ create_bd_cell -type ip -vlnv cern.ch:ip:axi_wb_i2c_master:3.2.0 axi_wb_i2c_master_2 ]
set_property -dict [ list \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.NUM_READ_OUTSTANDING {1} \
CONFIG.NUM_WRITE_OUTSTANDING {1} \
CONFIG.MAX_BURST_LENGTH {1} \
] [get_bd_intf_pins /axi_wb_i2c_master_2/s00_axi]
# Create instance: fasec_hwtest_0, and set properties
......@@ -383,8 +382,10 @@ proc cr_bd_system_design { parentCell } {
] $fasec_hwtest_0
set_property -dict [ list \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.NUM_READ_OUTSTANDING {1} \
CONFIG.NUM_WRITE_OUTSTANDING {1} \
CONFIG.MAX_BURST_LENGTH {1} \
] [get_bd_intf_pins /fasec_hwtest_0/S00_AXI]
# Create instance: processing_system7_0, and set properties
......@@ -421,11 +422,23 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
CONFIG.PCW_CLK0_FREQ {100000000} \
CONFIG.PCW_CLK1_FREQ {10000000} \
......@@ -436,13 +449,28 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_CORE1_FIQ_INTR {0} \
CONFIG.PCW_CORE1_IRQ_INTR {0} \
CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {800} \
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
CONFIG.PCW_DM_WIDTH {4} \
CONFIG.PCW_DQS_WIDTH {4} \
CONFIG.PCW_DQ_WIDTH {32} \
......@@ -453,11 +481,20 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
CONFIG.PCW_ENET0_RESET_ENABLE {0} \
CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {External} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
CONFIG.PCW_ENET1_RESET_ENABLE {0} \
CONFIG.PCW_ENET_RESET_ENABLE {1} \
CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
......@@ -527,17 +564,37 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_EN_USB1 {0} \
CONFIG.PCW_EN_WDT {0} \
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {10} \
CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \
CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {10} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200} \
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {125} \
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
CONFIG.PCW_FTM_CTI_IN0 {<Select>} \
CONFIG.PCW_FTM_CTI_IN1 {<Select>} \
CONFIG.PCW_FTM_CTI_IN2 {<Select>} \
CONFIG.PCW_FTM_CTI_IN3 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT0 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT1 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT2 {<Select>} \
CONFIG.PCW_FTM_CTI_OUT3 {<Select>} \
CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {0} \
CONFIG.PCW_GP0_NUM_READ_THREADS {4} \
CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \
......@@ -546,6 +603,7 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \
CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
......@@ -561,166 +619,231 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
CONFIG.PCW_I2C1_I2C1_IO {MIO 28 .. 29} \
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \
CONFIG.PCW_I2C_RESET_ENABLE {1} \
CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
CONFIG.PCW_MIO_0_DIRECTION {out} \
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_0_PULLUP {disabled} \
CONFIG.PCW_MIO_0_SLEW {slow} \
CONFIG.PCW_MIO_10_DIRECTION {inout} \
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_10_PULLUP {disabled} \
CONFIG.PCW_MIO_10_SLEW {slow} \
CONFIG.PCW_MIO_11_DIRECTION {inout} \
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_11_PULLUP {disabled} \
CONFIG.PCW_MIO_11_SLEW {slow} \
CONFIG.PCW_MIO_12_DIRECTION {inout} \
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_12_PULLUP {disabled} \
CONFIG.PCW_MIO_12_SLEW {slow} \
CONFIG.PCW_MIO_13_DIRECTION {inout} \
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_13_PULLUP {disabled} \
CONFIG.PCW_MIO_13_SLEW {slow} \
CONFIG.PCW_MIO_14_DIRECTION {inout} \
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_14_PULLUP {enabled} \
CONFIG.PCW_MIO_14_SLEW {slow} \
CONFIG.PCW_MIO_15_DIRECTION {inout} \
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_15_PULLUP {enabled} \
CONFIG.PCW_MIO_15_SLEW {slow} \
CONFIG.PCW_MIO_16_DIRECTION {out} \
CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_16_PULLUP {disabled} \
CONFIG.PCW_MIO_16_SLEW {fast} \
CONFIG.PCW_MIO_17_DIRECTION {out} \
CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_17_PULLUP {disabled} \
CONFIG.PCW_MIO_17_SLEW {fast} \
CONFIG.PCW_MIO_18_DIRECTION {out} \
CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_18_PULLUP {disabled} \
CONFIG.PCW_MIO_18_SLEW {fast} \
CONFIG.PCW_MIO_19_DIRECTION {out} \
CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_19_PULLUP {disabled} \
CONFIG.PCW_MIO_19_SLEW {fast} \
CONFIG.PCW_MIO_1_DIRECTION {out} \
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_1_PULLUP {disabled} \
CONFIG.PCW_MIO_1_SLEW {slow} \
CONFIG.PCW_MIO_20_DIRECTION {out} \
CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_20_PULLUP {disabled} \
CONFIG.PCW_MIO_20_SLEW {fast} \
CONFIG.PCW_MIO_21_DIRECTION {out} \
CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_21_PULLUP {disabled} \
CONFIG.PCW_MIO_21_SLEW {fast} \
CONFIG.PCW_MIO_22_DIRECTION {in} \
CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_22_PULLUP {disabled} \
CONFIG.PCW_MIO_22_SLEW {fast} \
CONFIG.PCW_MIO_23_DIRECTION {in} \
CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_23_PULLUP {disabled} \
CONFIG.PCW_MIO_23_SLEW {fast} \
CONFIG.PCW_MIO_24_DIRECTION {in} \
CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_24_PULLUP {disabled} \
CONFIG.PCW_MIO_24_SLEW {fast} \
CONFIG.PCW_MIO_25_DIRECTION {in} \
CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_25_PULLUP {disabled} \
CONFIG.PCW_MIO_25_SLEW {fast} \
CONFIG.PCW_MIO_26_DIRECTION {in} \
CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_26_PULLUP {disabled} \
CONFIG.PCW_MIO_26_SLEW {fast} \
CONFIG.PCW_MIO_27_DIRECTION {in} \
CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_27_PULLUP {disabled} \
CONFIG.PCW_MIO_27_SLEW {fast} \
CONFIG.PCW_MIO_28_DIRECTION {inout} \
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_28_PULLUP {disabled} \
CONFIG.PCW_MIO_28_SLEW {fast} \
CONFIG.PCW_MIO_29_DIRECTION {inout} \
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_29_PULLUP {disabled} \
CONFIG.PCW_MIO_29_SLEW {fast} \
CONFIG.PCW_MIO_2_DIRECTION {inout} \
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_2_PULLUP {disabled} \
CONFIG.PCW_MIO_2_SLEW {slow} \
CONFIG.PCW_MIO_30_DIRECTION {inout} \
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_30_PULLUP {enabled} \
CONFIG.PCW_MIO_30_SLEW {fast} \
CONFIG.PCW_MIO_31_DIRECTION {inout} \
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_31_PULLUP {enabled} \
CONFIG.PCW_MIO_31_SLEW {fast} \
CONFIG.PCW_MIO_32_DIRECTION {inout} \
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_32_PULLUP {enabled} \
CONFIG.PCW_MIO_32_SLEW {slow} \
CONFIG.PCW_MIO_33_DIRECTION {inout} \
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_33_PULLUP {enabled} \
CONFIG.PCW_MIO_33_SLEW {slow} \
CONFIG.PCW_MIO_34_DIRECTION {inout} \
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_34_PULLUP {enabled} \
CONFIG.PCW_MIO_34_SLEW {slow} \
CONFIG.PCW_MIO_35_DIRECTION {inout} \
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_35_PULLUP {enabled} \
CONFIG.PCW_MIO_35_SLEW {slow} \
CONFIG.PCW_MIO_36_DIRECTION {inout} \
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_36_PULLUP {enabled} \
CONFIG.PCW_MIO_36_SLEW {slow} \
CONFIG.PCW_MIO_37_DIRECTION {inout} \
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_37_PULLUP {enabled} \
CONFIG.PCW_MIO_37_SLEW {slow} \
CONFIG.PCW_MIO_38_DIRECTION {inout} \
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_38_PULLUP {disabled} \
CONFIG.PCW_MIO_38_SLEW {fast} \
CONFIG.PCW_MIO_39_DIRECTION {inout} \
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_39_PULLUP {disabled} \
CONFIG.PCW_MIO_39_SLEW {fast} \
CONFIG.PCW_MIO_3_DIRECTION {inout} \
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_3_PULLUP {disabled} \
CONFIG.PCW_MIO_3_SLEW {slow} \
CONFIG.PCW_MIO_40_DIRECTION {inout} \
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_40_PULLUP {disabled} \
CONFIG.PCW_MIO_40_SLEW {slow} \
CONFIG.PCW_MIO_41_DIRECTION {inout} \
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_41_PULLUP {disabled} \
CONFIG.PCW_MIO_41_SLEW {slow} \
CONFIG.PCW_MIO_42_DIRECTION {inout} \
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_42_PULLUP {disabled} \
CONFIG.PCW_MIO_42_SLEW {slow} \
CONFIG.PCW_MIO_43_DIRECTION {inout} \
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_43_PULLUP {disabled} \
CONFIG.PCW_MIO_43_SLEW {slow} \
CONFIG.PCW_MIO_44_DIRECTION {inout} \
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_44_PULLUP {disabled} \
CONFIG.PCW_MIO_44_SLEW {slow} \
CONFIG.PCW_MIO_45_DIRECTION {inout} \
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_45_PULLUP {disabled} \
CONFIG.PCW_MIO_45_SLEW {slow} \
CONFIG.PCW_MIO_46_DIRECTION {in} \
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_46_PULLUP {enabled} \
CONFIG.PCW_MIO_46_SLEW {slow} \
CONFIG.PCW_MIO_47_DIRECTION {in} \
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_47_PULLUP {enabled} \
CONFIG.PCW_MIO_47_SLEW {slow} \
CONFIG.PCW_MIO_48_DIRECTION {inout} \
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_48_PULLUP {disabled} \
CONFIG.PCW_MIO_48_SLEW {slow} \
CONFIG.PCW_MIO_49_DIRECTION {inout} \
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_49_PULLUP {disabled} \
CONFIG.PCW_MIO_49_SLEW {slow} \
CONFIG.PCW_MIO_4_DIRECTION {inout} \
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_4_PULLUP {disabled} \
CONFIG.PCW_MIO_4_SLEW {slow} \
CONFIG.PCW_MIO_50_DIRECTION {inout} \
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_50_PULLUP {enabled} \
CONFIG.PCW_MIO_50_SLEW {slow} \
CONFIG.PCW_MIO_51_DIRECTION {inout} \
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_51_PULLUP {enabled} \
CONFIG.PCW_MIO_51_SLEW {slow} \
CONFIG.PCW_MIO_52_DIRECTION {out} \
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_52_PULLUP {disabled} \
CONFIG.PCW_MIO_52_SLEW {slow} \
CONFIG.PCW_MIO_53_DIRECTION {inout} \
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_53_PULLUP {enabled} \
CONFIG.PCW_MIO_53_SLEW {slow} \
CONFIG.PCW_MIO_5_DIRECTION {inout} \
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_5_PULLUP {disabled} \
CONFIG.PCW_MIO_5_SLEW {slow} \
CONFIG.PCW_MIO_6_DIRECTION {out} \
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_6_PULLUP {disabled} \
CONFIG.PCW_MIO_6_SLEW {slow} \
CONFIG.PCW_MIO_7_DIRECTION {out} \
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_7_PULLUP {disabled} \
CONFIG.PCW_MIO_7_SLEW {slow} \
CONFIG.PCW_MIO_8_DIRECTION {out} \
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_8_PULLUP {disabled} \
CONFIG.PCW_MIO_8_SLEW {slow} \
CONFIG.PCW_MIO_9_DIRECTION {out} \
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_9_PULLUP {disabled} \
CONFIG.PCW_MIO_9_SLEW {slow} \
......@@ -742,6 +865,8 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_NAND_CYCLES_T_RR {1} \
CONFIG.PCW_NAND_CYCLES_T_WC {11} \
CONFIG.PCW_NAND_CYCLES_T_WP {1} \
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_NOR_CS0_T_CEOE {1} \
CONFIG.PCW_NOR_CS0_T_PC {1} \
CONFIG.PCW_NOR_CS0_T_RC {11} \
......@@ -756,6 +881,13 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_NOR_CS1_T_WC {11} \
CONFIG.PCW_NOR_CS1_T_WP {1} \
CONFIG.PCW_NOR_CS1_WE_TIME {0} \
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
......@@ -771,12 +903,33 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
CONFIG.PCW_P2F_CAN0_INTR {0} \
CONFIG.PCW_P2F_CAN1_INTR {0} \
CONFIG.PCW_P2F_CTI_INTR {0} \
CONFIG.PCW_P2F_DMAC0_INTR {0} \
CONFIG.PCW_P2F_DMAC1_INTR {0} \
CONFIG.PCW_P2F_DMAC2_INTR {0} \
CONFIG.PCW_P2F_DMAC3_INTR {0} \
CONFIG.PCW_P2F_DMAC4_INTR {0} \
CONFIG.PCW_P2F_DMAC5_INTR {0} \
CONFIG.PCW_P2F_DMAC6_INTR {0} \
CONFIG.PCW_P2F_DMAC7_INTR {0} \
CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
CONFIG.PCW_P2F_ENET0_INTR {0} \
CONFIG.PCW_P2F_ENET1_INTR {0} \
CONFIG.PCW_P2F_GPIO_INTR {0} \
CONFIG.PCW_P2F_I2C0_INTR {0} \
CONFIG.PCW_P2F_I2C1_INTR {0} \
CONFIG.PCW_P2F_QSPI_INTR {0} \
CONFIG.PCW_P2F_SDIO0_INTR {0} \
CONFIG.PCW_P2F_SDIO1_INTR {0} \
CONFIG.PCW_P2F_SMC_INTR {0} \
CONFIG.PCW_P2F_SPI0_INTR {0} \
CONFIG.PCW_P2F_SPI1_INTR {0} \
CONFIG.PCW_P2F_UART0_INTR {0} \
CONFIG.PCW_P2F_UART1_INTR {0} \
CONFIG.PCW_P2F_USB0_INTR {0} \
CONFIG.PCW_P2F_USB1_INTR {0} \
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.109} \
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.098} \
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.100} \
......@@ -787,6 +940,7 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.015} \
CONFIG.PCW_PACKAGE_NAME {ffg676} \
CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
......@@ -802,6 +956,7 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFDFFFFFF} \
CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {8} \
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {125} \
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
......@@ -812,10 +967,16 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_SD0_GRP_WP_IO {MIO 47} \
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {40} \
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {25} \
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
CONFIG.PCW_SMC_CYCLE_T0 {NA} \
......@@ -826,46 +987,102 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_SMC_CYCLE_T5 {NA} \
CONFIG.PCW_SMC_CYCLE_T6 {NA} \
CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
CONFIG.PCW_UART0_BAUD_RATE {115200} \
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
CONFIG.PCW_UART1_BAUD_RATE {115200} \
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_UART_PERIPHERAL_VALID {0} \
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
CONFIG.PCW_UIPARAM_DDR_AL {0} \
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
CONFIG.PCW_UIPARAM_DDR_BL {8} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.310} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.310} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.368} \
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.368} \
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
CONFIG.PCW_UIPARAM_DDR_CL {7} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {97.8165} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
......@@ -879,6 +1096,9 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {97.8165} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {119.765} \
CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
......@@ -907,18 +1127,35 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {113.5445} \
CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333333} \
CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125} \
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
CONFIG.PCW_UIPARAM_DDR_T_RC {48.75} \
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NONE} \
CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_USB0_RESET_ENABLE {0} \
CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_USB1_RESET_ENABLE {0} \
CONFIG.PCW_USB_RESET_ENABLE {0} \
CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
......@@ -928,11 +1165,13 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_USE_CR_FABRIC {1} \
CONFIG.PCW_USE_DDR_BYPASS {0} \
CONFIG.PCW_USE_DEBUG {0} \
CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
CONFIG.PCW_USE_DMA0 {0} \
CONFIG.PCW_USE_DMA1 {0} \
CONFIG.PCW_USE_DMA2 {0} \
CONFIG.PCW_USE_DMA3 {0} \
CONFIG.PCW_USE_EXPANDED_IOP {0} \
CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.PCW_USE_HIGH_OCM {0} \
CONFIG.PCW_USE_M_AXI_GP0 {1} \
......@@ -947,10 +1186,12 @@ proc cr_bd_system_design { parentCell } {
CONFIG.PCW_USE_S_AXI_HP2 {0} \
CONFIG.PCW_USE_S_AXI_HP3 {0} \
CONFIG.PCW_USE_TRACE {0} \
CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
CONFIG.PCW_VALUE_SILVERSION {3} \
CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
] $processing_system7_0
# Create instance: processing_system7_0_axi_periph, and set properties
......@@ -967,12 +1208,21 @@ proc cr_bd_system_design { parentCell } {
# Create instance: rst_wrc_1p_kintex7_0_62M, and set properties
set rst_wrc_1p_kintex7_0_62M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_wrc_1p_kintex7_0_62M ]
# Create instance: util_ds_buf_0, and set properties
set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ]
set_property -dict [ list \
CONFIG.C_BUF_TYPE {IOBUFDS} \
CONFIG.C_SIZE {1} \
] $util_ds_buf_0
# Create instance: wrc_1p_kintex7_0, and set properties
set wrc_1p_kintex7_0 [ create_bd_cell -type ip -vlnv CERN:wrc:wrc_1p_kintex7:3.2.1 wrc_1p_kintex7_0 ]
set_property -dict [ list \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.NUM_READ_OUTSTANDING {1} \
CONFIG.NUM_WRITE_OUTSTANDING {1} \
CONFIG.MAX_BURST_LENGTH {1} \
] [get_bd_intf_pins /wrc_1p_kintex7_0/s00_axi]
# Create instance: xadc_axis_fifo_adapter_0, and set properties
......@@ -1033,8 +1283,13 @@ proc cr_bd_system_design { parentCell } {
] [get_bd_intf_pins /xadc_wiz_0/M_AXIS]
set_property -dict [ list \
CONFIG.HAS_WSTRB {1} \
CONFIG.HAS_BRESP {1} \
CONFIG.HAS_RRESP {1} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.NUM_READ_OUTSTANDING {1} \
CONFIG.NUM_WRITE_OUTSTANDING {1} \
CONFIG.MAX_BURST_LENGTH {1} \
] [get_bd_intf_pins /xadc_wiz_0/s_axi_lite]
# Create instance: xlconcat_0, and set properties
......@@ -1056,6 +1311,9 @@ proc cr_bd_system_design { parentCell } {
CONFIG.CONST_WIDTH {1} \
] $xlconstant_1
# Create instance: xlconstant_2, and set properties
set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ]
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP1]
connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_ports Vaux0] [get_bd_intf_pins xadc_wiz_0/Vaux0]
......@@ -1068,7 +1326,7 @@ proc cr_bd_system_design { parentCell } {
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_dma_0/M_AXI_S2MM] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_GP0]
connect_bd_intf_net -intf_net axi_interconnect_1_M00_AXI [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins wrc_1p_kintex7_0/s00_axi]
connect_bd_intf_net -intf_net axi_wb_i2c_master_1_i2c_master [get_bd_intf_ports i2c_master_mdio] [get_bd_intf_pins axi_wb_i2c_master_1/i2c_master]
connect_bd_intf_net -intf_net axi_wb_i2c_master_0_i2c_master [get_bd_intf_ports i2c_master_fmc_fp] [get_bd_intf_pins axi_wb_i2c_master_0/i2c_master]
connect_bd_intf_net -intf_net axi_wb_i2c_master_2_i2c_master [get_bd_intf_ports i2c_master_fmcx] [get_bd_intf_pins axi_wb_i2c_master_2/i2c_master]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
......@@ -1076,7 +1334,6 @@ proc cr_bd_system_design { parentCell } {
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_wb_i2c_master_2/s00_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_wb_i2c_master_0/s00_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M02_AXI [get_bd_intf_pins fasec_hwtest_0/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M02_AXI]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_wb_i2c_master_1/s00_axi] [get_bd_intf_pins processing_system7_0_axi_periph/M03_AXI]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M04_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M04_AXI] [get_bd_intf_pins xadc_wiz_0/s_axi_lite]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M05_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M05_AXI] [get_bd_intf_pins xadc_axis_fifo_adapter_0/S_AXI]
connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M06_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins processing_system7_0_axi_periph/M06_AXI]
......@@ -1092,6 +1349,8 @@ proc cr_bd_system_design { parentCell } {
connect_bd_net -net FMC2_CLK0M2C_N_i_1 [get_bd_ports FMC2_CLK0M2C_N_i] [get_bd_pins fasec_hwtest_0/FMC2_CLK0M2C_N_i]
connect_bd_net -net FMC2_CLK0M2C_P_i_1 [get_bd_ports FMC2_CLK0M2C_P_i] [get_bd_pins fasec_hwtest_0/FMC2_CLK0M2C_P_i]
connect_bd_net -net FMC2_PRSNTM2C_n_i_1 [get_bd_ports FMC2_PRSNTM2C_n_i] [get_bd_pins fasec_hwtest_0/FMC2_PRSNTM2C_n_i]
connect_bd_net -net Net [get_bd_ports mdio_spi_P] [get_bd_pins util_ds_buf_0/IOBUF_DS_P]
connect_bd_net -net Net1 [get_bd_ports mdio_spi_N] [get_bd_pins util_ds_buf_0/IOBUF_DS_N]
connect_bd_net -net Net2 [get_bd_ports eeprom_scl] [get_bd_pins wrc_1p_kintex7_0/fpga_scl_b]
connect_bd_net -net Net3 [get_bd_ports eeprom_sda] [get_bd_pins wrc_1p_kintex7_0/fpga_sda_b]
connect_bd_net -net Net4 [get_bd_ports FMC2_LA_P_b] [get_bd_pins fasec_hwtest_0/FMC2_LA_P_b]
......@@ -1127,10 +1386,10 @@ proc cr_bd_system_design { parentCell } {
connect_bd_net -net gtp_dedicated_clk_p_i_1 [get_bd_ports gtp_dedicated_clk_p_i] [get_bd_pins wrc_1p_kintex7_0/gtp_dedicated_clk_p_i]
connect_bd_net -net osc100_clk_i_1 [get_bd_ports osc100_clk_i] [get_bd_pins fasec_hwtest_0/osc100_clk_i]
connect_bd_net -net pb_gp_i_1 [get_bd_ports pb_gp_i] [get_bd_pins fasec_hwtest_0/pb_gp_n_i] [get_bd_pins wrc_1p_kintex7_0/button_rst_n_i]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_wb_i2c_master_0/s00_axi_aclk] [get_bd_pins axi_wb_i2c_master_1/s00_axi_aclk] [get_bd_pins axi_wb_i2c_master_2/s00_axi_aclk] [get_bd_pins fasec_hwtest_0/ps_clk_i] [get_bd_pins fasec_hwtest_0/s00_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/M01_ACLK] [get_bd_pins processing_system7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0_axi_periph/M03_ACLK] [get_bd_pins processing_system7_0_axi_periph/M04_ACLK] [get_bd_pins processing_system7_0_axi_periph/M05_ACLK] [get_bd_pins processing_system7_0_axi_periph/M06_ACLK] [get_bd_pins processing_system7_0_axi_periph/M07_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins rst_processing_system7_0_100M/slowest_sync_clk] [get_bd_pins xadc_axis_fifo_adapter_0/M_AXIS_ACLK] [get_bd_pins xadc_axis_fifo_adapter_0/S_AXIS_ACLK] [get_bd_pins xadc_axis_fifo_adapter_0/S_AXI_ACLK] [get_bd_pins xadc_wiz_0/s_axi_aclk] [get_bd_pins xadc_wiz_0/s_axis_aclk]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_wb_i2c_master_0/s00_axi_aclk] [get_bd_pins axi_wb_i2c_master_2/s00_axi_aclk] [get_bd_pins fasec_hwtest_0/ps_clk_i] [get_bd_pins fasec_hwtest_0/s00_axi_aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/M01_ACLK] [get_bd_pins processing_system7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0_axi_periph/M03_ACLK] [get_bd_pins processing_system7_0_axi_periph/M04_ACLK] [get_bd_pins processing_system7_0_axi_periph/M05_ACLK] [get_bd_pins processing_system7_0_axi_periph/M06_ACLK] [get_bd_pins processing_system7_0_axi_periph/M07_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins rst_processing_system7_0_100M/slowest_sync_clk] [get_bd_pins xadc_axis_fifo_adapter_0/M_AXIS_ACLK] [get_bd_pins xadc_axis_fifo_adapter_0/S_AXIS_ACLK] [get_bd_pins xadc_axis_fifo_adapter_0/S_AXI_ACLK] [get_bd_pins xadc_wiz_0/s_axi_aclk] [get_bd_pins xadc_wiz_0/s_axis_aclk]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_processing_system7_0_100M/ext_reset_in] [get_bd_pins rst_wrc_1p_kintex7_0_62M/ext_reset_in]
connect_bd_net -net rst_processing_system7_0_100M_interconnect_aresetn [get_bd_pins processing_system7_0_axi_periph/ARESETN] [get_bd_pins rst_processing_system7_0_100M/interconnect_aresetn]
connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_wb_i2c_master_0/s00_axi_aresetn] [get_bd_pins axi_wb_i2c_master_1/s00_axi_aresetn] [get_bd_pins axi_wb_i2c_master_2/s00_axi_aresetn] [get_bd_pins fasec_hwtest_0/s00_axi_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M01_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M02_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M03_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M04_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M05_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M06_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M07_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn] [get_bd_pins xadc_axis_fifo_adapter_0/AXIS_RESET_N] [get_bd_pins xadc_axis_fifo_adapter_0/S_AXI_ARESETN] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
connect_bd_net -net rst_processing_system7_0_100M_peripheral_aresetn [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_wb_i2c_master_0/s00_axi_aresetn] [get_bd_pins axi_wb_i2c_master_2/s00_axi_aresetn] [get_bd_pins fasec_hwtest_0/s00_axi_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M01_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M02_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M03_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M04_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M05_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M06_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M07_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_processing_system7_0_100M/peripheral_aresetn] [get_bd_pins xadc_axis_fifo_adapter_0/AXIS_RESET_N] [get_bd_pins xadc_axis_fifo_adapter_0/S_AXI_ARESETN] [get_bd_pins xadc_wiz_0/s_axi_aresetn]
connect_bd_net -net rst_wrc_1p_kintex7_0_62M_interconnect_aresetn [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins rst_wrc_1p_kintex7_0_62M/interconnect_aresetn]
connect_bd_net -net rst_wrc_1p_kintex7_0_62M_peripheral_aresetn [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins rst_wrc_1p_kintex7_0_62M/peripheral_aresetn] [get_bd_pins wrc_1p_kintex7_0/s00_axi_aresetn]
connect_bd_net -net wrc_1p_kintex7_0_clk_ref_o [get_bd_pins fasec_hwtest_0/FMC1_GP0_i] [get_bd_pins wrc_1p_kintex7_0/clk_ref_o]
......@@ -1149,6 +1408,7 @@ proc cr_bd_system_design { parentCell } {
connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout]
connect_bd_net -net xlconstant_0_dout [get_bd_pins fasec_hwtest_0/gem_status_vector_i] [get_bd_pins xlconstant_0/dout]
connect_bd_net -net xlconstant_1_dout [get_bd_pins wrc_1p_kintex7_0/pps_i] [get_bd_pins xlconstant_1/dout]
connect_bd_net -net xlconstant_2_dout [get_bd_pins util_ds_buf_0/IOBUF_IO_I] [get_bd_pins util_ds_buf_0/IOBUF_IO_T] [get_bd_pins xlconstant_2/dout]
# Create address segments
create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM
......@@ -1157,7 +1417,6 @@ proc cr_bd_system_design { parentCell } {
create_bd_addr_seg -range 0x00010000 -offset 0x40400000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] SEG_axi_dma_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x42C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_wb_i2c_master_0/s00_axi/Reg] SEG_axi_wb_i2c_master_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_wb_i2c_master_1/s00_axi/Reg] SEG_axi_wb_i2c_master_1_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_wb_i2c_master_2/s00_axi/Reg] SEG_axi_wb_i2c_master_2_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs fasec_hwtest_0/S00_AXI/S00_AXI_reg] SEG_fasec_hwtest_0_S00_AXI_reg
create_bd_addr_seg -range 0x00010000 -offset 0x80000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs wrc_1p_kintex7_0/s00_axi/Reg] SEG_wrc_1p_kintex7_0_Reg
......@@ -1169,6 +1428,8 @@ proc cr_bd_system_design { parentCell } {
current_bd_instance $oldCurInst
save_bd_design
common::send_msg_id "BD_TCL-1000" "WARNING" "This Tcl script was generated from a block design that has not been validated. It is possible that design <$design_name> may result in errors during validation."
close_bd_design $design_name
}
# End of cr_bd_system_design()
......@@ -1398,6 +1659,7 @@ if { $obj != "" } {
}
set obj [get_runs impl_1]
set_property -name "needs_refresh" -value "1" -objects $obj
set_property -name "part" -value "xc7z030ffg676-2" -objects $obj
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.opt_design.args.verbose" -value "1" -objects $obj
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment