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FPGA and ARM SoC FMC Carrier FASEC
Commit b2a8f4f0 authored by Pieter Van Trappen's avatar Pieter Van Trappen
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fasec_hwtest IP was old and obsolete, updated; all output files generated

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FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd
View file @ b2a8f4f0
--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
--Date : Tue Jun 26 19:07:23 2018
--Date : Tue Jun 26 20:45:41 2018
--Host : lapte24154 running 64-bit openSUSE Leap 42.3
--Command : generate_target system_design_wrapper.bd
--Design : system_design_wrapper
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
View file @ b2a8f4f0
......@@ -7,7 +7,7 @@
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>system_design_fasec_hwtest_0_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.7"/>
<spirit:componentRef spirit:vendor="user.org" spirit:library="user" spirit:name="fasec_hwtest" spirit:version="3.2.8"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S00_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
......@@ -65,7 +65,7 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">35</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">37</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
View file @ b2a8f4f0
......@@ -1399,7 +1399,7 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>fasec_hwtest</xilinx:displayName>
<xilinx:coreRevision>35</xilinx:coreRevision>
<xilinx:coreRevision>37</xilinx:coreRevision>
<xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:1.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:2.0_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
......@@ -1432,7 +1432,8 @@
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.4_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.5_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.6_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.7_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/cores/FASEC_hwtest</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.7_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/FASEC_prototype/ip_cores/cores/FASEC_hwtest</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:fasec_hwtest:3.2.8_ARCHIVE_LOCATION">/home/pieter/Development/projects/FIDS/FASEC_prototype/ip_cores/cores/FASEC_hwtest</xilinx:tag>
</xilinx:tags>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S00_AXI.ADDR_WIDTH" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
......@@ -1467,13 +1468,13 @@
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2016.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="92ed6682"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="6bf44be4"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="85b35840"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="fe85f838"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="455aa684"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="f383f867"/>
<xilinx:xilinxVersion>2018.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="e26110fd"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="e4009ebe"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bc4d2a4c"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="4d3e81cb"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="2668e947"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="985a3c93"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd
View file @ b2a8f4f0
......@@ -1217,7 +1217,7 @@
</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>fasec_hwtest_0</spirit:instanceName>
<spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.7"/>
<spirit:componentRef spirit:library="user" spirit:name="fasec_hwtest" spirit:vendor="user.org" spirit:version="3.2.8"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="bd:xciName">system_design_fasec_hwtest_0_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="g_FMC1">EDA-03287</spirit:configurableElementValue>
......
FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml
View file @ b2a8f4f0
......@@ -2,10 +2,10 @@
<Root MajorVersion="0" MinorVersion="35">
<CompositeFile CompositeFileTopName="system_design" CanBeSetAsTop="false" CanDisplayChildGraph="true">
<Description>Composite Fileset</Description>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1530033539"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1530033539"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1530033539"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1530033539"/>
<Generation Name="SYNTHESIS" State="RESET" Timestamp="1530039884"/>
<Generation Name="IMPLEMENTATION" State="RESET" Timestamp="1530039884"/>
<Generation Name="SIMULATION" State="RESET" Timestamp="1530039884"/>
<Generation Name="HW_HANDOFF" State="RESET" Timestamp="1530039884"/>
<FileCollection Name="SOURCES" Type="SOURCES">
<File Name="ip/system_design_processing_system7_0_0/system_design_processing_system7_0_0.xci" Type="IP">
<Instance HierarchyPath="processing_system7_0"/>
......
FASEC_prototype.srcs/tcl/set_registers.tcl
View file @ b2a8f4f0
......@@ -73,8 +73,14 @@ reset_run $runname
# it's using VHDL-2008, fileset property is not persisent
set_property vhdl_version vhdl_2008 [get_filesets $ipname]
eval launch_runs $runname -jobs 4 $_remote
# after BD IP update, the below run also might need rerunning..
if {[get_property PROGRESS [get_runs system_design_auto_pc_0_synth_1]] != "100%"} { eval launch_runs system_design_auto_pc_0_synth_1 -jobs 4 $_remote }
# after BD IP update, the below runs also need rerunning..
foreach a [get_runs *auto_pc_?_synth_1] {
if {[get_property PROGRESS [get_runs $a]] != "100%"} {
reset_run $a
eval launch_runs $a -jobs 4 $_remote
}
}
wait_on_run $runname
# eval concatenates its arguments in the same fashion as concat, and hands them to the interpreter to be evaluated as a Tcl script
......
FASEC_prototype.xpr
View file @ b2a8f4f0
......@@ -41,13 +41,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="93"/>
<Option Name="WTModelSimExportSim" Val="93"/>
<Option Name="WTQuestaExportSim" Val="93"/>
<Option Name="WTIesExportSim" Val="93"/>
<Option Name="WTVcsExportSim" Val="93"/>
<Option Name="WTRivieraExportSim" Val="93"/>
<Option Name="WTActivehdlExportSim" Val="93"/>
<Option Name="WTXSimExportSim" Val="96"/>
<Option Name="WTModelSimExportSim" Val="96"/>
<Option Name="WTQuestaExportSim" Val="96"/>
<Option Name="WTIesExportSim" Val="96"/>
<Option Name="WTVcsExportSim" Val="96"/>
<Option Name="WTRivieraExportSim" Val="96"/>
<Option Name="WTActivehdlExportSim" Val="96"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
......@@ -131,7 +131,9 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
......@@ -140,7 +142,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design">
<Option Id="Verbose">1</Option>
......
cores @ 55810b7d
Subproject commit 0e406a2e84dc8f47a06e85430288b375ab560c04
Subproject commit 55810b7d4b7efda486cb66cfe30c943547f47b45
ip_upgrade.log
View file @ b2a8f4f0
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
| Date : Tue Jun 26 20:33:30 2018
| Host : lapte24154 running 64-bit openSUSE Leap 42.3
| Command : upgrade_ip
| Device : xc7z030ffg676-2
------------------------------------------------------------------------------------
Upgrade Log for IP 'system_design_fasec_hwtest_0_0'
1. Summary
----------
SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 (user.org:user:fasec_hwtest:3.2.8) from (Rev. 36) to (Rev. 37)
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
| Date : Tue Jun 26 20:26:05 2018
| Host : lapte24154 running 64-bit openSUSE Leap 42.3
| Command : upgrade_ip
| Device : xc7z030ffg676-2
------------------------------------------------------------------------------------
Upgrade Log for IP 'system_design_fasec_hwtest_0_0'
1. Summary
----------
SUCCESS in the upgrade of system_design_fasec_hwtest_0_0 from user.org:user:fasec_hwtest:3.2.7 (Rev. 35) to user.org:user:fasec_hwtest:3.2.8 (Rev. 36)
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (lin64) Build 2188600 Wed Apr 4 18:39:19 MDT 2018
......
syn/fasec_prototype_project-generation.tcl
View file @ b2a8f4f0
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