<RunId="impl_1"Type="Ft2:EntireDesign"Part="xc7z030ffg676-2"ConstrsSet="constrs_1"Description="Default settings for Implementation."WriteIncrSynthDcp="false"State="current"Dir="$PRUNDIR/impl_1"SynthRun="synth_1"IncludeInArchive="true">
common::send_msg_id "BD_TCL-006""INFO""Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if {$ip_obj eq ""}{
lappend list_ips_missing $ip_vlnv
}
}
if {$list_ips_missing ne ""}{
catch {common::send_msg_id "BD_TCL-115""ERROR""The following IPs are not found in the IP Catalog:\n$list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project."}
set bCheckIPsPassed 0
}
}
if {$bCheckIPsPassed != 1 }{
common::send_msg_id "BD_TCL-1003""WARNING""Will not continue with creation of design due to the error(s) above."
return 3
}
variable script_folder
if {$parentCell eq ""}{
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if {$parentObj == ""}{
catch {common::send_msg_id "BD_TCL-100""ERROR""Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if {$parentType ne "hier"}{
catch {common::send_msg_id "BD_TCL-101""ERROR""Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
set Vaux0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 ]
set Vaux1 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1 ]
set Vaux2 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux2 ]
set Vaux8 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 ]
set Vaux9 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9 ]
set Vaux10 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux10 ]
set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ]
set gtp_wr [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 gtp_wr ]
set i2c_master_fmcx [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_master_fmcx ]
set i2c_master_mdio [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 i2c_master_mdio ]
# Create ports
set FMC1_CLK0C2M_N_o [ create_bd_port -dir O FMC1_CLK0C2M_N_o ]
set FMC1_CLK0C2M_P_o [ create_bd_port -dir O FMC1_CLK0C2M_P_o ]
set FMC1_CLK0M2C_N_i [ create_bd_port -dir I FMC1_CLK0M2C_N_i ]
set FMC1_CLK0M2C_P_i [ create_bd_port -dir I FMC1_CLK0M2C_P_i ]
