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FPGA and ARM SoC FMC Carrier FASEC
Commit 96664c9d authored by Pieter Van Trappen's avatar Pieter Van Trappen
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after synthesis

parent f38fc372
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FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
View file @ 96664c9d
......@@ -480,7 +480,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Oct 11 10:21:17 UTC 2017</spirit:value>
<spirit:value>Wed Oct 11 13:10:29 UTC 2017</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>boundaryCRC</spirit:name>
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.v
View file @ 96664c9d
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
// Date : Wed Oct 11 12:21:16 2017
// Date : Wed Oct 11 15:10:28 2017
// Host : lapte24154 running 64-bit openSUSE Leap 42.2
// Command : write_verilog -force -mode synth_stub
// /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.v
......
FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.vhdl
View file @ 96664c9d
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-- Date : Wed Oct 11 12:21:16 2017
-- Date : Wed Oct 11 15:10:28 2017
-- Host : lapte24154 running 64-bit openSUSE Leap 42.2
-- Command : write_vhdl -force -mode synth_stub
-- /home/pieter/Development/projects/FIDS/FASEC_prototype/FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0_stub.vhdl
......
FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_6/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
View file @ 96664c9d
......@@ -294,8 +294,8 @@ begin
s_data(c_FASEC_BASE+1) <= resize(unsigned(s_ins), g_S00_AXI_DATA_WIDTH);
s_data(c_FASEC_BASE+2) <= resize(unsigned(gem_status_vector_i), g_S00_AXI_DATA_WIDTH);
-- s_data(c_FASEC_BASE+3).data used in p_fasec_dio
s_data(c_FASEC_BASE+6) <= x"59DDF043"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"f08bde95"; -- tcl-script will put git commit id
s_data(c_FASEC_BASE+6) <= x"59DE17F0"; -- tcl-script will put unix build time
s_data(c_FASEC_BASE+7) <= x"f38fc372"; -- tcl-script will put git commit id
-- copy in rw data, 'for generate' only possible with constants!
gen_data_readwrite : for i in 0 to c_MEMMAX-1 generate
gen_fasec : if c_FASECMEM(i).ro = '0' generate
......
FASEC_prototype.xpr
View file @ 96664c9d
......@@ -426,7 +426,7 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" SynthRun="synth_1" IncludeInArchive="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
......@@ -441,6 +441,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream" PostStepTclHook="$PSRCDIR/tcl/copy_bitstream.tcl"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="system_design_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z030ffg676-2" ConstrsSet="system_design_processing_system7_0_0" Description="Default settings for Implementation." SynthRun="system_design_processing_system7_0_0_synth_1" IncludeInArchive="false">
<Strategy Version="1" Minor="2">
......
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